Extended Configuration of RX_AACK mode

There are additional configuration options, which allow to customize the operation in RX_AACK mode. This allows for example the indication of frames, which do not match the IEEE 802.15.4-2006 filter rules as well as a specific configuration of the automatic acknowledgement frame transmission. For a detailed description refer to section 5.2.3.1 (RX_AACK Configuration Registers) of the AT86RF212 datasheet.

Parameters:

	safe_mode	Enable {1}/disable {0} usage of dynamic frame buffer protection (see section Dynamic Frame Buffer Protection).
	prom_mode	Enable {1}/disable {0} promiscuous mode (see CFG_IEEE_SNIFFER)
	ack_time	Enable {1}/disable {0} an acknowledgement frame latency of tWaitAck = 2 * tsym (see section Examples for non-IEEE-compliant RX_AACK Configuration).
	upld_res_ft_mode	Enable {1}/disable {0} reserved frame type reception (see section Examples for non-IEEE-compliant RX_AACK Configuration).
	fltr_res_ft	Filter reserved frame types like data frame type (see section Examples for non-IEEE-compliant RX_AACK Configuration).
	dis_ack	Disable automatic generation of acknowledgment (see use case CFG_IEEE_SNIFFER).
	fvn_mode	Enable {1}/disable {0} processing of IEEE 802.15.4 frame versions, depending on FCF frame version number (see table 5-28 (Frame Version Subfield dependent Frame Acknowledgment) of the AT86RF212 datasheet).

Additional Parameters:

panid, short_addr, ext_addr: Set address filter parameters of the node, see section Address Filter.
slmode: Enable {1}/disable {0} slotted acknowledgment transmission, see section Extended Frame Receive Procedure (RX_AACK).
coord: Enable {1}/disable {0} coordinator specific address filter behaviour, see PHY_CONFIG_RX_AACK.
pendd: Set pending data flag in the FCF of an automatically generated acknowledgement frame, see use cases PHY_SET_PD, PHY_SET_PD_BUSY.

Use Cases:

PHY_CFG_RX_AACK_EXT

Code example

    /* AT86RF212::[CONFIG] && MCU::[Frame Handling] */
    trx_bit_write(SR_RX_SAFE_MODE, safe_mode);
    trx_bit_write(SR_AACK_PROM_MODE, prom_mode);
    trx_bit_write(SR_AACK_ACK_TIME, ack_time);
    trx_bit_write(SR_AACK_UPLD_RES_FT, upld_res_ft);
    trx_bit_write(SR_AACK_FLTR_RES_FT, fltr_res_ft);
    trx_bit_write(SR_AACK_DIS_ACK, dis_ack);
    trx_bit_write(SR_AACK_FVN_MODE, fvn_mode);
    trx_bit_write(SR_AACK_SET_PD, pendd);
    /* MCU::[Addr. Filter] */
    trx_reg_write(RG_PAN_ID_0, panid_7_0);
    trx_reg_write(RG_PAN_ID_1, panid_15_8);
    trx_reg_write(RG_SHORT_ADDR_0, short_addr_7_0);
    trx_reg_write(RG_SHORT_ADDR_1, short_addr_15_8);
    trx_reg_write(RG_IEEE_ADDR_0, ext_addr_7_0);
    trx_reg_write(RG_IEEE_ADDR_1, ext_addr_15_8);
    trx_reg_write(RG_IEEE_ADDR_2, ext_addr_23_16);
    trx_reg_write(RG_IEEE_ADDR_3, ext_addr_31_24);
    trx_reg_write(RG_IEEE_ADDR_4, ext_addr_39_32);
    trx_reg_write(RG_IEEE_ADDR_5, ext_addr_47_40);
    trx_reg_write(RG_IEEE_ADDR_6, ext_addr_55_48);
    trx_reg_write(RG_IEEE_ADDR_7, ext_addr_63_56);
    /* MCU::[Network] */
    trx_bit_write(SR_AACK_I_AM_COORD, coord);
    trx_bit_write(SR_SLOTTED_OPERATION, slmode);