Frame Transmit Procedure (TX)

For transmission of frames in the Basic Operating Mode, the radio transceiver needs to be in the state PLL_ON (see also section Transitions to State PLL_ON).

Frame transmit start commands:
There are two methods to initiate a frame transmission, either with a rising edge on the pin TRX_PIN_SLP_TR (pin start) or by writing CMD_TX_START to sub register SR_TRX_CMD (register start) .

After the frame start command, the radio transceiver sends out the IEEE 802.15.4 synchronization header (SHR), which consists of 4 octets preamble and 1 octet start-of-frame delimitter (SFD). The transmission of the whole SHR takes tSHR. After SHR, PHR, and PSDU have been transmitted, the TRX_IRQ_TRX_END interrupt indicates the completion of the transmission.

Timing constraints for frame transmission:
If the SPI data rate is higher than the data rate of the air interface, the frame can be downloaded after the transmit start command has been issued. In this case the following conditions need to be met:

The PHR must be available in the frame buffer before (tTR10+tSHR).
The last byte of the PSDU must be available in the frame buffer at latest
T = tSHR + toct *(len(PHR) + len(PSDU) - 1).

If one of the above conditions is violated, a TRX_IRQ_TRX_UR interrupt occurs and the frame was incorrectly transmitted (see PHY_EVENT_TRX_UR_TX).

Parameters:

frame

Before a frame transmission, the PHR field and the PSDU have to be stored in the frame buffer. The PHR field contains the PSDU length information (bit 0:6, bit 7 is reserved) and the PSDU contains the payload. The maximum PSDU length is 127. If the sub register SR_TX_AUTO_CRC_ON is set to 1, the last two bytes (FCS bytes) of the PSDU do not need to be downloaded, because the FCS is calculated internally by the radio transceiver (see also PHY_SET_TX_AUTO_CRC). The frame is stored in the frame buffer of the radio transceiver in the following way:

        0   1   2                     L-2 L-1  L
      +--- --- --- --- --- --- ~~~~~~ --- --- ---+
      | P | D | D | D | D | D |      | D |D/F|D/F|
      +--- --- --- --- --- --- ~~~~~~ --- --- ---+
      |                                          |
      |<--- access via "SRAM Write Access" ----->|
      |                                          |
      |<--- access via "Frame Write Access" ---->|

        P   : PHR field containing the PSDU length information L
        D,F : data byte, F = FCS byte (D and F belong to the PSDU)

Use Cases:

PHY_DATA_REQUEST_PINSTART

This sequence describes a frame transmission, which is initiated by a rising edge on pin TRX_PIN_SLP_TR. If the timing constraint cannot be ensured, the frame shall be downloaded before the pin TRX_PIN_SLP_TR is toggled. After the last byte of the frame has been sent out, the TRX_IRQ_TRX_END interrupt is generated confirming that the frame was sent correctly.

Code example

    /* AT86RF212::PLL_ON */
    trx_pinset_slptr(1);
    trx_pinset_slptr(0);
    /* AT86RF212::BUSY_TX */
    trx_frame_write(len(frame), frame);
    /* TRX_IRQ_TRX_END occurs here */
    /* AT86RF212::PLL_ON */

PHY_DATA_REQUEST_REGSTART

This sequence describes a frame transmission, which is initiated by writing the command CMD_TX_START to sub register SR_TRX_CMD. If the timing constraint cannot be ensured, the frame shall be downloaded before the value CMD_TX_START is written to sub register SR_TRX_CMD. After the last byte of the frame has been sent out, the TRX_IRQ_TRX_END interrupt is generated confirming that the frame was sent correctly.

Code example

    /* AT86RF212::PLL_ON */
    trx_bit_write(SR_TRX_CMD, CMD_TX_START);
    /* AT86RF212::BUSY_TX */
    trx_frame_write(len(frame), frame);
    /* TRX_IRQ_TRX_END occurs here */
    /* AT86RF212::PLL_ON */