Transceiver Access Primitives

The following section describes the basic radio transceiver access primitives:

Register Access

Registers

The radio transceiver has a set of registers, which are used for configuration, reading status information, and initiating transactions.

All registers in the AT86RF212 are 8 bit wide and they can be accessed with a single SPI command (see section 4.3 (SPI Protocol) of the AT86RF212 datasheet). An overview of all registers can be found in chapter 12 (Register Reference) of the AT86RF212 datasheet.

The functions trx_reg_read() and trx_reg_write() implement the SPI packet structure for reading and writing the radio transceiver registers.

Additionaly, the RG_<XYZ> macros contain the addresses of all registers.

SPI packet structure for trx_reg_read()

SPI packet structure for trx_reg_write()

Handling of Multibyte Variables

The following example shows the notation, which is used to describe, how multibyte variables are splitted into byte variables, which are used in the sequences for the Extended Operating Mode configuration.

      uint64_t var;
      uint8_t var_7_0   = var & 0xff          // bit 7:0
      uint8_t var_15_8  = (var >> 8) & 0xff   // bit 15:8
      uint8_t var_23_16 = (var >> 16) & 0xff  // bit 23:16
      uint8_t var_31_24 = (var >> 24) & 0xff  // bit 31:24
      uint8_t var_39_32 = (var >> 32) & 0xff  // bit 39:32
      uint8_t var_47_40 = (var >> 40) & 0xff  // bit 47:40
      uint8_t var_55_48 = (var >> 48) & 0xff  // bit 55:48
      uint8_t var_63_56 = (var >> 56) & 0xff  // bit 63:56

Sub Registers

A sub register is a single bit or a group of adjacent bits within an 8 bit register. It represents a logical value in the radio transceiver, e.g. a power level, a channel number or an interrupt flag. Sub registers are accessed with the functions trx_bit_read() and trx_bit_write(), which perform 8 bit register accesses and do the multiplexing and masking. The SR_<XYZ> macros contain the offset values, masks and shift values for accessing sub registers in the radio transceiver.

For some of the sub registers, there exist predefined constants which assign symbolic names to numeric values (e.g. TRX_OFF, PLL_ON, RX_ON and SLEEP as state names for the sub register SR_TRX_STATUS).

Example 1 for sub register SR_TRX_STATUS

This example defines the five bit sub register SR_TRX_STATUS, which is located in the register RG_TRX_STATUS.

   #define SR_TRX_STATUS   0x01, 0x1f, 0

       -------------------------------
      | Register 0x01:  RG_TRX_STATUS |
       --- --- --- --- --- --- --- ---
      |   |   |   | v   v   v   v   v |
       --- --- --- --- --- --- --- ---
        7   6   5   4   3   2   1   0
                  [===================]---> SR_TRX_STATUS

                   offset = 0x01
                   mask   = 0x1f
                   shift  =    0

Example 2 for sub register SR_TX_AUTO_CRC_ON

This example defines the single bit sub register SR_TX_AUTO_CRC_ON, which is located in the register RG_TRX_CTRL_1.

    #define SR_TX_AUTO_CRC_ON   0x04, 0x20, 5

       -------------------------------
      | Register 0x04:  RG_TRX_CTRL_1 |
       --- --- --- --- --- --- --- ---
      |   |   | v |   |   |   |   |   |
       --- --- --- --- --- --- --- ---
        7   6   5   4   3   2   1   0
      --------[===]-----------------------> SR_TX_AUTO_CRC_ON

                   offset = 0x04
                   mask   = 0x20
                   shift  =    5

Frame Buffer Access

Frame Buffer Access Mode

The 128-byte frame buffer can store a single IEEE 802.15.4 compliant PHY packet, consisting of PHY Header (PHR) and PHY Payload (PSDU: PHY service data unit) at a time, see also section 4.3.2 (Frame Buffer Access Mode) of the AT86RF212 datasheet.

Note:: The synchronization header (SHR) of the PHY packet is generated/detected automatically from the radio transceiver in TX or RX mode and is not stored in the frame buffer.

If a frame has to be stored in the radio transceiver for transmission, the function trx_frame_write() is used. A received frame can be read from the radio transceiver by the MCU with the function trx_frame_read().

SPI packet structure for trx_frame_read()

SPI packet structure for trx_frame_write()

Frame Buffer Read with Empty Indicator

If a frame has to be read from the radio transceiver while the reception process is in progress (e.g. if the frame upload has to start with the TRX_IRQ_RX_START in order to meet IEEE 802.15.4 ACK timing), the "empty indicator" feature of the radio transceiver can be used. It is described in section Frame Buffer Empty Indicator. The empty indication is signaled via the TRX_PIN_IRQ line, which is asserted, if the frame buffer gets empty. The function trx_frame_read_blm() implements this feature.

SRAM Access Mode

Memory Map of the SRAM

The following graphic illustrates the logical organization of the SRAM:

      +------ ------ ~~~~~~ ------+------ ------+------ ------ ~~~~~~ ------ ------+
      | 0x00 | 0x01 |      | 0x7F | 0x80 | 0x81 | 0x82 | 0x83 |      | 0x93 | 0x94 |
      +------ ------ ~~~~~~ ------+------ ------+------ ------ ~~~~~~ ------ ------+
      | Frame Buffer (1)          | reserved    | AES Block (1,2)                  |
      +------ ------ ~~~~~~ ------+------ ------+------ ------ ~~~~~~ ------ ------+

The different blocks are accessed with different SPI packet structures.

(1) accessable with the functions trx_sram_read(), trx_sram_write().
(2) accessable with the functions trx_aes_read(), trx_aes_write(), trx_aes_wrrd().

Note:: Although the frame buffer and the AES block have consecutive SRAM addresses, they cannot be read in one block.

SRAM Access

The SRAM is subdivided into a radio transceiver section [0x00...0x7F] and an AES section [0x82...0x94]. The former can be accessed using trx_sram_read() and trx_sram_write(), whereas the latter can be accessed using trx_aes_write(), trx_aes_read() and trx_aes_wrrd(). However, the AES-functions trx_aes_*() internally use functions trx_sram_*(). The AES functions are provided in this document for a simplified access to the AES block.

SPI packet structure for trx_sram_read()

SPI packet structure for trx_sram_write()

AES Block Access and Fast SRAM Access

The AES block has a special SPI packet structure, which is shown below. In order to use the AES block, the following functions can be used:

trx_aes_write() for AES access 0
trx_aes_wrrd() for AES access [1...n]
trx_aes_read() for AES access n+1

The fast SRAM access, described in function trx_aes_wrrd(), can only be used for the AES block. This mode allows simultaneously writing new data and reading data from previously processed data within the same SPI transfer.

SPI packet structure for trx_aes_wrrd()

Note:: ^[1] Byte 19 is the mirrored version of register AES_CTRL on SRAM address 0x94, see register description AES_CTRL_MIRROR for details.