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mcu_drv.h

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00001 00002 00003 00004 00005 00006 00007 00008 00009 00010 00011 00012 00013 00014 #ifndef _MCU_DRV_H_ 00015 #define _MCU_DRV_H_ 00016 00017 // ____ I N C L U D E S ____________________________________________________ 00018 00019 00020 // ____ M A C R O S ________________________________________________________ 00021 00022 00023 // ____ D E F I N I T I O N ________________________________________________ 00024 /* INTERRUPT NUMBER */ 00025 00026 #define IRQ_INT0 0 00027 #define IRQ_T0 1 00028 #define IRQ_INT1 2 00029 #define IRQ_T1 3 00030 #define IRQ_UART 4 00031 #define IRQ_T2 5 00032 #define IRQ_PCA 6 00033 #define IRQ_KBD 7 00034 #define IRQ_TWI 8 00035 #define IRQ_SPI 9 00036 #define IRQ_USB 13 00037 00038 /* USB */ 00039 00040 #define MSK_TXCMPL 0x01 /* UEPSTAX */ 00041 #define MSK_RXOUTB0 0x02 00042 #define MSK_RXOUT 0x02 00043 #define MSK_RXSETUP 0x04 00044 #define MSK_STALLED 0x08 00045 #define MSK_TXRDY 0x10 00046 #define MSK_STALLRQ 0x20 00047 #define MSK_RXOUTB1 0x40 00048 #define MSK_DIR 0x80 00049 #define MSK_RXOUTB0B1 0x42 00050 #define MSK_EP_DIR 0x7F 00051 00052 #define MSK_SPINT 0x01 /* USBINT */ 00053 #define MSK_SOFINT 0x08 00054 #define MSK_EORINT 0x10 00055 #define MSK_WUPCPU 0x20 00056 00057 #define MSK_ESPINT 0x01 /* USBIEN */ 00058 #define MSK_ESOFINT 0x08 00059 #define MSK_EEORINT 0x10 00060 #define MSK_EWUPCPU 0x20 00061 00062 #define MSK_USBE 0x80 /* USBCON */ 00063 #define MSK_SUSPCLK 0x40 00064 #define MSK_SDRMWUP 0x20 00065 #define MSK_DETACH 0x10 00066 #define MSK_UPRSM 0x08 00067 #define MSK_RMWUPE 0x04 00068 #define MSK_CONFG 0x02 00069 #define MSK_FADDEN 0x01 00070 00071 #define MSK_FEN 0x80 /* USBADDR */ 00072 00073 #define MSK_EPEN 0x80 /* UEPCONX */ 00074 #define MSK_DTGL 0x08 00075 #define MSK_EPDIR 0x04 00076 #define MSK_EPTYPE1 0x02 00077 #define MSK_EPTYPE0 0x01 00078 00079 #define MSK_EP6RST 0x40 /* UEPRST */ 00080 #define MSK_EP5RST 0x20 00081 #define MSK_EP4RST 0x10 00082 #define MSK_EP3RST 0x08 00083 #define MSK_EP2RST 0x04 00084 #define MSK_EP1RST 0x02 00085 #define MSK_EP0RST 0x01 00086 00087 #define MSK_EP6INTE 0x40 /* UEPIEN */ 00088 #define MSK_EP5INTE 0x20 00089 #define MSK_EP4INTE 0x10 00090 #define MSK_EP3INTE 0x08 00091 #define MSK_EP2INTE 0x04 00092 #define MSK_EP1INTE 0x02 00093 #define MSK_EP0INTE 0x01 00094 00095 #define MSK_CRCOK 0x20 /* UFNUMH */ 00096 #define MSK_CRCERR 0x10 00097 00098 /* SYSTEM MANAGEMENT */ 00099 00100 #define MSK_SMOD1 0x80 /* PCON */ 00101 #define MSK_SMOD0 0x40 00102 #define MSK_POF 0x10 00103 #define MSK_GF1 0x08 00104 #define MSK_GF0 0x04 00105 #define MSK_PD 0x02 00106 #define MSK_IDLE 0x01 00107 00108 #define MSK_DPU 0x80 /* AUXR0 */ 00109 #define MSK_M0 0x20 00110 #define MSK_DPHDIS 0x10 00111 #define MSK_XRS 0x0C 00112 #define MSK_EXTRAM 0x02 00113 #define MSK_AO 0x01 00114 00115 #define MSK_ENBOOT 0x20 /* AUXR1 */ 00116 #define MSK_GF3 0x08 00117 #define MSK_DPS 0x01 00118 00119 00120 /* PLL & CLOCK */ 00121 00122 #define MSK_TWIX2 0x80 /* CKCON0 */ 00123 #define MSK_WDX2 0x40 00124 #define MSK_PCAX2 0x20 00125 #define MSK_SIX2 0x10 00126 #define MSK_T2X2 0x08 00127 #define MSK_T1X2 0x04 00128 #define MSK_T0X2 0x02 00129 #define MSK_X2 0x01 00130 00131 #define MSK_SPIX2 0x01 /* CKCON1 */ 00132 00133 #define MSK_PLOCK 0x01 /* PLLCON */ 00134 #define MSK_PLLEN 0x02 00135 #define MSK_EXT48 0x04 00136 00137 #define MSK_R 0xF0 /* PLLDIV */ 00138 #define MSK_N 0x0F 00139 00140 00141 /* INTERRUPT */ 00142 00143 #define MSK_EC 0x40 /* IEN0 */ 00144 #define MSK_ET2 0x20 00145 #define MSK_ES 0x10 00146 #define MSK_ET1 0x08 00147 #define MSK_EX1 0x04 00148 #define MSK_ET0 0x02 00149 #define MSK_EX0 0x01 00150 00151 #define MSK_EUSB 0x40 /* IEN1 */ 00152 #define MSK_ESPI 0x04 00153 #define MSK_ETWI 0x02 00154 #define MSK_EKB 0x01 00155 00156 00157 /* TIMERS */ 00158 00159 #define MSK_GATE1 0x80 /* TMOD */ 00160 #define MSK_C_T1 0x40 00161 #define MSK_MO1 0x30 00162 #define MSK_GATE0 0x08 00163 #define MSK_C_T0 0x04 00164 #define MSK_MO0 0x03 00165 00166 00167 /* WATCHDOG */ 00168 00169 #define MSK_WTO 0x07 /* WDTPRG*/ 00170 00171 /* SPI CONTROLLER */ 00172 00173 #define MSK_SPR 0x83 /* SPCON */ 00174 #define MSK_SPEN 0x40 00175 #define MSK_SSDIS 0x20 00176 #define MSK_MSTR 0x10 00177 #define MSK_MODE 0x0C 00178 #define MSK_CPOL 0x08 00179 #define MSK_CPHA 0x04 00180 00181 #define MSK_SPIF 0x80 /* SPSTA */ 00182 #define MSK_WCOL 0x40 00183 #define MSK_MODF 0x10 00184 00185 00186 /* TWI CONTROLLER */ 00187 00188 #define MSK_SSCR 0x83 /* SSCON */ 00189 #define MSK_SSPE 0x40 00190 #define MSK_SSSTA 0x20 00191 #define MSK_SSSTO 0x10 00192 #define MSK_SSSI 0x08 00193 #define MSK_SSAA 0x04 00194 00195 00196 /* FLASH */ 00197 00198 #define MSK_FCON_FBUSY 0x01 00199 00200 00201 00202 #define Set_x2_mode() (CKCON0 |= MSK_X2) 00203 #define Set_x1_mode() (CKCON0 &= ~MSK_X2) 00204 #define Mode_x2() ((CKCON0 & MSK_X2) == MSK_X2) 00205 00206 #define Set_timer0_x1_mode() (CKCON0 |= MSK_T0X2) 00207 #define Set_timer0_x2_mode() (CKCON0 &=~MSK_T0X2) 00208 #define Set_timer1_x1_mode() (CKCON0 |= MSK_T1X2) 00209 #define Set_timer1_x2_mode() (CKCON0 &=~MSK_T1X2) 00210 #define Set_timer2_x1_mode() (CKCON0 |= MSK_T2X2) 00211 #define Set_timer2_x2_mode() (CKCON0 &=~MSK_T2X2) 00212 #define Set_uart_x1_mode() (CKCON0 |= MSK_UARTX2) 00213 #define Set_uart_x2_mode() (CKCON0 &=~MSK_UARTX2) 00214 #define Set_pca_x1_mode()() (CKCON0 |= MSK_PCAX2) 00215 #define Set_pca_x2_mode() (CKCON0 &=~MSK_PCAX2) 00216 00217 #define Set_idle_mode() (PCON |= MSK_IDLE) 00218 #define Set_power_down_mode() (PCON |= MSK_PD) 00219 00220 #define Enable_eram() (AUXR &= ~MSK_EXTRAM) 00221 #define Disable_eram() (AUXR |= MSK_EXTRAM) 00222 #define Set_eram_size(s) ((AUXR &= ~MSK_XRS),(AUXR |= s)) 00223 00224 #define Enable_interrupt() (EA = 1) 00225 #define Disable_interrupt() (EA = 0) 00226 00227 #define Enable_usb_interrupt() (IE1 |= MSK_EUSB) 00228 #define Disable_usb_interrupt() (IE1 &= ~MSK_EUSB) 00229 00230 #define Enable_twi_interrupt() (IE1 |= 0x02) 00231 #define Disable_twi_interrupt() (IE1 &= 0xFD) 00232 00233 #define Disable_ale() (AUXR |= MSK_AO) 00234 #define Enable_ale() (AUXR &= ~MSK_AO) 00235 #define Switch_ale() (AUXR ^= MSK_AO) 00236 00237 #define Wdt_immediate_reset() ((WDTRST = 0x1E), \ 00238 (WDTRST = 0xE1), \ 00239 (WDTRST = 0x3C), \ 00240 (WDTRST = 0xC3)) 00241 00242 00243 #endif // _MCU_DRV_H_ 00244 00245

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