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#ifndef _BOARD_H_
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#define _BOARD_H_
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00028 #define VERSION 22 // V2.1 or V2.2
00029
00030 #define INT0_button P3_2
00031
00032 #define NF_WP P1_7
00033 #define Nf_WP_ON() (P1_7 = 0)
00034 #define Nf_WP_OFF() (P1_7 = 1)
00035
00036 #define NF_CE0 0
00037 #define NF_CE1 1
00038 #define NF_CE NF_CE0
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#if(NF_CE == NF_CE0)
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00042 #define NF_IDLE_STATE_ADD 0x3C // Smart Media Card not selected
00043 #define NF_ADD_LATCH_ENABLE_ADD 0x2600 // Address Latch Enable Address
00044 #define NF_CMD_LATCH_ENABLE_ADD 0x2500 // Command Latch Enable Address
00045 #define NF_ADDRESS_CMD_DATA 0x2400 // Command / Data Address register
00046 #define NF_RD_BUSY P2_4
00047 #define Nf_CS_ON() (P2_3 = 0)
00048 #define Nf_CS_OFF() (P2_3 = 1)
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#endif
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#if(NF_CE == NF_CE1)
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#define NF_IDLE_STATE_ADD 0x3C // Smart Media Card not selected
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#define NF_ADD_LATCH_ENABLE_ADD 0x0A00 // Address Latch Enable Address
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#define NF_CMD_LATCH_ENABLE_ADD 0x0900 // Command Latch Enable Address
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#define NF_ADDRESS_CMD_DATA 0x0800 // Command / Data Address register
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#define NF_RD_BUSY P2_2
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#define Nf_CS_ON() (P2_5 = 0)
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#define Nf_CS_OFF() (P2_5 = 1)
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#endif
00061
00062 #define NF_IDLE_STATE_ADD_DOUBLE 0x3C // Idle state for 2 Nand Flash
00063 #define NF_ADD_LATCH_ENABLE_ADD_EVEN 0x6200 // Address Latch Enable Address
00064 #define NF_CMD_LATCH_ENABLE_ADD_EVEN 0x6100 // Command Latch Enable Address
00065 #define NF_ADDRESS_CMD_DATA_EVEN 0x6000 // Command / Data Address register
00066 #define NF_ADD_LATCH_ENABLE_ADD_ODD 0x4A00 // Address Latch Enable Address
00067 #define NF_CMD_LATCH_ENABLE_ADD_ODD 0x4900 // Command Latch Enable Address
00068 #define NF_ADDRESS_CMD_DATA_ODD 0x4800 // Command / Data Address register
00069
00070 #define NF_BSY_ODD P2_2
00071 #define NF_BSY_EVEN P2_4
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00074 #define NF_CS_ODD P2_5
00075 #define NF_CS_EVEN P2_3
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00077 #define NF_EVEN 0
00078 #define NF_ODD 1
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00081 #define Nf_CS_ODD() nf_parity_bit = NF_ODD; NF_CS_EVEN = 1; NF_CS_ODD = 0
00082 #define Nf_CS_EVEN() nf_parity_bit = NF_EVEN; NF_CS_ODD = 1; NF_CS_EVEN = 0
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00084 #define Nf_active_ODD() NF_CS_EVEN = 1; NF_CS_ODD = 0
00085 #define Nf_active_EVEN() NF_CS_ODD = 1; NF_CS_EVEN = 0
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00088 #define NF_128 // Nand Flash Capacity : NF_16 NF_32 NF_64 NF_128
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00092 #define DATA_REGISTER 0x10
00093 #define ERROR_REGISTER 0x11
00094 #define SECTOR_COUNT_REGISTER 0x12
00095 #define SECTOR_NUMBER_REGISTER 0x13
00096 #define CYL_LOW_REGISTER 0x14
00097 #define CYL_HIGH_REGISTER 0x15
00098 #define DRIVE_HEAD_REGISTER 0x16
00099 #define STATUS_COMMAND_REGISTER 0x17
00100 #define ALT_STAT_REGISTER 0x0E
00101 #define DRIVE_REGISTER 0x0F
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00103 #define H_DATA_REGISTER 0x1000
00104 #define H_ERROR_REGISTER 0x1100
00105 #define H_SECTOR_COUNT_REGISTER 0x1200
00106 #define H_SECTOR_NUMBER_REGISTER 0x1300
00107 #define H_CYL_LOW_REGISTER 0x1400
00108 #define H_CYL_HIGH_REGISTER 0x1500
00109 #define H_DRIVE_HEAD_REGISTER 0x1600
00110 #define H_STATUS_COMMAND_REGISTER 0x1700
00111 #define H_ALT_STAT_REGISTER 0x0E00
00112 #define H_DRIVE_REGISTER 0x0F00
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00115 #define DF_CS P2 // dataflash CS# port
00116 #define DF_CS0 P2_3
00117 #define DF_CS1 P2_5
00118 #define DF_CS2 P2_6
00119 #define DF_CS3 P2_6
00120 #define DF_DESEL_ALL ((Byte)0x08) // set CS# dataflash memories
00121 #define DF_NB_MEM 1 // 1 on-board memories
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#endif // _BOARD_H_
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