scif_uc3l.h

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/* Copyright (c) 2009 Atmel Corporation. All rights reserved.
 *
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 *
 * 1. Redistributions of source code must retain the above copyright notice, this
 * list of conditions and the following disclaimer.
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 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
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 * 3. The name of Atmel may not be used to endorse or promote products derived
 * from this software without specific prior written permission.
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 * 4. This software may only be redistributed and used in connection with an Atmel
 * AVR product.
 *
 * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
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#ifndef _SCIF_UC3L_H_
#define _SCIF_UC3L_H_

#ifdef __cplusplus
extern "C" {
#endif

#include "compiler.h"

//  These defines are missing from or wrong in the toolchain header file ip_xxx.h or part.h
#ifdef AVR32_SCIF_100_H_INCLUDED
// Optionnal #undef AVR32_SCIF_GC_NO_DIV_CLOCK if the define values is wrong.
#define AVR32_SCIF_GC_NO_DIV_CLOCK       AVR32_GC_NO_DIV_CLOCK
#endif

#define AVR32_SCIF_OSCCTRL0_OSCEN_ENABLE      0x00000001  
#define AVR32_SCIF_OSCCTRL0_OSCEN_DISABLE     0x00000000  
#define AVR32_SCIF_OSCCTRL32_OSC32EN_ENABLE   0x00000001  
#define AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE  0x00000000  


#if ((__GNUC__ && (__AVR32_UC3L016__ || __AVR32_UC3L032__ || __AVR32_UC3L064__)) \
    ||(__ICCAVR32__ && (__AT32UC3L016__ || __AT32UC3L032__ || __AT32UC3L064__  )))
// NOTE: the #if here above could be removed since we're in a file named scif_uc3l.h

#define SCIF_EXT_CRYSTAL_MIN_FREQ_HZ  4000000
#define SCIF_EXT_CRYSTAL_MAX_FREQ_HZ  20000000

typedef enum
{
  SCIF_GCCTRL_SLOWCLOCK  = AVR32_SCIF_GC_USES_CLK_SLOW,
  SCIF_GCCTRL_CLK32  = AVR32_SCIF_GC_USES_CLK_32,
  SCIF_GCCTRL_DFLL0  = AVR32_SCIF_GC_USES_DFLL0,
  SCIF_GCCTRL_OSC0  = AVR32_SCIF_GC_USES_OSC0,
  SCIF_GCCTRL_RC120M  = AVR32_SCIF_GC_USES_RC120M,
  SCIF_GCCTRL_CPUCLOCK  = AVR32_SCIF_GC_USES_CLK_CPU,
  SCIF_GCCTRL_HSBCLOCK  = AVR32_SCIF_GC_USES_CLK_HSB,
  SCIF_GCCTRL_PBACLOCK  = AVR32_SCIF_GC_USES_CLK_PBA,
  SCIF_GCCTRL_PBBCLOCK  = AVR32_SCIF_GC_USES_CLK_PBB,
  SCIF_GCCTRL_RC32K  = AVR32_SCIF_GC_USES_RC32K,
  SCIF_GCCTRL_CRIPOSC  = AVR32_SCIF_GC_USES_CRIPOSC,
  SCIF_GCCTRL_CLK1K  = AVR32_SCIF_GC_USES_CLK_1K,
  SCIF_GCCTRL_OSCSEL_INVALID
} scif_gcctrl_oscsel_t;

// low frequency clock with high accuracy can be used as reference clock to get
// high accuracy on the output frequency.
typedef enum
{
  SCIF_DFLL_CLKREF_GC_SRC_115KHZ = SCIF_GCCTRL_SLOWCLOCK,
  SCIF_DFLL_CLKREF_GC_SRC_32KHZ = SCIF_GCCTRL_RC32K,
  SCIF_DFLL_CLKREF_GC_SRC_INVALID
} scif_dfll_clkref_t;

#define SCIF_DFLL_MINFREQ_KHZ         20000
#define SCIF_DFLL_MINFREQ_HZ          20000000

#define SCIF_DFLL_MAXFREQ_KHZ         150000
#define SCIF_DFLL_MAXFREQ_HZ          150000000

#define SCIF_SLOWCLOCK_FREQ_HZ        AVR32_SCIF_RCOSC_FREQUENCY
#define SCIF_SLOWCLOCK_FREQ_KHZ       (SCIF_SLOWCLOCK_FREQ_HZ/100)

#define SCIF_RC32K_FREQ_HZ            32768
#define SCIF_RC32K_FREQ_KHZ           (SCIF_RC32K_FREQ_HZ/100)

#define SCIF_RC120M_FREQ_HZ           120000000
#define SCIF_RC120M_FREQ_KHZ          120000

#endif


#define SCIF_POLL_TIMEOUT             100000

#define SCIF_NOT_SUPPORTED            (-10000)


typedef enum
{
  SCIF_OSC0  = 0,
  SCIF_OSC1  = 1
} scif_osc_t;

typedef enum
{
  SCIF_OSC_MODE_EXT_CLK = 0,            // For both OSC0 & OSC32
  SCIF_OSC_MODE_2PIN_CRYSTAL = 1,       // For OSC0 only
  SCIF_OSC_MODE_1PIN_CRYSTAL = 2,       // For OSC32 only
  SCIF_OSC_MODE_NOT_SUPPORTED_1 = 3,
  SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR = 4, // For OSC32 only
  SCIF_OSC_MODE_NOT_SUPPORTED_2 = 5,
  SCIF_OSC_MODE_NOT_SUPPORTED_3 = 6
} scif_osc_mode_t;

typedef struct
{
  unsigned long   freq_hz;
  scif_osc_mode_t mode;
  unsigned char   startup;
  unsigned char   gain;
} scif_osc_opt_t;

typedef struct
{
  scif_osc_mode_t mode;
  unsigned char   startup;
  bool            pinsel;
  bool            en1k;
  bool            en32k;
} scif_osc32_opt_t;


typedef struct
{
  scif_gcctrl_oscsel_t clock_source;
  unsigned int divider;
  unsigned int diven;
} scif_gclk_opt_t;


typedef struct
{
  unsigned int  fine;
  unsigned int  coarse;
} scif_dfll_openloop_conf_t;

typedef struct
{
  unsigned int    coarse;
  unsigned int    fmul;
  unsigned int    maxstep;
} scif_dfll_closedloop_conf_t;

typedef struct
{
  unsigned int    use_random;
  unsigned int    amplitude;
  unsigned int    step_size;
} scif_dfll_ssg_conf_t;


#define SCIF_UNLOCK(reg)  (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)|(reg))



 #if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ void scif_enable_interrupts(unsigned long mask)
{
  AVR32_SCIF.ier = mask;
}

#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ void scif_disable_interrupts(unsigned long mask)
{
  AVR32_SCIF.idr = mask;
}

#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ unsigned long scif_get_enabled_interrupts(void)
{
  return(AVR32_SCIF.imr);
}

#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ unsigned long scif_get_interrupts_status(void)
{
  return(AVR32_SCIF.isr);
}

#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ void scif_clear_interrupts_status(unsigned long mask)
{
  AVR32_SCIF.icr = mask;
}





#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ unsigned long scif_get_pclk_status(void)
{
  return(AVR32_SCIF.pclksr);
}





extern long int scif_start_osc(scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready);

extern bool scif_is_osc_ready(scif_osc_t osc);

extern long int scif_stop_osc(scif_osc_t osc);

extern long int scif_configure_osc_crystalmode(scif_osc_t osc, unsigned int fcrystal);

extern long int scif_enable_osc(scif_osc_t osc, unsigned int startup, bool wait_for_ready);





extern long int scif_start_osc32(const scif_osc32_opt_t *opt, bool wait_for_ready);

#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ bool scif_is_osc32_ready()
{
  return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC32RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC32RDY_OFFSET);
}

#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ void scif_osc32_1kout_ena()
{
  AVR32_SCIF.oscctrl32 |= AVR32_SCIF_EN1K_MASK;
}

#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ void scif_osc32_1kout_dis()
{
  AVR32_SCIF.oscctrl32 &= ~AVR32_SCIF_EN1K_MASK;
}

#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ void scif_osc32_32kout_ena()
{
  AVR32_SCIF.oscctrl32 |= AVR32_SCIF_EN32K_MASK;
}

#if __GNUC__
__attribute__((__always_inline__))
#endif
extern __inline__ void scif_osc32_32kout_dis()
{
  AVR32_SCIF.oscctrl32 &= ~AVR32_SCIF_EN32K_MASK;
}

extern long int scif_stop_osc32();





extern long int scif_dfll0_openloop_start(const scif_dfll_openloop_conf_t *pdfllconfig);

extern long int scif_dfll0_openloop_start_auto(unsigned long TargetFreqkHz);

extern long int scif_dfll0_openloop_updatefreq(const scif_dfll_openloop_conf_t *pdfllconfig);

extern long int scif_dfll0_openloop_updatefreq_auto(unsigned long TargetFreq);

extern long int scif_dfll0_openloop_stop(void);

extern long int scif_dfll0_ssg_gc_enable(void);

extern long int scif_dfll0_ssg_enable(scif_dfll_ssg_conf_t *pssg_conf);

#define scif_dfll0_closedloop_mainref_gc_enable(conf) scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_REF, conf)

extern long int scif_dfll0_closedloop_start(const scif_dfll_closedloop_conf_t *pdfllconfig);

extern long int scif_dfll0_closedloop_configure_and_start( scif_dfll_clkref_t dfll_main_ref_gc,
                                                    unsigned long long target_freq_hz,
                                                    bool enable_ssg);

#define scif_dfll0_closedloop_dither_gc_enable()  scif_dfll0_ssg_gc_enable()












extern void scif_start_rc120M(void);

extern void scif_stop_rc120M(void);





extern void scif_start_rc32k(void);

extern void scif_stop_rc32k(void);





extern long int scif_start_gclk(unsigned int gclk, const scif_gclk_opt_t *opt);

extern long int scif_stop_gclk(unsigned int gclk);

extern long int scif_gc_setup(unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor);

extern long int scif_gc_enable(unsigned int gclk);










long int scif_pclksr_statushigh_wait(unsigned long statusMask);


#ifdef __cplusplus
}
#endif

#endif  // _SCIF_UC3L_H_

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