power_clocks_lib.h File Reference

High-level library abstracting features such as oscillators/pll/dfll configuration, clock configuration, System-sensible parameters configuration, buses clocks configuration, sleep mode, reset. More...

#include <avr32/io.h>
#include "compiler.h"
#include "pm.h"

Go to the source code of this file.

Defines
#define	pcl_disable_module(module) pm_disable_module(&AVR32_PM, module)
	Disable the clock of a module.
#define	pcl_enable_module(module) pm_enable_module(&AVR32_PM, module)
	Enable the clock of a module.
#define	pcl_freq_param_t pm_freq_param_t
	Input and output parameters to configure clocks with pcl_configure_clocks().
#define	PCL_NOT_SUPPORTED (-10000)
	Define "not supported" for the lib.
Enumerations
enum	pcl_dfll_t { PCL_DFLL0 = 0, PCL_DFLL1 = 1 }
	The different DFLLs. More...
enum	pcl_mainclk_t { PCL_MC_RCSYS, PCL_MC_OSC0, PCL_MC_OSC1, PCL_MC_OSC0_PLL0, PCL_MC_OSC1_PLL0, PCL_MC_OSC0_PLL1, PCL_MC_OSC1_PLL1, PCL_MC_DFLL0, PCL_MC_DFLL1, PCL_MC_RC120M, PCL_MC_RC8M, PCL_MC_CRIPOSC }
	Possible Main Clock Sources. More...
enum	pcl_osc_t { PCL_OSC0 = 0, PCL_OSC1 = 1 }
	The different oscillators. More...
Functions
long int	pcl_configure_clocks (pcl_freq_param_t *param)
	Automatically configure the CPU, PBA, PBB, and HSB clocks.
long int	pcl_configure_clocks_dfll0 (pcl_freq_param_t *param)
	Automatically configure the CPU, PBA, PBB, and HSB clocks using the DFLL0 as main source clock.
long int	pcl_configure_clocks_osc0 (pcl_freq_param_t *param)
	Automatically configure the CPU, PBA, PBB, and HSB clocks using the OSC0 osc as main source clock.
long int	pcl_configure_clocks_rc120m (pcl_freq_param_t *param)
	Automatically configure the CPU, PBA, PBB, and HSB clocks using the RC120M osc as main source clock.
long int	pcl_configure_clocks_rcsys (pcl_freq_param_t *param)
	Automatically configure the CPU, PBA, PBB, and HSB clocks using the RCSYS osc as main source clock.
long int	pcl_configure_usb_clock (void)
	Configure the USB Clock.
long int	pcl_switch_to_osc (pcl_osc_t osc, unsigned int fcrystal, unsigned int startup)
	Switch the main clock source to Osc0 configured in crystal mode.

Detailed Description

High-level library abstracting features such as oscillators/pll/dfll configuration, clock configuration, System-sensible parameters configuration, buses clocks configuration, sleep mode, reset.

Compiler: IAR EWAVR32 and GNU GCC for AVR32
Supported devices: All AVR32 devices.
AppNote:

Author:: Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file power_clocks_lib.h.

Define Documentation

#define pcl_disable_module ( module ) pm_disable_module(&AVR32_PM, module)

Disable the clock of a module.

Parameters:

module

The module to shut down (use one of the defines in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks" or look in the module section).

Returns:: Status.

Return values:

	0	Success.
	<0	An error occured.

Definition at line 330 of file power_clocks_lib.h.

#define pcl_enable_module ( module ) pm_enable_module(&AVR32_PM, module)

Enable the clock of a module.

Parameters:

module

The module to clock (use one of the defines in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks" or look in the module section).

Returns:: Status.

Return values:

	0	Success.
	<0	An error occured.

Definition at line 311 of file power_clocks_lib.h.

#define pcl_freq_param_t pm_freq_param_t

Input and output parameters to configure clocks with pcl_configure_clocks().

Definition at line 113 of file power_clocks_lib.h.

#define PCL_NOT_SUPPORTED (-10000)

Define "not supported" for the lib.

Definition at line 145 of file power_clocks_lib.h.

Referenced by pcl_configure_usb_clock(), and pcl_switch_to_osc().

Enumeration Type Documentation

enum pcl_dfll_t

The different DFLLs.

Enumerator:

PCL_DFLL0
PCL_DFLL1

Definition at line 86 of file power_clocks_lib.h.

00087 {
00088   PCL_DFLL0  = 0,
00089   PCL_DFLL1  = 1
00090 } pcl_dfll_t;

enum pcl_mainclk_t

Possible Main Clock Sources.

Enumerator:

PCL_MC_RCSYS
PCL_MC_OSC0
PCL_MC_OSC1
PCL_MC_OSC0_PLL0
PCL_MC_OSC1_PLL0
PCL_MC_OSC0_PLL1
PCL_MC_OSC1_PLL1
PCL_MC_DFLL0
PCL_MC_DFLL1
PCL_MC_RC120M
PCL_MC_RC8M
PCL_MC_CRIPOSC

Definition at line 93 of file power_clocks_lib.h.

00094 {
00095   PCL_MC_RCSYS,      // Default main clock source, supported by all (aka Slow Clock)
00096   PCL_MC_OSC0,       // Supported by all
00097   PCL_MC_OSC1,       // Supported by UC3C only
00098   PCL_MC_OSC0_PLL0,  // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC0 as reference)
00099   PCL_MC_OSC1_PLL0,  // Supported by UC3A, UC3B, UC3A3, UC3C (the main clock source is PLL0 with OSC1 as reference)
00100   PCL_MC_OSC0_PLL1,  // Supported by UC3C  (the main clock source is PLL1 with OSC0 as reference)
00101   PCL_MC_OSC1_PLL1,  // Supported by UC3C  (the main clock source is PLL1 with OSC1 as reference)
00102   PCL_MC_DFLL0,      // Supported by UC3L
00103   PCL_MC_DFLL1,      // Not supported yet
00104   PCL_MC_RC120M,     // Supported by UC3L, UC3C
00105   PCL_MC_RC8M,       // Supported by UC3C
00106   PCL_MC_CRIPOSC     // Supported by UC3C
00107 } pcl_mainclk_t;

enum pcl_osc_t

The different oscillators.

Enumerator:

PCL_OSC0
PCL_OSC1

Definition at line 79 of file power_clocks_lib.h.

00080 {
00081   PCL_OSC0  = 0,
00082   PCL_OSC1  = 1
00083 } pcl_osc_t;

Function Documentation

long int pcl_configure_clocks ( pcl_freq_param_t * param )

Automatically configure the CPU, PBA, PBB, and HSB clocks.

This function needs some parameters stored in a pcl_freq_param_t structure:

main_clk_src is the id of the main clock source to use,
cpu_f and pba_f and pbb_f are the wanted frequencies,
osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0),
osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP).
dfll_f is the target DFLL frequency to set-up if main_clk_src is the dfll.

The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.

Note:: : since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks() and modify it to use preprocessor computation from pre-defined target frequencies.

Parameters:

param

pointer on the configuration structure.

Return values:

	0	Success.
	<0	The configuration cannot be performed.

Definition at line 58 of file power_clocks_lib.c.

References FAIL, FALSE, flashc_set_wait_state(), PASS, pcl_configure_clocks_uc3l(), PM_CLK_DOMAIN_0, PM_CLK_DOMAIN_1, PM_CLK_DOMAIN_2, PM_CLK_DOMAIN_3, PM_CLK_SRC_OSC0, pm_configure_clocks(), PM_MAX_MUL, pm_set_clk_domain_div(), pm_set_mclk_source(), scif_configure_osc_crystalmode(), scif_enable_osc(), SCIF_OSC0, and TRUE.

00060 00061 00062 00063 00064 00065 00066 00067 00068 00069 00070 00071 00072 00073 00074 00075 00076 00077 00078 00079 00080 00081 00082 00083 00084 00085 00086 00087 00088 00089 00090 00091 00092 00093 00094 00095 00096 00097 00098 00099 00100 00101 00102 00103         { 00104 00105 00106 00107         } 00108 00109         { 00110 00111         } 00112 00113 00114 00115 00116         { 00117 00118 00119         } 00120 00121 00122 00123 00124 00125 00126 00127 00128 00129 00130         { 00131 00132 00133         } 00134 00135 00136 00137 00138 00139 00140         { 00141 00142 00143 00144 00145         } 00146 00147 00148         { 00149 00150 00151         } 00152 00153 00154 00155 00156 00157 00158 00159 00160 00161 00162 00163 00164 00165 00166 00167 00168 00169 00170 00171 00172 00173 00174 00175 00176 00177 00178 00179 00180 00181         { 00182 00183 00184 00185 00186         } 00187 00188 00189 00190 00191 00192 00193         { 00194 00195 00196         } 00197 00198 00199 00200 00201         { 00202 00203 00204         } 00205 00206 00207 00208 00209         { 00210 00211 00212 00213         } 00214 00215         { 00216 00217 00218         } 00219 00220 00221         { 00222 00223 00224 00225 00226 00227 00228 00229 00230 00231         { 00232 00233 00234 00235 00236 00237 00238 00239 00240 00241 00242 00243 00244 00245 00246 00247 00248 00249

class="fragment">00059 { #ifndef AVR32_PM_VERSION_RESETVALUE // Implementation for UC3A, UC3A3, UC3B parts. return(pm_configure_clocks(param)); #else #ifdef AVR32_PM_410_H_INCLUDED #define PM_MAX_MUL ((1 << AVR32_SCIF_PLLMUL_SIZE) - 1) #define AVR32_PM_PBA_MAX_FREQ 66000000 #define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ 240000000 #define AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ 33000000 #define AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ 66000000 #define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ 160000000 // Implementation for UC3C parts. // Supported frequencies: // Fosc0 mul div PLL div2_en cpu_f pba_f Comment // 12 15 1 192 1 12 12 // 12 9 3 40 1 20 20 PLL out of spec // 12 15 1 192 1 24 12 // 12 9 1 120 1 30 15 // 12 9 3 40 0 40 20 PLL out of spec // 12 15 1 192 1 48 12 // 12 15 1 192 1 48 24 // 12 8 1 108 1 54 27 // 12 9 1 120 1 60 15 // 12 9 1 120 1 60 30 // 12 10 1 132 1 66 16.5 // unsigned long in_cpu_f = param->cpu_f; unsigned long in_osc0_f = param->osc0_f; unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0; unsigned long pll_freq, rest; Bool b_div2_pba, b_div2_cpu; // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency. scif_configure_osc_crystalmode(SCIF_OSC0, in_osc0_f); // Enable the OSC0 scif_enable_osc(SCIF_OSC0, param->osc0_startup, true); // Set the main clock source as being OSC0. pm_set_mclk_source(PM_CLK_SRC_OSC0); // Start with CPU freq config if (in_cpu_f == in_osc0_f) param->cpu_f = in_osc0_f; param->pba_f = in_osc0_f; return PASS; else if (in_cpu_f < in_osc0_f) // TBD rest = in_cpu_f % in_osc0_f; for (div = 1; div < 32; div++) if ((div * rest) % in_osc0_f == 0) break; if (div == 32) return FAIL; mul = (in_cpu_f * div) / in_osc0_f; if (mul > PM_MAX_MUL) return FAIL; // export 2power from PLL div to div2_cpu while (!(div % 2)) div /= 2; div2_cpu++; // Here we know the mul and div parameter of the PLL config. // . Check out if the PLL has a valid in_cpu_f. // . Try to have for the PLL frequency (VCO output) the highest possible value // to reduce jitter. while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ) if (2 * mul > PM_MAX_MUL) break; mul *= 2; div2_cpu++; if (div2_cpu != 0) div2_cpu--; div2_en = 1; pll_freq = in_osc0_f * mul / (div * (1 << div2_en)); // Update real CPU Frequency param->cpu_f = pll_freq / (1 << div2_cpu); mul--; scif_pll_opt_t opt; opt.osc = SCIF_OSC0, // Sel Osc0 or Osc1 opt.lockcount = 16, // lockcount in main clock for the PLL wait lock opt.div = div, // DIV=1 in the formula opt.mul = mul, // MUL=7 in the formula opt.pll_div2 = div2_en, // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value) opt.pll_wbwdisable = 0, //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode. opt.pll_freq = (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0, // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz. scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock /* Enable PLL0 */ scif_pll_enable(SCIF_PLL0); /* Wait for PLL0 locked */ scif_wait_for_pll_locked(SCIF_PLL0) ; rest = pll_freq; while (rest > AVR32_PM_PBA_MAX_FREQ || rest != param->pba_f) div2_pba++; rest = pll_freq / (1 << div2_pba); if (rest < param->pba_f) break; // Update real PBA Frequency param->pba_f = pll_freq / (1 << div2_pba); if (div2_cpu) b_div2_cpu = TRUE; div2_cpu--; else b_div2_cpu = FALSE; if (div2_pba) b_div2_pba = TRUE; div2_pba--; else b_div2_pba = FALSE; if (b_div2_cpu == TRUE ) pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) div2_cpu); // CPU pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) div2_cpu); // HSB pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) div2_cpu); // PBB if (b_div2_pba == TRUE ) pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) div2_pba); // PBA pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) div2_pba); // PBC if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ) flashc_set_wait_state(1); #if (defined AVR32_FLASHC_300_H_INCLUDED) if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ) flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1); else flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1); #endif } else flashc_set_wait_state(0); #if (defined AVR32_FLASHC_300_H_INCLUDED) if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ) flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1); else flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1); #endif } // Set the main clock source as being PLL0. pm_set_mclk_source(PM_CLK_SRC_PLL0); return PASS; #else return(pcl_configure_clocks_uc3l(param)); #endif #endif }

long int pcl_configure_clocks_dfll0 ( pcl_freq_param_t * param )

Automatically configure the CPU, PBA, PBB, and HSB clocks using the DFLL0 as main source clock.

This function needs some parameters stored in a pcl_freq_param_t structure:

cpu_f and pba_f and pbb_f are the wanted frequencies,
dfll_f is the target DFLL frequency to set-up

Note:: : when the DFLL0 is to be used as main source clock for the synchronous clocks, the target frequency of the DFLL should be chosen to be as high as possible within the specification range (for stability reasons); the target cpu and pbx frequencies will then be reached by appropriate division ratio.

Supported main clock sources: PCL_MC_DFLL0

Supported synchronous clocks frequencies: (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example) 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.

Note:: : by default, this implementation doesn't perform thorough checks on the input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.; : since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_dfll0() and modify it to use preprocessor computation from pre-defined target frequencies.

Parameters:

param

pointer on the configuration structure.

Return values:

	0	Success.
	<0	The configuration cannot be performed.

Definition at line 353 of file power_clocks_lib.c.

References pcl_configure_synchronous_clocks(), PM_CLK_SRC_DFLL0, scif_dfll0_closedloop_configure_and_start(), SCIF_DFLL_CLKREF_GC_SRC_115KHZ, SCIF_DFLL_MAXFREQ_HZ, SCIF_DFLL_MINFREQ_HZ, and TRUE.

Referenced by pcl_configure_clocks_uc3l().

00354 {
00355   // Supported main clock sources: PCL_MC_DFLL
00356 
00357   // Supported synchronous clocks frequencies if DFLL is the main clock source:
00358   // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)
00359   // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.
00360 
00361   // NOTE: by default, this implementation doesn't perform thorough checks on the
00362   // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
00363 
00364   unsigned long               main_clock_freq;
00365 
00366 
00367 #ifdef AVR32SFW_INPUT_CHECK
00368   // Verify that fCPU >= fPBx
00369   if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
00370     return(-1);
00371 #endif
00372 
00373   main_clock_freq = param->dfll_f;
00374 #ifdef AVR32SFW_INPUT_CHECK
00375   // Verify that the target DFLL output frequency is in the correct range.
00376   if((main_clock_freq > SCIF_DFLL_MAXFREQ_HZ) || (main_clock_freq < SCIF_DFLL_MINFREQ_HZ))
00377     return(-1);
00378   // Verify that the target frequencies are reachable.
00379   if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
00380     || (param->pbb_f > main_clock_freq))
00381     return(-1);
00382 #endif
00383   // Implementation note: this implementation configures the DFLL in closed-loop
00384   // mode (because it gives the best accuracy) which enables the generic clock CLK_DFLLIF_REF
00385   // as a reference (RCSYS being used as the generic clock source, undivided).
00386   scif_dfll0_closedloop_configure_and_start(SCIF_DFLL_CLKREF_GC_SRC_115KHZ, main_clock_freq, TRUE);
00387 
00388   return(pcl_configure_synchronous_clocks(PM_CLK_SRC_DFLL0, main_clock_freq, param));
00389 }

long int pcl_configure_clocks_osc0 ( pcl_freq_param_t * param )

Automatically configure the CPU, PBA, PBB, and HSB clocks using the OSC0 osc as main source clock.

This function needs some parameters stored in a pcl_freq_param_t structure:

cpu_f and pba_f and pbb_f are the wanted frequencies,
osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0),
osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP).

Supported main clock sources: PCL_MC_OSC0

Supported synchronous clocks frequencies: (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example) 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.

Note:: : by default, this implementation doesn't perform thorough checks on the input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.; : since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_osc0() and modify it to use preprocessor computation from pre-defined target frequencies.

Parameters:

param

pointer on the configuration structure.

Return values:

	0	Success.
	<0	The configuration cannot be performed.

Definition at line 317 of file power_clocks_lib.c.

References pcl_configure_synchronous_clocks(), PM_CLK_SRC_OSC0, scif_configure_osc_crystalmode(), scif_enable_osc(), and SCIF_OSC0.

Referenced by pcl_configure_clocks_uc3l().

00318 {
00319   // Supported main clock sources: PCL_MC_OSC0
00320 
00321   // Supported synchronous clocks frequencies if OSC0 is the main clock source:
00322   // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)
00323   // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.
00324 
00325   // NOTE: by default, this implementation doesn't perform thorough checks on the
00326   // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
00327 
00328   unsigned long               main_clock_freq;
00329 
00330 
00331 #ifdef AVR32SFW_INPUT_CHECK
00332   // Verify that fCPU >= fPBx
00333   if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
00334     return(-1);
00335 #endif
00336 
00337   main_clock_freq = param->osc0_f;
00338 #ifdef AVR32SFW_INPUT_CHECK
00339   // Verify that the target frequencies are reachable.
00340   if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
00341     || (param->pbb_f > main_clock_freq))
00342     return(-1);
00343 #endif
00344   // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
00345   scif_configure_osc_crystalmode(SCIF_OSC0, main_clock_freq);
00346   // Enable the OSC0
00347   scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
00348 
00349   return(pcl_configure_synchronous_clocks(PM_CLK_SRC_OSC0, main_clock_freq, param));
00350 }

long int pcl_configure_clocks_rc120m ( pcl_freq_param_t * param )

Automatically configure the CPU, PBA, PBB, and HSB clocks using the RC120M osc as main source clock.

This function needs some parameters stored in a pcl_freq_param_t structure:

cpu_f and pba_f and pbb_f are the wanted frequencies

Supported main clock sources: PCL_MC_RC120M

Supported synchronous clocks frequencies: 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.

Note:: : by default, this implementation doesn't perform thorough checks on the input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.; : since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_rc120m() and modify it to use preprocessor computation from pre-defined target frequencies.

Parameters:

param

pointer on the configuration structure.

Return values:

	0	Success.
	<0	The configuration cannot be performed.

Definition at line 287 of file power_clocks_lib.c.

References pcl_configure_synchronous_clocks(), PM_CLK_SRC_RC120M, SCIF_RC120M_FREQ_HZ, and scif_start_rc120M().

Referenced by pcl_configure_clocks_uc3l().

00288 {
00289   // Supported main clock sources: PCL_MC_RC120M
00290 
00291   // Supported synchronous clocks frequencies if RC120M is the main clock source:
00292   // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.
00293 
00294   // NOTE: by default, this implementation doesn't perform thorough checks on the
00295   // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
00296 
00297 #ifdef AVR32SFW_INPUT_CHECK
00298   // Verify that fCPU >= fPBx
00299   if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
00300     return(-1);
00301 #endif
00302 
00303 #ifdef AVR32SFW_INPUT_CHECK
00304   // Verify that the target frequencies are reachable.
00305   if((param->cpu_f > SCIF_RC120M_FREQ_HZ) || (param->pba_f > SCIF_RC120M_FREQ_HZ)
00306     || (param->pbb_f > SCIF_RC120M_FREQ_HZ))
00307     return(-1);
00308 #endif
00309 
00310   // Start the 120MHz internal RCosc (RC120M) clock
00311   scif_start_rc120M();
00312 
00313   return(pcl_configure_synchronous_clocks(PM_CLK_SRC_RC120M, SCIF_RC120M_FREQ_HZ, param));
00314 }

long int pcl_configure_clocks_rcsys ( pcl_freq_param_t * param )

Automatically configure the CPU, PBA, PBB, and HSB clocks using the RCSYS osc as main source clock.

This function needs some parameters stored in a pcl_freq_param_t structure:

cpu_f and pba_f and pbb_f are the wanted frequencies

Supported main clock sources: PCL_MC_RCSYS

Supported synchronous clocks frequencies: 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.

Note:: : by default, this implementation doesn't perform thorough checks on the input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.; : since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_rcsys() and modify it to use preprocessor computation from pre-defined target frequencies.

Parameters:

param

pointer on the configuration structure.

Return values:

	0	Success.
	<0	The configuration cannot be performed.

Definition at line 260 of file power_clocks_lib.c.

References pcl_configure_synchronous_clocks(), PM_CLK_SRC_SLOW, and SCIF_SLOWCLOCK_FREQ_HZ.

Referenced by pcl_configure_clocks_uc3l().

00261 {
00262   // Supported main clock sources: PCL_MC_RCSYS
00263 
00264   // Supported synchronous clocks frequencies if RCSYS is the main clock source:
00265   // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.
00266 
00267   // NOTE: by default, this implementation doesn't perform thorough checks on the
00268   // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
00269 
00270 #ifdef AVR32SFW_INPUT_CHECK
00271   // Verify that fCPU >= fPBx
00272   if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
00273     return(-1);
00274 #endif
00275 
00276 #ifdef AVR32SFW_INPUT_CHECK
00277     // Verify that the target frequencies are reachable.
00278     if((param->cpu_f > SCIF_SLOWCLOCK_FREQ_HZ) || (param->pba_f > SCIF_SLOWCLOCK_FREQ_HZ)
00279       || (param->pbb_f > SCIF_SLOWCLOCK_FREQ_HZ))
00280       return(-1);
00281 #endif
00282 
00283   return(pcl_configure_synchronous_clocks(PM_CLK_SRC_SLOW, SCIF_SLOWCLOCK_FREQ_HZ, param));
00284 }

long int pcl_configure_usb_clock ( void )

Configure the USB Clock.

Parameters:

none

Returns:: Status.

Return values:

	0	Success.
	<0	An error occured.

Definition at line 501 of file power_clocks_lib.c.

References PASS, PCL_NOT_SUPPORTED, pm_configure_usb_clock(), scif_gc_enable(), scif_gc_setup(), and SCIF_OSC0.

00502 {
00503 #ifndef AVR32_PM_VERSION_RESETVALUE
00504 // Implementation for UC3A, UC3A3, UC3B parts.
00505   pm_configure_usb_clock();
00506 #else
00507   #ifdef AVR32_PM_410_H_INCLUDED
00508     const scif_pll_opt_t opt = {
00509               .osc = SCIF_OSC0,     // Sel Osc0 or Osc1
00510               .lockcount = 16,      // lockcount in main clock for the PLL wait lock
00511               .div = 1,             // DIV=1 in the formula
00512               .mul = 5,             // MUL=7 in the formula
00513               .pll_div2 = 1,        // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
00514               .pll_wbwdisable = 0,  //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
00515               .pll_freq = 1,        // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
00516     };
00517   
00518     /* Setup PLL1 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 16Mhzx6 = 96MHz output */
00519     scif_pll_setup(SCIF_PLL1, opt); // lockcount in main clock for the PLL wait lock
00520   
00521     /* Enable PLL1 */
00522     scif_pll_enable(SCIF_PLL1);
00523   
00524     /* Wait for PLL1 locked */
00525     scif_wait_for_pll_locked(SCIF_PLL1) ;
00526       
00527   // Implementation for UC3C parts.
00528     // Setup the generic clock for USB
00529     scif_gc_setup(AVR32_SCIF_GCLK_USB, 
00530                   SCIF_GCCTRL_PLL1, 
00531                   AVR32_SCIF_GC_NO_DIV_CLOCK, 
00532                   0);  
00533     // Now enable the generic clock
00534     scif_gc_enable(AVR32_SCIF_GCLK_USB);
00535   #else
00536       return PCL_NOT_SUPPORTED;
00537   #endif      
00538 #endif
00539   return PASS;      
00540 }

long int pcl_switch_to_osc	(	pcl_osc_t	osc,
		unsigned int	fcrystal,
		unsigned int	startup
	)

Switch the main clock source to Osc0 configured in crystal mode.

Parameters:

	osc	The oscillator to enable and switch to.
	fcrystal	Oscillator external crystal frequency (Hz)
	startup	Oscillator startup time.

Returns:: Status.

Return values:

	0	Success.
	<0	An error occured.

Definition at line 462 of file power_clocks_lib.c.

References flashcdw_set_flash_waitstate_and_readmode(), PASS, PCL_NOT_SUPPORTED, PCL_OSC0, PM_CLK_SRC_OSC0, pm_set_mclk_source(), pm_switch_to_osc0(), scif_configure_osc_crystalmode(), scif_enable_osc(), and SCIF_OSC0.

00463 {
00464 #ifndef AVR32_PM_VERSION_RESETVALUE
00465 // Implementation for UC3A, UC3A3, UC3B parts.
00466   if(PCL_OSC0 == osc)
00467   {
00468     // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency,
00469     // enable the OSC0, set the main clock source as being OSC0.
00470     pm_switch_to_osc0(&AVR32_PM, fcrystal, startup);
00471   }
00472   else
00473   {
00474     return PCL_NOT_SUPPORTED;
00475   }
00476 #else
00477 // Implementation for UC3C, UC3L parts.
00478   #if AVR32_PM_VERSION_RESETVALUE < 0x400
00479     return PCL_NOT_SUPPORTED;
00480   #else
00481   if(PCL_OSC0 == osc)
00482   {
00483     // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
00484     scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal);
00485     // Enable the OSC0
00486     scif_enable_osc(SCIF_OSC0, startup, true);
00487     // Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
00488     flashcdw_set_flash_waitstate_and_readmode(fcrystal);
00489     // Set the main clock source as being OSC0.
00490     pm_set_mclk_source(PM_CLK_SRC_OSC0);
00491   }
00492   else
00493   {
00494     return PCL_NOT_SUPPORTED;
00495   }
00496   #endif
00497 #endif
00498   return PASS;
00499 }

power_clocks_lib.h File Reference

Defines

Enumerations

Functions

Detailed Description

Define Documentation

Enumeration Type Documentation

Function Documentation