power_clocks_lib.c File Reference

High-level library abstracting features such as oscillators/pll/dfll configuration, clock configuration, System-sensible parameters configuration, buses clocks configuration, sleep mode, reset. More...

#include "power_clocks_lib.h"

Go to the source code of this file.

Functions
long int	pcl_configure_clocks (pcl_freq_param_t *param)
	Automatically configure the CPU, PBA, PBB, and HSB clocks.
long int	pcl_configure_clocks_dfll0 (pcl_freq_param_t *param)
	Automatically configure the CPU, PBA, PBB, and HSB clocks using the DFLL0 as main source clock.
long int	pcl_configure_clocks_osc0 (pcl_freq_param_t *param)
	Automatically configure the CPU, PBA, PBB, and HSB clocks using the OSC0 osc as main source clock.
long int	pcl_configure_clocks_rc120m (pcl_freq_param_t *param)
	Automatically configure the CPU, PBA, PBB, and HSB clocks using the RC120M osc as main source clock.
long int	pcl_configure_clocks_rcsys (pcl_freq_param_t *param)
	Automatically configure the CPU, PBA, PBB, and HSB clocks using the RCSYS osc as main source clock.
static long int	pcl_configure_clocks_uc3l (pcl_freq_param_t *param)
	Device-specific data.
static long int	pcl_configure_synchronous_clocks (pm_clk_src_t main_clk_src, unsigned long main_clock_freq_hz, pcl_freq_param_t *param)
	Device-specific implementation.
long int	pcl_configure_usb_clock (void)
	Configure the USB Clock.
long int	pcl_switch_to_osc (pcl_osc_t osc, unsigned int fcrystal, unsigned int startup)
	Switch the main clock source to Osc0 configured in crystal mode.

---

Detailed Description

High-level library abstracting features such as oscillators/pll/dfll configuration, clock configuration, System-sensible parameters configuration, buses clocks configuration, sleep mode, reset.

• Compiler: IAR EWAVR32 and GNU GCC for AVR32
• Supported devices: All AVR32 devices.
• AppNote:

Author:

Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file power_clocks_lib.c.

---

Function Documentation

long int pcl_configure_clocks

(

pcl_freq_param_t *

param

)

Automatically configure the CPU, PBA, PBB, and HSB clocks.

This function needs some parameters stored in a pcl_freq_param_t structure:

• main_clk_src is the id of the main clock source to use,
• cpu_f and pba_f and pbb_f are the wanted frequencies,
• osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0),
• osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP).
• dfll_f is the target DFLL frequency to set-up if main_clk_src is the dfll.

The CPU, HSB and PBA frequencies programmed after configuration are stored back into cpu_f and pba_f.

Note:

: since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks() and modify it to use preprocessor computation from pre-defined target frequencies.

Parameters:

param

pointer on the configuration structure.

Return values:

	0	Success.
	<0	The configuration cannot be performed.

Definition at line 58 of file power_clocks_lib.c.

References FAIL, FALSE, flashc_set_wait_state(), PASS, pcl_configure_clocks_uc3l(), PM_CLK_DOMAIN_0, PM_CLK_DOMAIN_1, PM_CLK_DOMAIN_2, PM_CLK_DOMAIN_3, PM_CLK_SRC_OSC0, pm_configure_clocks(), PM_MAX_MUL, pm_set_clk_domain_div(), pm_set_mclk_source(), scif_configure_osc_crystalmode(), scif_enable_osc(), SCIF_OSC0, and TRUE.

{
#ifndef AVR32_PM_VERSION_RESETVALUE
// Implementation for UC3A, UC3A3, UC3B parts.
  return(pm_configure_clocks(param));
#else
  #ifdef AVR32_PM_410_H_INCLUDED
  
#define PM_MAX_MUL                         ((1 << AVR32_SCIF_PLLMUL_SIZE) - 1)
#define AVR32_PM_PBA_MAX_FREQ              66000000
#define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ   240000000
#define AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ   33000000
#define AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ   66000000
#define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ   160000000

    // Implementation for  UC3C parts.
        // Supported frequencies:
        // Fosc0 mul div PLL div2_en cpu_f pba_f   Comment
        //  12   15   1  192     1     12    12
        //  12    9   3   40     1     20    20    PLL out of spec
        //  12   15   1  192     1     24    12
        //  12    9   1  120     1     30    15
        //  12    9   3   40     0     40    20    PLL out of spec
        //  12   15   1  192     1     48    12
        //  12   15   1  192     1     48    24
        //  12    8   1  108     1     54    27
        //  12    9   1  120     1     60    15
        //  12    9   1  120     1     60    30
        //  12   10   1  132     1     66    16.5
        //
        unsigned long in_cpu_f  = param->cpu_f;
        unsigned long in_osc0_f = param->osc0_f;
        unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
        unsigned long pll_freq, rest;
        Bool b_div2_pba, b_div2_cpu;
      
        // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
        scif_configure_osc_crystalmode(SCIF_OSC0, in_osc0_f);
        // Enable the OSC0
        scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
        // Set the main clock source as being OSC0.
        pm_set_mclk_source(PM_CLK_SRC_OSC0);
      
        // Start with CPU freq config
        if (in_cpu_f == in_osc0_f)
        {
          param->cpu_f = in_osc0_f;
          param->pba_f = in_osc0_f;
          return PASS;
        }
        else if (in_cpu_f < in_osc0_f)
        {
          // TBD
        }
      
        rest = in_cpu_f % in_osc0_f;
      
        for (div = 1; div < 32; div++)
        {
          if ((div * rest) % in_osc0_f == 0)
            break;
        }
        if (div == 32)
          return FAIL;
      
        mul = (in_cpu_f * div) / in_osc0_f;
      
        if (mul > PM_MAX_MUL)
          return FAIL;
      
        // export 2power from PLL div to div2_cpu
        while (!(div % 2))
        {
          div /= 2;
          div2_cpu++;
        }
      
        // Here we know the mul and div parameter of the PLL config.
        // . Check out if the PLL has a valid in_cpu_f.
        // . Try to have for the PLL frequency (VCO output) the highest possible value
        //   to reduce jitter.
        while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
        {
          if (2 * mul > PM_MAX_MUL)
            break;
          mul *= 2;
          div2_cpu++;
        }
      
        if (div2_cpu != 0)
        {
          div2_cpu--;
          div2_en = 1;
        }
      
        pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
      
        // Update real CPU Frequency
        param->cpu_f = pll_freq / (1 << div2_cpu);
        mul--;
      
        scif_pll_opt_t opt;

        opt.osc = SCIF_OSC0,     // Sel Osc0 or Osc1
        opt.lockcount = 16,      // lockcount in main clock for the PLL wait lock
        opt.div = div,             // DIV=1 in the formula
        opt.mul = mul,             // MUL=7 in the formula
        opt.pll_div2 = div2_en,        // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
        opt.pll_wbwdisable = 0,  //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
        opt.pll_freq = (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0,        // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.

  
        scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock
      
        /* Enable PLL0 */
        scif_pll_enable(SCIF_PLL0);
      
        /* Wait for PLL0 locked */
        scif_wait_for_pll_locked(SCIF_PLL0) ;
    
        rest = pll_freq;
        while (rest > AVR32_PM_PBA_MAX_FREQ ||
               rest != param->pba_f)
        {
          div2_pba++;
          rest = pll_freq / (1 << div2_pba);
          if (rest < param->pba_f)
            break;
        }
      
        // Update real PBA Frequency
        param->pba_f = pll_freq / (1 << div2_pba);
      
      
        if (div2_cpu)
        {
          b_div2_cpu = TRUE;
          div2_cpu--;
        }
        else
          b_div2_cpu = FALSE;
      
        if (div2_pba)
        {
          b_div2_pba = TRUE;
          div2_pba--;
        }
        else
          b_div2_pba = FALSE;
          
        if (b_div2_cpu == TRUE )
        {
          pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) div2_cpu); // CPU
          pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) div2_cpu); // HSB
          pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) div2_cpu); // PBB          
        }
        if (b_div2_pba == TRUE )  
        {
          pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) div2_pba); // PBA
          pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) div2_pba); // PBC
        }
                        
        if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ)
        {
          flashc_set_wait_state(1);
      #if (defined AVR32_FLASHC_300_H_INCLUDED)
          if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ)
            flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
          else
            flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
      #endif
        }
        else
        {
          flashc_set_wait_state(0);
      #if (defined AVR32_FLASHC_300_H_INCLUDED)          
          if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ)
            flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
          else
            flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
      #endif            
        }
      
        // Set the main clock source as being PLL0.
        pm_set_mclk_source(PM_CLK_SRC_PLL0);
      
        return PASS;    
  #else
    return(pcl_configure_clocks_uc3l(param));
  #endif
#endif
}

long int pcl_configure_clocks_dfll0

(

pcl_freq_param_t *

param

)

Automatically configure the CPU, PBA, PBB, and HSB clocks using the DFLL0 as main source clock.

This function needs some parameters stored in a pcl_freq_param_t structure:

• cpu_f and pba_f and pbb_f are the wanted frequencies,
• dfll_f is the target DFLL frequency to set-up

Note:

: when the DFLL0 is to be used as main source clock for the synchronous clocks, the target frequency of the DFLL should be chosen to be as high as possible within the specification range (for stability reasons); the target cpu and pbx frequencies will then be reached by appropriate division ratio.

Supported main clock sources: PCL_MC_DFLL0

Supported synchronous clocks frequencies: (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example) 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.

Note:

: by default, this implementation doesn't perform thorough checks on the input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.

: since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_dfll0() and modify it to use preprocessor computation from pre-defined target frequencies.

Parameters:

param

pointer on the configuration structure.

Return values:

	0	Success.
	<0	The configuration cannot be performed.

Definition at line 353 of file power_clocks_lib.c.

References pcl_configure_synchronous_clocks(), PM_CLK_SRC_DFLL0, scif_dfll0_closedloop_configure_and_start(), SCIF_DFLL_CLKREF_GC_SRC_115KHZ, SCIF_DFLL_MAXFREQ_HZ, SCIF_DFLL_MINFREQ_HZ, and TRUE.

Referenced by pcl_configure_clocks_uc3l().

{
  // Supported main clock sources: PCL_MC_DFLL

  // Supported synchronous clocks frequencies if DFLL is the main clock source:
  // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)
  // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.

  // NOTE: by default, this implementation doesn't perform thorough checks on the
  // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.

  unsigned long               main_clock_freq;


#ifdef AVR32SFW_INPUT_CHECK
  // Verify that fCPU >= fPBx
  if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
    return(-1);
#endif

  main_clock_freq = param->dfll_f;
#ifdef AVR32SFW_INPUT_CHECK
  // Verify that the target DFLL output frequency is in the correct range.
  if((main_clock_freq > SCIF_DFLL_MAXFREQ_HZ) || (main_clock_freq < SCIF_DFLL_MINFREQ_HZ))
    return(-1);
  // Verify that the target frequencies are reachable.
  if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
    || (param->pbb_f > main_clock_freq))
    return(-1);
#endif
  // Implementation note: this implementation configures the DFLL in closed-loop
  // mode (because it gives the best accuracy) which enables the generic clock CLK_DFLLIF_REF
  // as a reference (RCSYS being used as the generic clock source, undivided).
  scif_dfll0_closedloop_configure_and_start(SCIF_DFLL_CLKREF_GC_SRC_115KHZ, main_clock_freq, TRUE);

  return(pcl_configure_synchronous_clocks(PM_CLK_SRC_DFLL0, main_clock_freq, param));
}

long int pcl_configure_clocks_osc0

(

pcl_freq_param_t *

param

)

Automatically configure the CPU, PBA, PBB, and HSB clocks using the OSC0 osc as main source clock.

This function needs some parameters stored in a pcl_freq_param_t structure:

• cpu_f and pba_f and pbb_f are the wanted frequencies,
• osc0_f is the oscillator 0's external crystal (or external clock) on-board frequency (e.g. FOSC0),
• osc0_startup is the oscillator 0's external crystal (or external clock) startup time (e.g. OSC0_STARTUP).

Supported main clock sources: PCL_MC_OSC0

Supported synchronous clocks frequencies: (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example) 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.

Note:

: by default, this implementation doesn't perform thorough checks on the input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.

: since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_osc0() and modify it to use preprocessor computation from pre-defined target frequencies.

Parameters:

param

pointer on the configuration structure.

Return values:

	0	Success.
	<0	The configuration cannot be performed.

Definition at line 317 of file power_clocks_lib.c.

References pcl_configure_synchronous_clocks(), PM_CLK_SRC_OSC0, scif_configure_osc_crystalmode(), scif_enable_osc(), and SCIF_OSC0.

Referenced by pcl_configure_clocks_uc3l().

{
  // Supported main clock sources: PCL_MC_OSC0

  // Supported synchronous clocks frequencies if OSC0 is the main clock source:
  // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)
  // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.

  // NOTE: by default, this implementation doesn't perform thorough checks on the
  // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.

  unsigned long               main_clock_freq;


#ifdef AVR32SFW_INPUT_CHECK
  // Verify that fCPU >= fPBx
  if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
    return(-1);
#endif

  main_clock_freq = param->osc0_f;
#ifdef AVR32SFW_INPUT_CHECK
  // Verify that the target frequencies are reachable.
  if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
    || (param->pbb_f > main_clock_freq))
    return(-1);
#endif
  // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
  scif_configure_osc_crystalmode(SCIF_OSC0, main_clock_freq);
  // Enable the OSC0
  scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);

  return(pcl_configure_synchronous_clocks(PM_CLK_SRC_OSC0, main_clock_freq, param));
}

long int pcl_configure_clocks_rc120m

(

pcl_freq_param_t *

param

)

Automatically configure the CPU, PBA, PBB, and HSB clocks using the RC120M osc as main source clock.

This function needs some parameters stored in a pcl_freq_param_t structure:

• cpu_f and pba_f and pbb_f are the wanted frequencies

Supported main clock sources: PCL_MC_RC120M

Supported synchronous clocks frequencies: 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.

Note:

: by default, this implementation doesn't perform thorough checks on the input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.

: since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_rc120m() and modify it to use preprocessor computation from pre-defined target frequencies.

Parameters:

param

pointer on the configuration structure.

Return values:

	0	Success.
	<0	The configuration cannot be performed.

Definition at line 287 of file power_clocks_lib.c.

References pcl_configure_synchronous_clocks(), PM_CLK_SRC_RC120M, SCIF_RC120M_FREQ_HZ, and scif_start_rc120M().

Referenced by pcl_configure_clocks_uc3l().

{
  // Supported main clock sources: PCL_MC_RC120M

  // Supported synchronous clocks frequencies if RC120M is the main clock source:
  // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.

  // NOTE: by default, this implementation doesn't perform thorough checks on the
  // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.

#ifdef AVR32SFW_INPUT_CHECK
  // Verify that fCPU >= fPBx
  if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
    return(-1);
#endif

#ifdef AVR32SFW_INPUT_CHECK
  // Verify that the target frequencies are reachable.
  if((param->cpu_f > SCIF_RC120M_FREQ_HZ) || (param->pba_f > SCIF_RC120M_FREQ_HZ)
    || (param->pbb_f > SCIF_RC120M_FREQ_HZ))
    return(-1);
#endif

  // Start the 120MHz internal RCosc (RC120M) clock
  scif_start_rc120M();

  return(pcl_configure_synchronous_clocks(PM_CLK_SRC_RC120M, SCIF_RC120M_FREQ_HZ, param));
}

long int pcl_configure_clocks_rcsys

(

pcl_freq_param_t *

param

)

Automatically configure the CPU, PBA, PBB, and HSB clocks using the RCSYS osc as main source clock.

This function needs some parameters stored in a pcl_freq_param_t structure:

• cpu_f and pba_f and pbb_f are the wanted frequencies

Supported main clock sources: PCL_MC_RCSYS

Supported synchronous clocks frequencies: 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.

Note:

: by default, this implementation doesn't perform thorough checks on the input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.

: since it is dynamically computing the appropriate field values of the configuration registers from the parameters structure, this function is not optimal in terms of code size. For a code size optimal solution, it is better to create a new function from pcl_configure_clocks_rcsys() and modify it to use preprocessor computation from pre-defined target frequencies.

Parameters:

param

pointer on the configuration structure.

Return values:

	0	Success.
	<0	The configuration cannot be performed.

Definition at line 260 of file power_clocks_lib.c.

References pcl_configure_synchronous_clocks(), PM_CLK_SRC_SLOW, and SCIF_SLOWCLOCK_FREQ_HZ.

Referenced by pcl_configure_clocks_uc3l().

{
  // Supported main clock sources: PCL_MC_RCSYS

  // Supported synchronous clocks frequencies if RCSYS is the main clock source:
  // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.

  // NOTE: by default, this implementation doesn't perform thorough checks on the
  // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.

#ifdef AVR32SFW_INPUT_CHECK
  // Verify that fCPU >= fPBx
  if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
    return(-1);
#endif

#ifdef AVR32SFW_INPUT_CHECK
    // Verify that the target frequencies are reachable.
    if((param->cpu_f > SCIF_SLOWCLOCK_FREQ_HZ) || (param->pba_f > SCIF_SLOWCLOCK_FREQ_HZ)
      || (param->pbb_f > SCIF_SLOWCLOCK_FREQ_HZ))
      return(-1);
#endif

  return(pcl_configure_synchronous_clocks(PM_CLK_SRC_SLOW, SCIF_SLOWCLOCK_FREQ_HZ, param));
}

static long int pcl_configure_clocks_uc3l

(

pcl_freq_param_t *

param

)

[static]

Device-specific data.

Definition at line 392 of file power_clocks_lib.c.

References pcl_configure_clocks_dfll0(), pcl_configure_clocks_osc0(), pcl_configure_clocks_rc120m(), pcl_configure_clocks_rcsys(), PCL_MC_OSC0, PCL_MC_RC120M, and PCL_MC_RCSYS.

Referenced by pcl_configure_clocks().

{
  // Supported main clock sources: PCL_MC_RCSYS, PCL_MC_OSC0, PCL_MC_DFLL0, PCL_MC_RC120M

  // Supported synchronous clocks frequencies if RCSYS is the main clock source:
  // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.

  // Supported synchronous clocks frequencies if RC120M is the main clock source:
  // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.

  // Supported synchronous clocks frequencies if OSC0 is the main clock source:
  // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)
  // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.

  // Supported synchronous clocks frequencies if DFLL is the main clock source:
  // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)
  // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.

  // NOTE: by default, this implementation doesn't perform thorough checks on the
  // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.

  
#ifdef AVR32SFW_INPUT_CHECK
  // Verify that fCPU >= fPBx
  if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
    return(-1);
#endif
  
  if(PCL_MC_RCSYS == param->main_clk_src)
  {
    return(pcl_configure_clocks_rcsys(param));
  }
  else if(PCL_MC_RC120M == param->main_clk_src)
  {
    return(pcl_configure_clocks_rc120m(param));
  }
  else if(PCL_MC_OSC0 == param->main_clk_src)
  { 
    return(pcl_configure_clocks_osc0(param));
  }
  else // PCL_MC_DFLL0 == param->main_clk_src
  {
    return(pcl_configure_clocks_dfll0(param));
  }
}

static long int pcl_configure_synchronous_clocks	(	pm_clk_src_t	main_clk_src,
		unsigned long	main_clock_freq_hz,
		pcl_freq_param_t *	param
	)			[static]

Device-specific implementation.

Definition at line 439 of file power_clocks_lib.c.

References flashcdw_set_flash_waitstate_and_readmode(), PASS, pm_set_all_cksel(), and pm_set_mclk_source().

Referenced by pcl_configure_clocks_dfll0(), pcl_configure_clocks_osc0(), pcl_configure_clocks_rc120m(), and pcl_configure_clocks_rcsys().

{
  //#
  //# Set the Synchronous clock division ratio for each clock domain
  //#
  pm_set_all_cksel(main_clock_freq_hz, param->cpu_f, param->pba_f, param->pbb_f);

  //#
  //# Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
  //#
  flashcdw_set_flash_waitstate_and_readmode(param->cpu_f);

  //#
  //# Switch the main clock source to the selected clock.
  //#
  pm_set_mclk_source(main_clk_src);

  return PASS;
}

long int pcl_configure_usb_clock

(

void

)

Configure the USB Clock.

Parameters:

none

Returns:

Status.

Return values:

	0	Success.
	<0	An error occured.

Definition at line 501 of file power_clocks_lib.c.

References PASS, PCL_NOT_SUPPORTED, pm_configure_usb_clock(), scif_gc_enable(), scif_gc_setup(), and SCIF_OSC0.

{
#ifndef AVR32_PM_VERSION_RESETVALUE
// Implementation for UC3A, UC3A3, UC3B parts.
  pm_configure_usb_clock();
#else
  #ifdef AVR32_PM_410_H_INCLUDED
    const scif_pll_opt_t opt = {
              .osc = SCIF_OSC0,     // Sel Osc0 or Osc1
              .lockcount = 16,      // lockcount in main clock for the PLL wait lock
              .div = 1,             // DIV=1 in the formula
              .mul = 5,             // MUL=7 in the formula
              .pll_div2 = 1,        // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
              .pll_wbwdisable = 0,  //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
              .pll_freq = 1,        // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
    };
  
    /* Setup PLL1 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 16Mhzx6 = 96MHz output */
    scif_pll_setup(SCIF_PLL1, opt); // lockcount in main clock for the PLL wait lock
  
    /* Enable PLL1 */
    scif_pll_enable(SCIF_PLL1);
  
    /* Wait for PLL1 locked */
    scif_wait_for_pll_locked(SCIF_PLL1) ;
      
  // Implementation for UC3C parts.
    // Setup the generic clock for USB
    scif_gc_setup(AVR32_SCIF_GCLK_USB, 
                  SCIF_GCCTRL_PLL1, 
                  AVR32_SCIF_GC_NO_DIV_CLOCK, 
                  0);  
    // Now enable the generic clock
    scif_gc_enable(AVR32_SCIF_GCLK_USB);
  #else
      return PCL_NOT_SUPPORTED;
  #endif      
#endif
  return PASS;      
}

long int pcl_switch_to_osc	(	pcl_osc_t	osc,
		unsigned int	fcrystal,
		unsigned int	startup
	)

Switch the main clock source to Osc0 configured in crystal mode.

Parameters:

	osc	The oscillator to enable and switch to.
	fcrystal	Oscillator external crystal frequency (Hz)
	startup	Oscillator startup time.

Returns:

Status.

Return values:

	0	Success.
	<0	An error occured.

Definition at line 462 of file power_clocks_lib.c.

References flashcdw_set_flash_waitstate_and_readmode(), PASS, PCL_NOT_SUPPORTED, PCL_OSC0, PM_CLK_SRC_OSC0, pm_set_mclk_source(), pm_switch_to_osc0(), scif_configure_osc_crystalmode(), scif_enable_osc(), and SCIF_OSC0.

{
#ifndef AVR32_PM_VERSION_RESETVALUE
// Implementation for UC3A, UC3A3, UC3B parts.
  if(PCL_OSC0 == osc)
  {
    // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency,
    // enable the OSC0, set the main clock source as being OSC0.
    pm_switch_to_osc0(&AVR32_PM, fcrystal, startup);
  }
  else
  {
    return PCL_NOT_SUPPORTED;
  }
#else
// Implementation for UC3C, UC3L parts.
  #if AVR32_PM_VERSION_RESETVALUE < 0x400
    return PCL_NOT_SUPPORTED;
  #else
  if(PCL_OSC0 == osc)
  {
    // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
    scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal);
    // Enable the OSC0
    scif_enable_osc(SCIF_OSC0, startup, true);
    // Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
    flashcdw_set_flash_waitstate_and_readmode(fcrystal);
    // Set the main clock source as being OSC0.
    pm_set_mclk_source(PM_CLK_SRC_OSC0);
  }
  else
  {
    return PCL_NOT_SUPPORTED;
  }
  #endif
#endif
  return PASS;
}