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# power_clocks_lib.c

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    00001 /*This file has been prepared for Doxygen automatic documentation generation.*/
    00018 /* Copyright (c) 2009 Atmel Corporation. All rights reserved.
    00019  *
    00020  * Redistribution and use in source and binary forms, with or without
    00021  * modification, are permitted provided that the following conditions are met:
    00022  *
    00023  * 1. Redistributions of source code must retain the above copyright notice, this
    00024  * list of conditions and the following disclaimer.
    00025  *
    00026  * 2. Redistributions in binary form must reproduce the above copyright notice,
    00027  * this list of conditions and the following disclaimer in the documentation
    00028  * and/or other materials provided with the distribution.
    00029  *
    00030  * 3. The name of Atmel may not be used to endorse or promote products derived
    00031  * from this software without specific prior written permission.
    00032  *
    00033  * 4. This software may only be redistributed and used in connection with an Atmel
    00034  * AVR product.
    00035  *
    00036  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
    00037  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    00038  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
    00039  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
    00040  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
    00041  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
    00042  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
    00043  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    00044  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
    00045  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
    00046  *
    00047  */
    00048 #include "power_clocks_lib.h"
    00049
    00050
    00052 #if (( defined (__GNUC__) && ( defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__))) \
    00053     ||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__)  )))
    00054 static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param); // FORWARD declaration
    00055 #endif
    00056
    00057
    00058 long int pcl_configure_clocks(pcl_freq_param_t *param)
    00059 {
    00060 #ifndef AVR32_PM_VERSION_RESETVALUE
    00061 // Implementation for UC3A, UC3A3, UC3B parts.
    00062   return(pm_configure_clocks(param));
    00063 #else
    00064   #ifdef AVR32_PM_410_H_INCLUDED
    00065
    00066 #define PM_MAX_MUL                         ((1 << AVR32_SCIF_PLLMUL_SIZE) - 1)
    00067 #define AVR32_PM_PBA_MAX_FREQ              66000000
    00068 #define AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ   240000000
    00069 #define AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ   33000000
    00070 #define AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ   66000000
    00071 #define AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ   160000000
    00072
    00073     // Implementation for  UC3C parts.
    00074         // Supported frequencies:
    00075         // Fosc0 mul div PLL div2_en cpu_f pba_f   Comment
    00076         //  12   15   1  192     1     12    12
    00077         //  12    9   3   40     1     20    20    PLL out of spec
    00078         //  12   15   1  192     1     24    12
    00079         //  12    9   1  120     1     30    15
    00080         //  12    9   3   40     0     40    20    PLL out of spec
    00081         //  12   15   1  192     1     48    12
    00082         //  12   15   1  192     1     48    24
    00083         //  12    8   1  108     1     54    27
    00084         //  12    9   1  120     1     60    15
    00085         //  12    9   1  120     1     60    30
    00086         //  12   10   1  132     1     66    16.5
    00087         //
    00088         unsigned long in_cpu_f  = param->cpu_f;
    00089         unsigned long in_osc0_f = param->osc0_f;
    00090         unsigned long mul, div, div2_en = 0, div2_cpu = 0, div2_pba = 0;
    00091         unsigned long pll_freq, rest;
    00092         Bool b_div2_pba, b_div2_cpu;
    00093
    00094         // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
    00095         scif_configure_osc_crystalmode(SCIF_OSC0, in_osc0_f);
    00096         // Enable the OSC0
    00097         scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
    00098         // Set the main clock source as being OSC0.
    00099         pm_set_mclk_source(PM_CLK_SRC_OSC0);
    00100
    00101         // Start with CPU freq config
    00102         if (in_cpu_f == in_osc0_f)
    00103         {
    00104           param->cpu_f = in_osc0_f;
    00105           param->pba_f = in_osc0_f;
    00106           return PASS;
    00107         }
    00108         else if (in_cpu_f < in_osc0_f)
    00109         {
    00110           // TBD
    00111         }
    00112
    00113         rest = in_cpu_f % in_osc0_f;
    00114
    00115         for (div = 1; div < 32; div++)
    00116         {
    00117           if ((div * rest) % in_osc0_f == 0)
    00118             break;
    00119         }
    00120         if (div == 32)
    00121           return FAIL;
    00122
    00123         mul = (in_cpu_f * div) / in_osc0_f;
    00124
    00125         if (mul > PM_MAX_MUL)
    00126           return FAIL;
    00127
    00128         // export 2power from PLL div to div2_cpu
    00129         while (!(div % 2))
    00130         {
    00131           div /= 2;
    00132           div2_cpu++;
    00133         }
    00134
    00135         // Here we know the mul and div parameter of the PLL config.
    00136         // . Check out if the PLL has a valid in_cpu_f.
    00137         // . Try to have for the PLL frequency (VCO output) the highest possible value
    00138         //   to reduce jitter.
    00139         while (in_osc0_f * 2 * mul / div < AVR32_PM_PLL_VCO_RANGE0_MAX_FREQ)
    00140         {
    00141           if (2 * mul > PM_MAX_MUL)
    00142             break;
    00143           mul *= 2;
    00144           div2_cpu++;
    00145         }
    00146
    00147         if (div2_cpu != 0)
    00148         {
    00149           div2_cpu--;
    00150           div2_en = 1;
    00151         }
    00152
    00153         pll_freq = in_osc0_f * mul / (div * (1 << div2_en));
    00154
    00155         // Update real CPU Frequency
    00156         param->cpu_f = pll_freq / (1 << div2_cpu);
    00157         mul--;
    00158
    00159         scif_pll_opt_t opt;
    00160
    00161         opt.osc = SCIF_OSC0,     // Sel Osc0 or Osc1
    00162         opt.lockcount = 16,      // lockcount in main clock for the PLL wait lock
    00163         opt.div = div,             // DIV=1 in the formula
    00164         opt.mul = mul,             // MUL=7 in the formula
    00165         opt.pll_div2 = div2_en,        // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
    00166         opt.pll_wbwdisable = 0,  //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
    00167         opt.pll_freq = (pll_freq < AVR32_PM_PLL_VCO_RANGE0_MIN_FREQ) ? 1 : 0,        // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
    00168
    00169
    00170         scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock
    00171
    00172         /* Enable PLL0 */
    00173         scif_pll_enable(SCIF_PLL0);
    00174
    00175         /* Wait for PLL0 locked */
    00176         scif_wait_for_pll_locked(SCIF_PLL0) ;
    00177
    00178         rest = pll_freq;
    00179         while (rest > AVR32_PM_PBA_MAX_FREQ ||
    00180                rest != param->pba_f)
    00181         {
    00182           div2_pba++;
    00183           rest = pll_freq / (1 << div2_pba);
    00184           if (rest < param->pba_f)
    00185             break;
    00186         }
    00187
    00188         // Update real PBA Frequency
    00189         param->pba_f = pll_freq / (1 << div2_pba);
    00190
    00191
    00192         if (div2_cpu)
    00193         {
    00194           b_div2_cpu = TRUE;
    00195           div2_cpu--;
    00196         }
    00197         else
    00198           b_div2_cpu = FALSE;
    00199
    00200         if (div2_pba)
    00201         {
    00202           b_div2_pba = TRUE;
    00203           div2_pba--;
    00204         }
    00205         else
    00206           b_div2_pba = FALSE;
    00207
    00208         if (b_div2_cpu == TRUE )
    00209         {
    00210           pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) div2_cpu); // CPU
    00211           pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) div2_cpu); // HSB
    00212           pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) div2_cpu); // PBB
    00213         }
    00214         if (b_div2_pba == TRUE )
    00215         {
    00216           pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) div2_pba); // PBA
    00217           pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) div2_pba); // PBC
    00218         }
    00219
    00220         if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ)
    00221         {
    00222           flashc_set_wait_state(1);
    00223       #if (defined AVR32_FLASHC_300_H_INCLUDED)
    00224           if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_1_MAX_FREQ)
    00225             flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
    00226           else
    00227             flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
    00228       #endif
    00229         }
    00230         else
    00231         {
    00232           flashc_set_wait_state(0);
    00233       #if (defined AVR32_FLASHC_300_H_INCLUDED)
    00234           if (param->cpu_f > AVR32_FLASHC_HSEN_FWS_0_MAX_FREQ)
    00235             flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSEN, -1);
    00236           else
    00237             flashc_issue_command(AVR32_FLASHC_FCMD_CMD_HSDIS, -1);
    00238       #endif
    00239         }
    00240
    00241         // Set the main clock source as being PLL0.
    00242         pm_set_mclk_source(PM_CLK_SRC_PLL0);
    00243
    00244         return PASS;
    00245   #else
    00246     return(pcl_configure_clocks_uc3l(param));
    00247   #endif
    00248 #endif
    00249 }
    00250
    00251
    00253 #if (( defined (__GNUC__) && ( defined (__AVR32_UC3L016__) || defined (__AVR32_UC3L032__) || defined (__AVR32_UC3L064__))) \
    00254     ||(defined (__ICCAVR32__) && (defined (__AT32UC3L016__) || defined (__AT32UC3L032__) || defined (__AT32UC3L064__)  )))
    00255 // FORWARD declaration
    00256 static long int pcl_configure_synchronous_clocks( pm_clk_src_t main_clk_src,
    00257                                                   unsigned long main_clock_freq_hz,
    00258                                                   pcl_freq_param_t *param);
    00259
    00260 long int pcl_configure_clocks_rcsys(pcl_freq_param_t *param)
    00261 {
    00262   // Supported main clock sources: PCL_MC_RCSYS
    00263
    00264   // Supported synchronous clocks frequencies if RCSYS is the main clock source:
    00265   // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.
    00266
    00267   // NOTE: by default, this implementation doesn't perform thorough checks on the
    00268   // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
    00269
    00270 #ifdef AVR32SFW_INPUT_CHECK
    00271   // Verify that fCPU >= fPBx
    00272   if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
    00273     return(-1);
    00274 #endif
    00275
    00276 #ifdef AVR32SFW_INPUT_CHECK
    00277     // Verify that the target frequencies are reachable.
    00278     if((param->cpu_f > SCIF_SLOWCLOCK_FREQ_HZ) || (param->pba_f > SCIF_SLOWCLOCK_FREQ_HZ)
    00279       || (param->pbb_f > SCIF_SLOWCLOCK_FREQ_HZ))
    00280       return(-1);
    00281 #endif
    00282
    00283   return(pcl_configure_synchronous_clocks(PM_CLK_SRC_SLOW, SCIF_SLOWCLOCK_FREQ_HZ, param));
    00284 }
    00285
    00286
    00287 long int pcl_configure_clocks_rc120m(pcl_freq_param_t *param)
    00288 {
    00289   // Supported main clock sources: PCL_MC_RC120M
    00290
    00291   // Supported synchronous clocks frequencies if RC120M is the main clock source:
    00292   // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.
    00293
    00294   // NOTE: by default, this implementation doesn't perform thorough checks on the
    00295   // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
    00296
    00297 #ifdef AVR32SFW_INPUT_CHECK
    00298   // Verify that fCPU >= fPBx
    00299   if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
    00300     return(-1);
    00301 #endif
    00302
    00303 #ifdef AVR32SFW_INPUT_CHECK
    00304   // Verify that the target frequencies are reachable.
    00305   if((param->cpu_f > SCIF_RC120M_FREQ_HZ) || (param->pba_f > SCIF_RC120M_FREQ_HZ)
    00306     || (param->pbb_f > SCIF_RC120M_FREQ_HZ))
    00307     return(-1);
    00308 #endif
    00309
    00310   // Start the 120MHz internal RCosc (RC120M) clock
    00311   scif_start_rc120M();
    00312
    00313   return(pcl_configure_synchronous_clocks(PM_CLK_SRC_RC120M, SCIF_RC120M_FREQ_HZ, param));
    00314 }
    00315
    00316
    00317 long int pcl_configure_clocks_osc0(pcl_freq_param_t *param)
    00318 {
    00319   // Supported main clock sources: PCL_MC_OSC0
    00320
    00321   // Supported synchronous clocks frequencies if OSC0 is the main clock source:
    00322   // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)
    00323   // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.
    00324
    00325   // NOTE: by default, this implementation doesn't perform thorough checks on the
    00326   // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
    00327
    00328   unsigned long               main_clock_freq;
    00329
    00330
    00331 #ifdef AVR32SFW_INPUT_CHECK
    00332   // Verify that fCPU >= fPBx
    00333   if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
    00334     return(-1);
    00335 #endif
    00336
    00337   main_clock_freq = param->osc0_f;
    00338 #ifdef AVR32SFW_INPUT_CHECK
    00339   // Verify that the target frequencies are reachable.
    00340   if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
    00341     || (param->pbb_f > main_clock_freq))
    00342     return(-1);
    00343 #endif
    00344   // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
    00345   scif_configure_osc_crystalmode(SCIF_OSC0, main_clock_freq);
    00346   // Enable the OSC0
    00347   scif_enable_osc(SCIF_OSC0, param->osc0_startup, true);
    00348
    00349   return(pcl_configure_synchronous_clocks(PM_CLK_SRC_OSC0, main_clock_freq, param));
    00350 }
    00351
    00352
    00353 long int pcl_configure_clocks_dfll0(pcl_freq_param_t *param)
    00354 {
    00355   // Supported main clock sources: PCL_MC_DFLL
    00356
    00357   // Supported synchronous clocks frequencies if DFLL is the main clock source:
    00358   // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)
    00359   // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.
    00360
    00361   // NOTE: by default, this implementation doesn't perform thorough checks on the
    00362   // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
    00363
    00364   unsigned long               main_clock_freq;
    00365
    00366
    00367 #ifdef AVR32SFW_INPUT_CHECK
    00368   // Verify that fCPU >= fPBx
    00369   if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
    00370     return(-1);
    00371 #endif
    00372
    00373   main_clock_freq = param->dfll_f;
    00374 #ifdef AVR32SFW_INPUT_CHECK
    00375   // Verify that the target DFLL output frequency is in the correct range.
    00376   if((main_clock_freq > SCIF_DFLL_MAXFREQ_HZ) || (main_clock_freq < SCIF_DFLL_MINFREQ_HZ))
    00377     return(-1);
    00378   // Verify that the target frequencies are reachable.
    00379   if((param->cpu_f > main_clock_freq) || (param->pba_f > main_clock_freq)
    00380     || (param->pbb_f > main_clock_freq))
    00381     return(-1);
    00382 #endif
    00383   // Implementation note: this implementation configures the DFLL in closed-loop
    00384   // mode (because it gives the best accuracy) which enables the generic clock CLK_DFLLIF_REF
    00385   // as a reference (RCSYS being used as the generic clock source, undivided).
    00386   scif_dfll0_closedloop_configure_and_start(SCIF_DFLL_CLKREF_GC_SRC_115KHZ, main_clock_freq, TRUE);
    00387
    00388   return(pcl_configure_synchronous_clocks(PM_CLK_SRC_DFLL0, main_clock_freq, param));
    00389 }
    00390
    00391
    00392 static long int pcl_configure_clocks_uc3l(pcl_freq_param_t *param)
    00393 {
    00394   // Supported main clock sources: PCL_MC_RCSYS, PCL_MC_OSC0, PCL_MC_DFLL0, PCL_MC_RC120M
    00395
    00396   // Supported synchronous clocks frequencies if RCSYS is the main clock source:
    00397   // 115200Hz, 57600Hz, 28800Hz, 14400Hz, 7200Hz, 3600Hz, 1800Hz, 900Hz, 450Hz.
    00398
    00399   // Supported synchronous clocks frequencies if RC120M is the main clock source:
    00400   // 30MHz, 15MHz, 7.5MHz, 3.75MHz, 1.875MHz, 937.5kHz, 468.75kHz.
    00401
    00402   // Supported synchronous clocks frequencies if OSC0 is the main clock source:
    00403   // (these obviously depend on the OSC0 frequency; we'll take 16MHz as an example)
    00404   // 16MHz, 8MHz, 4MHz, 2MHz, 1MHz, 500kHz, 250kHz, 125kHz, 62.5kHz.
    00405
    00406   // Supported synchronous clocks frequencies if DFLL is the main clock source:
    00407   // (these obviously depend on the DFLL target frequency; we'll take 100MHz as an example)
    00408   // 50MHz, 25MHz, 12.5MHz, 6.25MHz, 3.125MHz, 1562.5kHz, 781.25kHz, 390.625kHz.
    00409
    00410   // NOTE: by default, this implementation doesn't perform thorough checks on the
    00411   // input parameters. To enable the checks, define AVR32SFW_INPUT_CHECK.
    00412
    00413
    00414 #ifdef AVR32SFW_INPUT_CHECK
    00415   // Verify that fCPU >= fPBx
    00416   if((param->cpu_f < param->pba_f) || (param->cpu_f < param->pbb_f))
    00417     return(-1);
    00418 #endif
    00419
    00420   if(PCL_MC_RCSYS == param->main_clk_src)
    00421   {
    00422     return(pcl_configure_clocks_rcsys(param));
    00423   }
    00424   else if(PCL_MC_RC120M == param->main_clk_src)
    00425   {
    00426     return(pcl_configure_clocks_rc120m(param));
    00427   }
    00428   else if(PCL_MC_OSC0 == param->main_clk_src)
    00429   {
    00430     return(pcl_configure_clocks_osc0(param));
    00431   }
    00432   else // PCL_MC_DFLL0 == param->main_clk_src
    00433   {
    00434     return(pcl_configure_clocks_dfll0(param));
    00435   }
    00436 }
    00437
    00438
    00439 static long int pcl_configure_synchronous_clocks(pm_clk_src_t main_clk_src, unsigned long main_clock_freq_hz, pcl_freq_param_t *param)
    00440 {
    00441   //#
    00442   //# Set the Synchronous clock division ratio for each clock domain
    00443   //#
    00444   pm_set_all_cksel(main_clock_freq_hz, param->cpu_f, param->pba_f, param->pbb_f);
    00445
    00446   //#
    00447   //# Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
    00448   //#
    00449   flashcdw_set_flash_waitstate_and_readmode(param->cpu_f);
    00450
    00451   //#
    00452   //# Switch the main clock source to the selected clock.
    00453   //#
    00454   pm_set_mclk_source(main_clk_src);
    00455
    00456   return PASS;
    00457 }
    00458
    00459 #endif // UC3L device-specific implementation
    00460
    00461
    00462 long int pcl_switch_to_osc(pcl_osc_t osc, unsigned int fcrystal, unsigned int startup)
    00463 {
    00464 #ifndef AVR32_PM_VERSION_RESETVALUE
    00465 // Implementation for UC3A, UC3A3, UC3B parts.
    00466   if(PCL_OSC0 == osc)
    00467   {
    00468     // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency,
    00469     // enable the OSC0, set the main clock source as being OSC0.
    00470     pm_switch_to_osc0(&AVR32_PM, fcrystal, startup);
    00471   }
    00472   else
    00473   {
    00474     return PCL_NOT_SUPPORTED;
    00475   }
    00476 #else
    00477 // Implementation for UC3C, UC3L parts.
    00478   #if AVR32_PM_VERSION_RESETVALUE < 0x400
    00479     return PCL_NOT_SUPPORTED;
    00480   #else
    00481   if(PCL_OSC0 == osc)
    00482   {
    00483     // Configure OSC0 in crystal mode, external crystal with a fcrystal Hz frequency.
    00484     scif_configure_osc_crystalmode(SCIF_OSC0, fcrystal);
    00485     // Enable the OSC0
    00486     scif_enable_osc(SCIF_OSC0, startup, true);
    00487     // Set the Flash wait state and the speed read mode (depending on the target CPU frequency).
    00488     flashcdw_set_flash_waitstate_and_readmode(fcrystal);
    00489     // Set the main clock source as being OSC0.
    00490     pm_set_mclk_source(PM_CLK_SRC_OSC0);
    00491   }
    00492   else
    00493   {
    00494     return PCL_NOT_SUPPORTED;
    00495   }
    00496   #endif
    00497 #endif
    00498   return PASS;
    00499 }
    00500
    00501 long int pcl_configure_usb_clock(void)
    00502 {
    00503 #ifndef AVR32_PM_VERSION_RESETVALUE
    00504 // Implementation for UC3A, UC3A3, UC3B parts.
    00505   pm_configure_usb_clock();
    00506 #else
    00507   #ifdef AVR32_PM_410_H_INCLUDED
    00508     const scif_pll_opt_t opt = {
    00509               .osc = SCIF_OSC0,     // Sel Osc0 or Osc1
    00510               .lockcount = 16,      // lockcount in main clock for the PLL wait lock
    00511               .div = 1,             // DIV=1 in the formula
    00512               .mul = 5,             // MUL=7 in the formula
    00513               .pll_div2 = 1,        // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
    00514               .pll_wbwdisable = 0,  //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
    00515               .pll_freq = 1,        // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
    00516     };
    00517
    00518     /* Setup PLL1 on Osc0, mul=7 ,no divisor, lockcount=16, ie. 16Mhzx6 = 96MHz output */
    00519     scif_pll_setup(SCIF_PLL1, opt); // lockcount in main clock for the PLL wait lock
    00520
    00521     /* Enable PLL1 */
    00522     scif_pll_enable(SCIF_PLL1);
    00523
    00524     /* Wait for PLL1 locked */
    00525     scif_wait_for_pll_locked(SCIF_PLL1) ;
    00526
    00527   // Implementation for UC3C parts.
    00528     // Setup the generic clock for USB
    00529     scif_gc_setup(AVR32_SCIF_GCLK_USB,
    00530                   SCIF_GCCTRL_PLL1,
    00531                   AVR32_SCIF_GC_NO_DIV_CLOCK,
    00532                   0);
    00533     // Now enable the generic clock
    00534     scif_gc_enable(AVR32_SCIF_GCLK_USB);
    00535   #else
    00536       return PCL_NOT_SUPPORTED;
    00537   #endif
    00538 #endif
    00539   return PASS;
    00540 }