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# pico_power_uc3l064.c

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    00001 /*This file has been prepared for Doxygen automatic documentation generation.*/
    00082 #include "board.h"
    00083 #include "gpio.h"
    00084 #include "scif_uc3l.h"
    00085 #include "power_clocks_lib.h"
    00086
    00089
    00090
    00092 #define   EXAMPLE_FDFLL_KHZ     50000
    00093 #define   EXAMPLE_FDFLL_HZ      50000000
    00094
    00095  volatile int i;
    00096  volatile avr32_scif_t * SCIF = &AVR32_SCIF;
    00097  volatile avr32_ast_t * AST = &AVR32_AST;
    00098  U8 *avr32_sram=AVR32_SRAM;
    00099
    00100 // Before entering a sleep mode, set R2 to 0x10000000 to avoid extra 40ua (related to scan issue on UC3L revB).
    00101 #define PM_SLEEP(sleep_mode)  {__asm__ __volatile__ (\
    00102         "MOV    R2, 0\n\t"\
    00103         "SBR    R2, 28\n\t"\
    00104         "sleep "STRINGZ(sleep_mode));}
    00105
    00106 // Extra hw setup for UC3L revB: PA21 and PB10 grounded and removed LED0 & LED1.
    00107 // PA11 grounded.
    00108
    00109
    00111
    00115 static void local_start_dfll_clock(void)
    00116 {
    00117   scif_dfll_closedloop_conf_t DfllConfig;
    00118   scif_gclk_opt_t             GcConf;
    00119
    00120
    00121   // 1) Configure and start the DFLL main reference generic clock:
    00122   // use the undivided RCOSC slow clock as source for the generic clock. The
    00123   // generic clock frequency will thus be ~115kHz.
    00124   GcConf.clock_source = SCIF_GCCTRL_CLK32;
    00125   GcConf.diven = OFF;
    00126   // Note: this function will start the AVR32_SCIF_GCLK_DFLL0_REF generic clock
    00127   // (i.e. the generic clock dedicated to be the DFLL main reference clock).
    00128   scif_dfll0_closedloop_mainref_gc_enable(&GcConf);
    00129
    00130   // 2) Configure and start the DFLL.
    00131   // The coarse value (= (fDFLL - SCIF_DFLL_MINFREQ_KHZ)*255/(SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ))
    00132   DfllConfig.coarse = ((unsigned long long)(EXAMPLE_FDFLL_HZ - SCIF_DFLL_MINFREQ_HZ)*255)/(SCIF_DFLL_MAXFREQ_HZ - SCIF_DFLL_MINFREQ_HZ);
    00133   // The fmul value (= (fDFLL*2^16)/fref, with fref being the frequency of the
    00134   // DFLL main reference generic clock)
    00135   DfllConfig.fmul = ((unsigned long long)EXAMPLE_FDFLL_HZ<<16)/SCIF_RC32K_FREQ_HZ;
    00136   // The maxstep value
    00137   DfllConfig.maxstep = 1;
    00138   scif_dfll0_closedloop_start(&DfllConfig);
    00139 }
    00140 // set flash wait state enabled
    00141 void flashc_set_wait_state(void)
    00142 {
    00143   volatile  avr32_flashcdw_t * AVR32_FLASHC = &AVR32_FLASHCDW;
    00144   AVR32_FLASHC->fcr=AVR32_FLASHC->fcr|0x0040;
    00145   //u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr};
    00146   //u_avr32_flashc_fcr.FCR.fws = wait_state;
    00147   //AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr;
    00148 }
    00149 //Flash high speed mode enabled
    00150 void flashc_hsben_command(void)
    00151 {
    00152   volatile  avr32_flashcdw_t * AVR32_FLASHC = &AVR32_FLASHCDW;
    00153   //flashc_wait_until_ready();
    00154   while ((AVR32_FLASHC->fsr & 0x01)==0);
    00155   AVR32_FLASHC->fcmd = 0xA5000010;//High Speed Mode Enable
    00156   //flashc_wait_until_ready();
    00157    while ((AVR32_FLASHC->fsr & 0x01)==0);
    00158 }
    00159
    00160 // enable port0 pull up except PA11,PA13,PA20,PA21
    00161 void gpio_enable_port0_pull_up(void)
    00162 {
    00163   volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[0];
    00164   gpio_port->puers =0x004FD7FF;
    00165 }
    00166 // enable port1 pull up except PB05,PB10
    00167 void gpio_enable_port1_pull_up(void)
    00168 {
    00169   volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[1];
    00170   gpio_port->puers =0x00001BDF;
    00171 }
    00172
    00173 // config the port0,port1 and the leds
    00174 void gpio_configuration(void)
    00175 {
    00176   gpio_enable_port0_pull_up();
    00177   gpio_enable_port1_pull_up();
    00178
    00179   gpio_clr_gpio_pin(AVR32_PIN_PA11);
    00180   gpio_clr_gpio_pin(AVR32_PIN_PB05);
    00181   gpio_clr_gpio_pin(AVR32_PIN_PA20);
    00182   gpio_clr_gpio_pin(AVR32_PIN_PA13);
    00183 }
    00184
    00185 //Enable OSC32crystal
    00186 void enableOSC32crystal(int pinsel, int mode, int startup)
    00187 {
    00188   union {
    00189     unsigned long               oscctrl32;
    00190     avr32_scif_oscctrl32_t       OSCCTRL32;
    00191   } oscctrl32 ;
    00192   union {
    00193     unsigned long               icr;
    00194     avr32_scif_icr_t            ICR;
    00195   } icr;
    00196
    00197   // Read register
    00198   oscctrl32.oscctrl32 = AVR32_SCIF.oscctrl32;
    00199   // Modify
    00200   oscctrl32.OSCCTRL32.osc32en = 1;
    00201   oscctrl32.OSCCTRL32.startup = startup;
    00202   oscctrl32.OSCCTRL32.mode = mode;
    00203   oscctrl32.OSCCTRL32.en32k = 1;
    00204   oscctrl32.OSCCTRL32.en1k = 0;
    00205   oscctrl32.OSCCTRL32.pinsel = pinsel;
    00206   AVR32_SCIF.oscctrl32 = oscctrl32.oscctrl32;
    00207   while(((AVR32_SCIF.isr)&AVR32_SCIF_ISR_OSC32RDY_MASK)!=AVR32_SCIF_ISR_OSC32RDY_MASK);
    00208   icr.icr = 0;
    00209   icr.ICR.osc32rdy = 1;
    00210   AVR32_SCIF.icr = icr.icr;
    00211 }
    00212 //enable the RTC32k and AST
    00213 void enable_rtc32k_ast(void)
    00214 {
    00215   enableOSC32crystal(0, 1, 5);          //enable the RTC
    00216   AVR32_AST.clock = 0x100;      // CLK CSEL
    00217   while((AVR32_AST.sr & 0x10000000));   // Wait on clkbusy
    00218   AVR32_AST.clock = 0x101;      // Enable clk
    00219   while((AVR32_AST.sr & 0x10000000));   // Wait on clkbusy
    00220   AVR32_AST.cv = 0;
    00221   while((AVR32_AST.sr & 0x01000000));
    00222   AVR32_AST.cr = 0x00000100;
    00223   while((AVR32_AST.sr & 0x01000000));
    00224   AVR32_AST.ar0 = 0x3FFFF;
    00225   while((AVR32_AST.sr & 0x01000000));
    00226   AVR32_AST.wer = 0x100;
    00227   while((AVR32_AST.sr & 0x01000000));
    00228   AVR32_AST.cr |= 1;
    00229   while((AVR32_AST.sr & 0x01000000));
    00230 }
    00231 //disable tht AST
    00232 void disable_ast(void)
    00233 {
    00234    AST->cr=AST->cr&0xFFFFFFFE;//disable the ast
    00235 }
    00236
    00237 //disable the Regulator and POR33
    00238 void disable_por33_regulator(void)
    00239 {
    00240   SCIF->unlock=0xAA00006C;
    00241   SCIF->rc32kcr=0x01;
    00242
    00243   SCIF->unlock=0xAA000044;
    00244   SCIF->vregcr=0x00090807;
    00245   while(SCIF->vregcr&0x00040000!=0x00040000);
    00246
    00247   SCIF->unlock=0xAA000044;
    00248   SCIF->vregcr=0x00190807;
    00249   while(SCIF->vregcr&0x00100000!=0x00100000);
    00250   SCIF->unlock=0xAA00006C;
    00251   SCIF->rc32kcr=0x00;
    00252 }
    00253 // choose the Reset Pullup, active low mode
    00254 void pm_ppcr_rstpun_mode(void)
    00255 {
    00256   AVR32_PM.unlock = 0xAA000000 | AVR32_PM_PPCR;
    00257   AVR32_PM.ppcr = 0x0;
    00258 }
    00259 //delay ms
    00260 void delayms(int ms)
    00261 {
    00262   int delay;
    00263   delay=ms;
    00264   for(delay=ms;delay>=0;delay--)
    00265   {
    00266        for(i=10; i>0; i--);
    00267   }
    00268 }
    00269
    00270
    00271 /* \brief This is an example that shows how to do the following:
    00272  * - generate a high frequency clock (~24MHz) with a DFLL in closed-loop mode
    00273  * - set-up a generic clock with a DFLL as a source
    00274  * - output the generic clock to GCLK_1_0
    00275  * - go into the frozen sleep mode (while still maintaining GCLK output)
    00276  *
    00277  */
    00278 int main(void)
    00279 {
    00280   long int ast_value=1;
    00281   ast_value=*(avr32_sram+1);
    00282   if(ast_value==0x00)
    00283   {
    00284     *(avr32_sram+1)=0x01;
    00285     //enable the RTC
    00286     enableOSC32crystal(0, 1, 5);
    00287     // choose the Reset Pullup, active low mode
    00288     pm_ppcr_rstpun_mode();
    00289     //config the port0,port1 and the leds
    00290     //port0 pull up except PA11,PA13,PA20,PA21
    00291     //port1 pull up except PB05,PB10
    00292     //clear the four led pins
    00293     gpio_configuration();
    00294     //blink the led
    00295     gpio_set_gpio_pin(AVR32_PIN_PA11);
    00296     delayms(500);
    00297     gpio_clr_gpio_pin(AVR32_PIN_PA11);
    00298     //disable tht AST
    00299     disable_ast();
    00300
    00301     // Generate a high frequency clock with a DFLL in closed-loop mode
    00302     local_start_dfll_clock();
    00303     // set flash wait state enabled
    00304     flashc_set_wait_state();
    00305     // Flash high speed mode enabled
    00306     flashc_hsben_command();
    00307     // Set the division ratio to apply to the main clock to 8 for each clock domain
    00308     pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_8);
    00309     // Switch the main clock source to the DFLL.
    00310     pm_set_mclk_source(PM_CLK_SRC_DFLL0);
    00311     // disable the Regulator and POR33
    00312     disable_por33_regulator();
    00313
    00314    while(1);
    00315   }
    00316 if(ast_value==0x01)
    00317   {
    00318    *(avr32_sram+1)=0x02;
    00319     enableOSC32crystal(0, 1, 5);//enable the RTC
    00320     // choose the Reset Pullup, active low mode
    00321     pm_ppcr_rstpun_mode();
    00322     //config the port0,port1 and the leds
    00323     //port0 pull up except PA11,PA13,PA20,PA21
    00324     //port1 pull up except PB05,PB10
    00325     //clear the four led pins
    00326     gpio_configuration();
    00327     //blink the led
    00328     gpio_set_gpio_pin(AVR32_PIN_PA13);
    00329     delayms(500);
    00330     gpio_clr_gpio_pin(AVR32_PIN_PA13);
    00331
    00332     // Generate a high frequency clock with a DFLL in closed-loop mode
    00333     local_start_dfll_clock();
    00334     // set flash wait state enabled
    00335     flashc_set_wait_state();
    00336     // Flash high speed mode enabled
    00337     flashc_hsben_command();
    00338     // Set the division ratio to apply to the main clock to 8 for each clock domain
    00339     pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_8);
    00340     // Switch the main clock source to the DFLL.
    00341     pm_set_mclk_source(PM_CLK_SRC_DFLL0);
    00342     //disable the Regulator and POR33
    00343     disable_por33_regulator();
    00344     //enter the Idle mode
    00345     PM_SLEEP(0);
    00346
    00347    while(1);
    00348
    00349   }
    00350 if(ast_value==0x02)
    00351   {
    00352     *(avr32_sram+1)=0x03;
    00353     // choose the Reset Pullup, active low mode
    00354     pm_ppcr_rstpun_mode();
    00355     //config the port0,port1 and the leds
    00356     //port0 pull up except PA11,PA13,PA20,PA21
    00357     //port1 pull up except PB05,PB10
    00358     //clear the four led pins
    00359     gpio_configuration();
    00360     //blink the led
    00361     gpio_set_gpio_pin(AVR32_PIN_PA20);
    00362     delayms(500);
    00363     gpio_clr_gpio_pin(AVR32_PIN_PA20);
    00364     //disable the Regulator and POR33
    00365     disable_por33_regulator();
    00366     //enable the RTC32k and AST
    00367     enable_rtc32k_ast();
    00368     //enter the static mode with the RTC
    00369     PM_SLEEP(5);
    00370     // when the static mode waken up by the AST, go to the static mode again
    00371     while(1)
    00372       {
    00373     AVR32_AST.scr = 0x100;
    00374     while((AVR32_AST.sr & 0x01000000));
    00375     //enter the static mode with the RTC
    00376     PM_SLEEP(5);
    00377       }
    00378    }
    00379
    00380 if(ast_value==0x03)
    00381
    00382   {
    00383     *(avr32_sram+1)=0x00;
    00384     // choose the Reset Pullup, active low mode
    00385     pm_ppcr_rstpun_mode();
    00386     //config the port0,port1 and the leds
    00387     //port0 pull up except PA11,PA13,PA20,PA21
    00388     //port1 pull up except PB05,PB10
    00389     //clear the four led pins
    00390     gpio_configuration();
    00391     //blink the led
    00392     gpio_set_gpio_pin(AVR32_PIN_PB05);
    00393     delayms(500);
    00394     gpio_clr_gpio_pin(AVR32_PIN_PB05);
    00395     //disable the Regulator and POR33
    00396     disable_por33_regulator();
    00397     //disable tht AST
    00398     disable_ast();
    00399     //stop the osc32
    00400     scif_stop_osc32();
    00401     //enter the static mode without the RTC
    00402     PM_SLEEP(5);
    00403     while(1);
    00404   }
    00405 else
    00406    {
    00407     *(avr32_sram+1)=0x01;
    00408    enableOSC32crystal(0, 1, 5);//enable the RTC
    00409     // choose the Reset Pullup, active low mode
    00410     pm_ppcr_rstpun_mode();
    00411     //config the port0,port1 and the leds
    00412     //port0 pull up except PA11,PA13,PA20,PA21
    00413     //port1 pull up except PB05,PB10
    00414     //clear the four led pins
    00415     gpio_configuration();
    00416     //blink the led
    00417     gpio_set_gpio_pin(AVR32_PIN_PA11);
    00418     delayms(500);
    00419     gpio_clr_gpio_pin(AVR32_PIN_PA11);
    00420     //disable tht AST
    00421     disable_ast();
    00422
    00423     // Generate a high frequency clock with a DFLL in closed-loop mode
    00424     local_start_dfll_clock();
    00425     // set flash wait state enabled
    00426     flashc_set_wait_state();
    00427     //Flash high speed mode enabled
    00428     flashc_hsben_command();
    00429     // Set the division ratio to apply to the main clock to 8 for each clock domain
    00430     pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_8);
    00431     // Switch the main clock source to the DFLL.
    00432     pm_set_mclk_source(PM_CLK_SRC_DFLL0);
    00433     //disable the Regulator and POR33
    00434     disable_por33_regulator();
    00435
    00436    while(1);
    00437   }
    00438 }
    00439