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# pm.c

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    00001 /*This file has been prepared for Doxygen automatic documentation generation.*/
    00016 /* Copyright (c) 2009 Atmel Corporation. All rights reserved.
    00017  *
    00018  * Redistribution and use in source and binary forms, with or without
    00019  * modification, are permitted provided that the following conditions are met:
    00020  *
    00021  * 1. Redistributions of source code must retain the above copyright notice, this
    00022  * list of conditions and the following disclaimer.
    00023  *
    00024  * 2. Redistributions in binary form must reproduce the above copyright notice,
    00025  * this list of conditions and the following disclaimer in the documentation
    00026  * and/or other materials provided with the distribution.
    00027  *
    00028  * 3. The name of Atmel may not be used to endorse or promote products derived
    00029  * from this software without specific prior written permission.
    00030  *
    00031  * 4. This software may only be redistributed and used in connection with an Atmel
    00032  * AVR product.
    00033  *
    00034  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
    00035  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    00036  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
    00037  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
    00038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
    00039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
    00040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
    00041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    00042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
    00043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
    00044  *
    00045  */
    00046
    00047 #include "compiler.h"
    00048 #include "pm.h"
    00049
    00050
    00053
    00054
    00055 typedef union
    00056 {
    00057   unsigned long                 mcctrl;
    00058   avr32_pm_mcctrl_t             MCCTRL;
    00059 } u_avr32_pm_mcctrl_t;
    00060
    00061 typedef union
    00062 {
    00063   unsigned long                 cksel;
    00064   avr32_pm_cksel_t              CKSEL;
    00065 } u_avr32_pm_cksel_t;
    00066
    00067 typedef union
    00068 {
    00069   unsigned long                 pll;
    00070   avr32_pm_pll_t                PLL;
    00071 } u_avr32_pm_pll_t;
    00072
    00073 typedef union
    00074 {
    00075   unsigned long                 oscctrl0;
    00076   avr32_pm_oscctrl0_t           OSCCTRL0;
    00077 } u_avr32_pm_oscctrl0_t;
    00078
    00079 typedef union
    00080 {
    00081   unsigned long                 oscctrl1;
    00082   avr32_pm_oscctrl1_t           OSCCTRL1;
    00083 } u_avr32_pm_oscctrl1_t;
    00084
    00085 typedef union
    00086 {
    00087   unsigned long                 oscctrl32;
    00088   avr32_pm_oscctrl32_t          OSCCTRL32;
    00089 } u_avr32_pm_oscctrl32_t;
    00090
    00091 typedef union
    00092 {
    00093   unsigned long                 ier;
    00094   avr32_pm_ier_t                IER;
    00095 } u_avr32_pm_ier_t;
    00096
    00097 typedef union
    00098 {
    00099   unsigned long                 idr;
    00100   avr32_pm_idr_t                IDR;
    00101 } u_avr32_pm_idr_t;
    00102
    00103 typedef union
    00104 {
    00105   unsigned long                 icr;
    00106   avr32_pm_icr_t                ICR;
    00107 } u_avr32_pm_icr_t;
    00108
    00109 typedef union
    00110 {
    00111   unsigned long                 gcctrl;
    00112   avr32_pm_gcctrl_t             GCCTRL;
    00113 } u_avr32_pm_gcctrl_t;
    00114
    00115 typedef union
    00116 {
    00117   unsigned long                 rccr;
    00118   avr32_pm_rccr_t               RCCR;
    00119 } u_avr32_pm_rccr_t;
    00120
    00121 typedef union
    00122 {
    00123   unsigned long                 bgcr;
    00124   avr32_pm_bgcr_t               BGCR;
    00125 } u_avr32_pm_bgcr_t;
    00126
    00127 typedef union
    00128 {
    00129   unsigned long                 vregcr;
    00130   avr32_pm_vregcr_t             VREGCR;
    00131 } u_avr32_pm_vregcr_t;
    00132
    00133 typedef union
    00134 {
    00135   unsigned long                 bod;
    00136   avr32_pm_bod_t                BOD;
    00137 } u_avr32_pm_bod_t;
    00138
    00140
    00141
    00147 static void pm_set_osc0_mode(volatile avr32_pm_t *pm, unsigned int mode)
    00148 {
    00149   // Read
    00150   u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};
    00151   // Modify
    00152   u_avr32_pm_oscctrl0.OSCCTRL0.mode = mode;
    00153   // Write
    00154   pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;
    00155 }
    00156
    00157
    00158 void pm_enable_osc0_ext_clock(volatile avr32_pm_t *pm)
    00159 {
    00160   pm_set_osc0_mode(pm, AVR32_PM_OSCCTRL0_MODE_EXT_CLOCK);
    00161 }
    00162
    00163
    00164 void pm_enable_osc0_crystal(volatile avr32_pm_t *pm, unsigned int fosc0)
    00165 {
    00166   pm_set_osc0_mode(pm, (fosc0 <  900000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G0 :
    00167                        (fosc0 < 3000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G1 :
    00168                        (fosc0 < 8000000) ? AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G2 :
    00169                                            AVR32_PM_OSCCTRL0_MODE_CRYSTAL_G3);
    00170 }
    00171
    00172
    00173 void pm_enable_clk0(volatile avr32_pm_t *pm, unsigned int startup)
    00174 {
    00175   pm_enable_clk0_no_wait(pm, startup);
    00176   pm_wait_for_clk0_ready(pm);
    00177 }
    00178
    00179
    00180 void pm_disable_clk0(volatile avr32_pm_t *pm)
    00181 {
    00182   pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC0EN_MASK;
    00183 }
    00184
    00185
    00186 void pm_enable_clk0_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
    00187 {
    00188   // Read register
    00189   u_avr32_pm_oscctrl0_t u_avr32_pm_oscctrl0 = {pm->oscctrl0};
    00190   // Modify
    00191   u_avr32_pm_oscctrl0.OSCCTRL0.startup = startup;
    00192   // Write back
    00193   pm->oscctrl0 = u_avr32_pm_oscctrl0.oscctrl0;
    00194
    00195   pm->mcctrl |= AVR32_PM_MCCTRL_OSC0EN_MASK;
    00196 }
    00197
    00198
    00199 void pm_wait_for_clk0_ready(volatile avr32_pm_t *pm)
    00200 {
    00201   while (!(pm->poscsr & AVR32_PM_POSCSR_OSC0RDY_MASK));
    00202 }
    00203
    00204
    00210 static void pm_set_osc1_mode(volatile avr32_pm_t *pm, unsigned int mode)
    00211 {
    00212   // Read
    00213   u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};
    00214   // Modify
    00215   u_avr32_pm_oscctrl1.OSCCTRL1.mode = mode;
    00216   // Write
    00217   pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;
    00218 }
    00219
    00220
    00221 void pm_enable_osc1_ext_clock(volatile avr32_pm_t *pm)
    00222 {
    00223   pm_set_osc1_mode(pm, AVR32_PM_OSCCTRL1_MODE_EXT_CLOCK);
    00224 }
    00225
    00226
    00227 void pm_enable_osc1_crystal(volatile avr32_pm_t *pm, unsigned int fosc1)
    00228 {
    00229   pm_set_osc1_mode(pm, (fosc1 <  900000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G0 :
    00230                        (fosc1 < 3000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G1 :
    00231                        (fosc1 < 8000000) ? AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G2 :
    00232                                            AVR32_PM_OSCCTRL1_MODE_CRYSTAL_G3);
    00233 }
    00234
    00235
    00236 void pm_enable_clk1(volatile avr32_pm_t *pm, unsigned int startup)
    00237 {
    00238   pm_enable_clk1_no_wait(pm, startup);
    00239   pm_wait_for_clk1_ready(pm);
    00240 }
    00241
    00242
    00243 void pm_disable_clk1(volatile avr32_pm_t *pm)
    00244 {
    00245   pm->mcctrl &= ~AVR32_PM_MCCTRL_OSC1EN_MASK;
    00246 }
    00247
    00248
    00249 void pm_enable_clk1_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
    00250 {
    00251   // Read register
    00252   u_avr32_pm_oscctrl1_t u_avr32_pm_oscctrl1 = {pm->oscctrl1};
    00253   // Modify
    00254   u_avr32_pm_oscctrl1.OSCCTRL1.startup = startup;
    00255   // Write back
    00256   pm->oscctrl1 = u_avr32_pm_oscctrl1.oscctrl1;
    00257
    00258   pm->mcctrl |= AVR32_PM_MCCTRL_OSC1EN_MASK;
    00259 }
    00260
    00261
    00262 void pm_wait_for_clk1_ready(volatile avr32_pm_t *pm)
    00263 {
    00264   while (!(pm->poscsr & AVR32_PM_POSCSR_OSC1RDY_MASK));
    00265 }
    00266
    00267
    00273 static void pm_set_osc32_mode(volatile avr32_pm_t *pm, unsigned int mode)
    00274 {
    00275   // Read
    00276   u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};
    00277   // Modify
    00278   u_avr32_pm_oscctrl32.OSCCTRL32.mode = mode;
    00279   // Write
    00280   pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;
    00281 }
    00282
    00283
    00284 void pm_enable_osc32_ext_clock(volatile avr32_pm_t *pm)
    00285 {
    00286   pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_EXT_CLOCK);
    00287 }
    00288
    00289
    00290 void pm_enable_osc32_crystal(volatile avr32_pm_t *pm)
    00291 {
    00292   pm_set_osc32_mode(pm, AVR32_PM_OSCCTRL32_MODE_CRYSTAL);
    00293 }
    00294
    00295
    00296 void pm_enable_clk32(volatile avr32_pm_t *pm, unsigned int startup)
    00297 {
    00298   pm_enable_clk32_no_wait(pm, startup);
    00299   pm_wait_for_clk32_ready(pm);
    00300 }
    00301
    00302
    00303 void pm_disable_clk32(volatile avr32_pm_t *pm)
    00304 {
    00305   pm->oscctrl32 &= ~AVR32_PM_OSCCTRL32_OSC32EN_MASK;
    00306 }
    00307
    00308
    00309 void pm_enable_clk32_no_wait(volatile avr32_pm_t *pm, unsigned int startup)
    00310 {
    00311   // Read register
    00312   u_avr32_pm_oscctrl32_t u_avr32_pm_oscctrl32 = {pm->oscctrl32};
    00313   // Modify
    00314   u_avr32_pm_oscctrl32.OSCCTRL32.osc32en = 1;
    00315   u_avr32_pm_oscctrl32.OSCCTRL32.startup = startup;
    00316   // Write back
    00317   pm->oscctrl32 = u_avr32_pm_oscctrl32.oscctrl32;
    00318 }
    00319
    00320
    00321 void pm_wait_for_clk32_ready(volatile avr32_pm_t *pm)
    00322 {
    00323   while (!(pm->poscsr & AVR32_PM_POSCSR_OSC32RDY_MASK));
    00324 }
    00325
    00326
    00327 void pm_cksel(volatile avr32_pm_t *pm,
    00328               unsigned int pbadiv,
    00329               unsigned int pbasel,
    00330               unsigned int pbbdiv,
    00331               unsigned int pbbsel,
    00332               unsigned int hsbdiv,
    00333               unsigned int hsbsel)
    00334 {
    00335   u_avr32_pm_cksel_t u_avr32_pm_cksel = {0};
    00336
    00337   u_avr32_pm_cksel.CKSEL.cpusel = hsbsel;
    00338   u_avr32_pm_cksel.CKSEL.cpudiv = hsbdiv;
    00339   u_avr32_pm_cksel.CKSEL.hsbsel = hsbsel;
    00340   u_avr32_pm_cksel.CKSEL.hsbdiv = hsbdiv;
    00341   u_avr32_pm_cksel.CKSEL.pbasel = pbasel;
    00342   u_avr32_pm_cksel.CKSEL.pbadiv = pbadiv;
    00343   u_avr32_pm_cksel.CKSEL.pbbsel = pbbsel;
    00344   u_avr32_pm_cksel.CKSEL.pbbdiv = pbbdiv;
    00345
    00346   pm->cksel = u_avr32_pm_cksel.cksel;
    00347
    00348   // Wait for ckrdy bit and then clear it
    00349   while (!(pm->poscsr & AVR32_PM_POSCSR_CKRDY_MASK));
    00350 }
    00351
    00352
    00353 void pm_gc_setup(volatile avr32_pm_t *pm,
    00354                   unsigned int gc,
    00355                   unsigned int osc_or_pll, // Use Osc (=0) or PLL (=1)
    00356                   unsigned int pll_osc, // Sel Osc0/PLL0 or Osc1/PLL1
    00357                   unsigned int diven,
    00358                   unsigned int div)
    00359 {
    00360   u_avr32_pm_gcctrl_t u_avr32_pm_gcctrl = {0};
    00361
    00362   u_avr32_pm_gcctrl.GCCTRL.oscsel = pll_osc;
    00363   u_avr32_pm_gcctrl.GCCTRL.pllsel = osc_or_pll;
    00364   u_avr32_pm_gcctrl.GCCTRL.diven  = diven;
    00365   u_avr32_pm_gcctrl.GCCTRL.div    = div;
    00366
    00367   pm->gcctrl[gc] = u_avr32_pm_gcctrl.gcctrl;
    00368 }
    00369
    00370
    00371 void pm_gc_enable(volatile avr32_pm_t *pm,
    00372                   unsigned int gc)
    00373 {
    00374   pm->gcctrl[gc] |= AVR32_PM_GCCTRL_CEN_MASK;
    00375 }
    00376
    00377
    00378 void pm_gc_disable(volatile avr32_pm_t *pm,
    00379                    unsigned int gc)
    00380 {
    00381   pm->gcctrl[gc] &= ~AVR32_PM_GCCTRL_CEN_MASK;
    00382 }
    00383
    00384
    00385 void pm_pll_setup(volatile avr32_pm_t *pm,
    00386                   unsigned int pll,
    00387                   unsigned int mul,
    00388                   unsigned int div,
    00389                   unsigned int osc,
    00390                   unsigned int lockcount)
    00391 {
    00392   u_avr32_pm_pll_t u_avr32_pm_pll = {0};
    00393
    00394   u_avr32_pm_pll.PLL.pllosc   = osc;
    00395   u_avr32_pm_pll.PLL.plldiv   = div;
    00396   u_avr32_pm_pll.PLL.pllmul   = mul;
    00397   u_avr32_pm_pll.PLL.pllcount = lockcount;
    00398
    00399   pm->pll[pll] = u_avr32_pm_pll.pll;
    00400 }
    00401
    00402
    00403 void pm_pll_set_option(volatile avr32_pm_t *pm,
    00404                        unsigned int pll,
    00405                        unsigned int pll_freq,
    00406                        unsigned int pll_div2,
    00407                        unsigned int pll_wbwdisable)
    00408 {
    00409   u_avr32_pm_pll_t u_avr32_pm_pll = {pm->pll[pll]};
    00410   u_avr32_pm_pll.PLL.pllopt = pll_freq | (pll_div2 << 1) | (pll_wbwdisable << 2);
    00411   pm->pll[pll] = u_avr32_pm_pll.pll;
    00412 }
    00413
    00414
    00415 unsigned int pm_pll_get_option(volatile avr32_pm_t *pm,
    00416                                unsigned int pll)
    00417 {
    00418   return (pm->pll[pll] & AVR32_PM_PLLOPT_MASK) >> AVR32_PM_PLLOPT_OFFSET;
    00419 }
    00420
    00421
    00422 void pm_pll_enable(volatile avr32_pm_t *pm,
    00423                   unsigned int pll)
    00424 {
    00425   pm->pll[pll] |= AVR32_PM_PLLEN_MASK;
    00426 }
    00427
    00428
    00429 void pm_pll_disable(volatile avr32_pm_t *pm,
    00430                   unsigned int pll)
    00431 {
    00432   pm->pll[pll] &= ~AVR32_PM_PLLEN_MASK;
    00433 }
    00434
    00435
    00436 void pm_wait_for_pll0_locked(volatile avr32_pm_t *pm)
    00437 {
    00438   while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK0_MASK));
    00439 }
    00440
    00441
    00442 void pm_wait_for_pll1_locked(volatile avr32_pm_t *pm)
    00443 {
    00444   while (!(pm->poscsr & AVR32_PM_POSCSR_LOCK1_MASK));
    00445 }
    00446
    00447
    00448 void pm_switch_to_clock(volatile avr32_pm_t *pm, unsigned long clock)
    00449 {
    00450   // Read
    00451   u_avr32_pm_mcctrl_t u_avr32_pm_mcctrl = {pm->mcctrl};
    00452   // Modify
    00453   u_avr32_pm_mcctrl.MCCTRL.mcsel = clock;
    00454   // Write back
    00455   pm->mcctrl = u_avr32_pm_mcctrl.mcctrl;
    00456 }
    00457
    00458
    00459 void pm_switch_to_osc0(volatile avr32_pm_t *pm, unsigned int fosc0, unsigned int startup)
    00460 {
    00461   pm_enable_osc0_crystal(pm, fosc0);            // Enable the Osc0 in crystal mode
    00462   pm_enable_clk0(pm, startup);                  // Crystal startup time - This parameter is critical and depends on the characteristics of the crystal
    00463   pm_switch_to_clock(pm, AVR32_PM_MCSEL_OSC0);  // Then switch main clock to Osc0
    00464 }
    00465
    00466
    00467 void pm_bod_enable_irq(volatile avr32_pm_t *pm)
    00468 {
    00469   pm->ier = AVR32_PM_IER_BODDET_MASK;
    00470 }
    00471
    00472
    00473 void pm_bod_disable_irq(volatile avr32_pm_t *pm)
    00474 {
    00475   Bool global_interrupt_enabled = Is_global_interrupt_enabled();
    00476
    00477   if (global_interrupt_enabled) Disable_global_interrupt();
    00478   pm->idr = AVR32_PM_IDR_BODDET_MASK;
    00479   pm->isr;
    00480   if (global_interrupt_enabled) Enable_global_interrupt();
    00481 }
    00482
    00483
    00484 void pm_bod_clear_irq(volatile avr32_pm_t *pm)
    00485 {
    00486   pm->icr = AVR32_PM_ICR_BODDET_MASK;
    00487 }
    00488
    00489
    00490 unsigned long pm_bod_get_irq_status(volatile avr32_pm_t *pm)
    00491 {
    00492   return ((pm->isr & AVR32_PM_ISR_BODDET_MASK) != 0);
    00493 }
    00494
    00495
    00496 unsigned long pm_bod_get_irq_enable_bit(volatile avr32_pm_t *pm)
    00497 {
    00498   return ((pm->imr & AVR32_PM_IMR_BODDET_MASK) != 0);
    00499 }
    00500
    00501
    00502 unsigned long pm_bod_get_level(volatile avr32_pm_t *pm)
    00503 {
    00504   return (pm->bod & AVR32_PM_BOD_LEVEL_MASK) >> AVR32_PM_BOD_LEVEL_OFFSET;
    00505 }
    00506
    00507
    00508 unsigned long pm_read_gplp(volatile avr32_pm_t *pm, unsigned long gplp)
    00509 {
    00510   return pm->gplp[gplp];
    00511 }
    00512
    00513
    00514 void pm_write_gplp(volatile avr32_pm_t *pm, unsigned long gplp, unsigned long value)
    00515 {
    00516   pm->gplp[gplp] = value;
    00517 }
    00518
    00519
    00520 long pm_enable_module(volatile avr32_pm_t *pm, unsigned long module)
    00521 {
    00522   unsigned long domain = module>>5;
    00523   unsigned long *regptr = (unsigned long*)(&(pm->cpumask) + domain*sizeof(unsigned long));
    00524
    00525   // Implementation-specific shortcut: the ckMASK registers are contiguous and
    00526   // memory-mapped in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK.
    00527
    00528   *regptr |= (module%32);
    00529
    00530   return PASS;
    00531 }
    00532
    00533 long pm_disable_module(volatile avr32_pm_t *pm, unsigned long module)
    00534 {
    00535   unsigned long domain = module>>5;
    00536   unsigned long *regptr = (unsigned long*)(&(pm->cpumask) + domain*sizeof(unsigned long));
    00537
    00538   // Implementation-specific shortcut: the ckMASK registers are contiguous and
    00539   // memory-mapped in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK.
    00540
    00541   *regptr &= ~(module%32);
    00542
    00543   return PASS;
    00544 }