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# scif_uc3l.h

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    00001 /*This file has been prepared for Doxygen automatic documentation generation.*/
    00016 /* Copyright (c) 2009 Atmel Corporation. All rights reserved.
    00017  *
    00018  * Redistribution and use in source and binary forms, with or without
    00019  * modification, are permitted provided that the following conditions are met:
    00020  *
    00021  * 1. Redistributions of source code must retain the above copyright notice, this
    00022  * list of conditions and the following disclaimer.
    00023  *
    00024  * 2. Redistributions in binary form must reproduce the above copyright notice,
    00025  * this list of conditions and the following disclaimer in the documentation
    00026  * and/or other materials provided with the distribution.
    00027  *
    00028  * 3. The name of Atmel may not be used to endorse or promote products derived
    00029  * from this software without specific prior written permission.
    00030  *
    00031  * 4. This software may only be redistributed and used in connection with an Atmel
    00032  * AVR product.
    00033  *
    00034  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
    00035  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    00036  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
    00037  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
    00038  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
    00039  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
    00040  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
    00041  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    00042  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
    00043  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
    00044  *
    00045  */
    00046 #ifndef _SCIF_UC3L_H_
    00047 #define _SCIF_UC3L_H_
    00048
    00049 #ifdef __cplusplus
    00050 extern "C" {
    00051 #endif
    00052
    00053 #include "compiler.h"
    00054
    00055 //  These defines are missing from or wrong in the toolchain header file ip_xxx.h or part.h
    00056 #ifdef AVR32_SCIF_100_H_INCLUDED
    00057 // Optionnal #undef AVR32_SCIF_GC_NO_DIV_CLOCK if the define values is wrong.
    00058 #define AVR32_SCIF_GC_NO_DIV_CLOCK       AVR32_GC_NO_DIV_CLOCK
    00059 #endif
    00060
    00061 #define AVR32_SCIF_OSCCTRL0_OSCEN_ENABLE      0x00000001
    00062 #define AVR32_SCIF_OSCCTRL0_OSCEN_DISABLE     0x00000000
    00063 #define AVR32_SCIF_OSCCTRL32_OSC32EN_ENABLE   0x00000001
    00064 #define AVR32_SCIF_OSCCTRL32_OSC32EN_DISABLE  0x00000000
    00065
    00066
    00068 #if ((__GNUC__ && (__AVR32_UC3L016__ || __AVR32_UC3L032__ || __AVR32_UC3L064__)) \
    00069     ||(__ICCAVR32__ && (__AT32UC3L016__ || __AT32UC3L032__ || __AT32UC3L064__  )))
    00070 // NOTE: the #if here above could be removed since we're in a file named scif_uc3l.h
    00071
    00073 #define SCIF_EXT_CRYSTAL_MIN_FREQ_HZ  4000000
    00075 #define SCIF_EXT_CRYSTAL_MAX_FREQ_HZ  20000000
    00076
    00078 typedef enum
    00079 {
    00080   SCIF_GCCTRL_SLOWCLOCK  = AVR32_SCIF_GC_USES_CLK_SLOW,
    00081   SCIF_GCCTRL_CLK32  = AVR32_SCIF_GC_USES_CLK_32,
    00082   SCIF_GCCTRL_DFLL0  = AVR32_SCIF_GC_USES_DFLL0,
    00083   SCIF_GCCTRL_OSC0  = AVR32_SCIF_GC_USES_OSC0,
    00084   SCIF_GCCTRL_RC120M  = AVR32_SCIF_GC_USES_RC120M,
    00085   SCIF_GCCTRL_CPUCLOCK  = AVR32_SCIF_GC_USES_CLK_CPU,
    00086   SCIF_GCCTRL_HSBCLOCK  = AVR32_SCIF_GC_USES_CLK_HSB,
    00087   SCIF_GCCTRL_PBACLOCK  = AVR32_SCIF_GC_USES_CLK_PBA,
    00088   SCIF_GCCTRL_PBBCLOCK  = AVR32_SCIF_GC_USES_CLK_PBB,
    00089   SCIF_GCCTRL_RC32K  = AVR32_SCIF_GC_USES_RC32K,
    00090   SCIF_GCCTRL_CRIPOSC  = AVR32_SCIF_GC_USES_CRIPOSC,
    00091   SCIF_GCCTRL_CLK1K  = AVR32_SCIF_GC_USES_CLK_1K,
    00092   SCIF_GCCTRL_OSCSEL_INVALID
    00093 } scif_gcctrl_oscsel_t;
    00094
    00096 // low frequency clock with high accuracy can be used as reference clock to get
    00097 // high accuracy on the output frequency.
    00098 typedef enum
    00099 {
    00100   SCIF_DFLL_CLKREF_GC_SRC_115KHZ = SCIF_GCCTRL_SLOWCLOCK,
    00101   SCIF_DFLL_CLKREF_GC_SRC_32KHZ = SCIF_GCCTRL_RC32K,
    00102   SCIF_DFLL_CLKREF_GC_SRC_INVALID
    00103 } scif_dfll_clkref_t;
    00104
    00106 #define SCIF_DFLL_MINFREQ_KHZ         20000
    00107 #define SCIF_DFLL_MINFREQ_HZ          20000000
    00108
    00110 #define SCIF_DFLL_MAXFREQ_KHZ         150000
    00111 #define SCIF_DFLL_MAXFREQ_HZ          150000000
    00112
    00114 #define SCIF_SLOWCLOCK_FREQ_HZ        AVR32_SCIF_RCOSC_FREQUENCY
    00115 #define SCIF_SLOWCLOCK_FREQ_KHZ       (SCIF_SLOWCLOCK_FREQ_HZ/100)
    00116
    00118 #define SCIF_RC32K_FREQ_HZ            32768
    00119 #define SCIF_RC32K_FREQ_KHZ           (SCIF_RC32K_FREQ_HZ/100)
    00120
    00122 #define SCIF_RC120M_FREQ_HZ           120000000
    00123 #define SCIF_RC120M_FREQ_KHZ          120000
    00124
    00125 #endif
    00126
    00127
    00129 #define SCIF_POLL_TIMEOUT             100000
    00130
    00132 #define SCIF_NOT_SUPPORTED            (-10000)
    00133
    00134
    00136 typedef enum
    00137 {
    00138   SCIF_OSC0  = 0,
    00139   SCIF_OSC1  = 1
    00140 } scif_osc_t;
    00141
    00143 typedef enum
    00144 {
    00145   SCIF_OSC_MODE_EXT_CLK = 0,            // For both OSC0 & OSC32
    00146   SCIF_OSC_MODE_2PIN_CRYSTAL = 1,       // For OSC0 only
    00147   SCIF_OSC_MODE_1PIN_CRYSTAL = 2,       // For OSC32 only
    00148   SCIF_OSC_MODE_NOT_SUPPORTED_1 = 3,
    00149   SCIF_OSC_MODE_2PIN_CRYSTAL_HICUR = 4, // For OSC32 only
    00150   SCIF_OSC_MODE_NOT_SUPPORTED_2 = 5,
    00151   SCIF_OSC_MODE_NOT_SUPPORTED_3 = 6
    00152 } scif_osc_mode_t;
    00153
    00155 typedef struct
    00156 {
    00158   unsigned long   freq_hz;
    00160   scif_osc_mode_t mode;
    00162   unsigned char   startup;
    00164   unsigned char   gain;
    00165 } scif_osc_opt_t;
    00166
    00168 typedef struct
    00169 {
    00171   scif_osc_mode_t mode;
    00173   unsigned char   startup;
    00175   bool            pinsel;
    00177   bool            en1k;
    00179   bool            en32k;
    00180 } scif_osc32_opt_t;
    00181
    00182
    00184 typedef struct
    00185 {
    00187   scif_gcctrl_oscsel_t clock_source;
    00189   unsigned int divider;
    00191   unsigned int diven;
    00192 } scif_gclk_opt_t;
    00193
    00194
    00196 typedef struct
    00197 {
    00198   unsigned int  fine;
    00199   unsigned int  coarse;
    00200 } scif_dfll_openloop_conf_t;
    00201
    00203 typedef struct
    00204 {
    00206   unsigned int    coarse;
    00208   unsigned int    fmul;
    00210   unsigned int    maxstep;
    00211 } scif_dfll_closedloop_conf_t;
    00212
    00214 typedef struct
    00215 {
    00217   unsigned int    use_random;
    00219   unsigned int    amplitude;
    00221   unsigned int    step_size;
    00222 } scif_dfll_ssg_conf_t;
    00223
    00224
    00226 #define SCIF_UNLOCK(reg)  (AVR32_SCIF.unlock = (AVR32_SCIF_UNLOCK_KEY_VALUE << AVR32_SCIF_UNLOCK_KEY_OFFSET)|(reg))
    00227
    00230
    00231
    00236  #if __GNUC__
    00237 __attribute__((__always_inline__))
    00238 #endif
    00239 extern __inline__ void scif_enable_interrupts(unsigned long mask)
    00240 {
    00241   AVR32_SCIF.ier = mask;
    00242 }
    00243
    00248 #if __GNUC__
    00249 __attribute__((__always_inline__))
    00250 #endif
    00251 extern __inline__ void scif_disable_interrupts(unsigned long mask)
    00252 {
    00253   AVR32_SCIF.idr = mask;
    00254 }
    00255
    00260 #if __GNUC__
    00261 __attribute__((__always_inline__))
    00262 #endif
    00263 extern __inline__ unsigned long scif_get_enabled_interrupts(void)
    00264 {
    00265   return(AVR32_SCIF.imr);
    00266 }
    00267
    00272 #if __GNUC__
    00273 __attribute__((__always_inline__))
    00274 #endif
    00275 extern __inline__ unsigned long scif_get_interrupts_status(void)
    00276 {
    00277   return(AVR32_SCIF.isr);
    00278 }
    00279
    00284 #if __GNUC__
    00285 __attribute__((__always_inline__))
    00286 #endif
    00287 extern __inline__ void scif_clear_interrupts_status(unsigned long mask)
    00288 {
    00289   AVR32_SCIF.icr = mask;
    00290 }
    00291
    00293
    00294
    00297
    00298
    00303 #if __GNUC__
    00304 __attribute__((__always_inline__))
    00305 #endif
    00306 extern __inline__ unsigned long scif_get_pclk_status(void)
    00307 {
    00308   return(AVR32_SCIF.pclksr);
    00309 }
    00310
    00312
    00313
    00316
    00317
    00331 extern long int scif_start_osc(scif_osc_t osc, const scif_osc_opt_t *opt, bool wait_for_ready);
    00332
    00341 extern bool scif_is_osc_ready(scif_osc_t osc);
    00342
    00351 extern long int scif_stop_osc(scif_osc_t osc);
    00352
    00362 extern long int scif_configure_osc_crystalmode(scif_osc_t osc, unsigned int fcrystal);
    00363
    00374 extern long int scif_enable_osc(scif_osc_t osc, unsigned int startup, bool wait_for_ready);
    00375
    00377
    00378
    00381
    00382
    00395 extern long int scif_start_osc32(const scif_osc32_opt_t *opt, bool wait_for_ready);
    00396
    00403 #if __GNUC__
    00404 __attribute__((__always_inline__))
    00405 #endif
    00406 extern __inline__ bool scif_is_osc32_ready()
    00407 {
    00408   return((AVR32_SCIF.pclksr & AVR32_SCIF_PCLKSR_OSC32RDY_MASK)>>AVR32_SCIF_PCLKSR_OSC32RDY_OFFSET);
    00409 }
    00410
    00414 #if __GNUC__
    00415 __attribute__((__always_inline__))
    00416 #endif
    00417 extern __inline__ void scif_osc32_1kout_ena()
    00418 {
    00419   AVR32_SCIF.oscctrl32 |= AVR32_SCIF_EN1K_MASK;
    00420 }
    00421
    00425 #if __GNUC__
    00426 __attribute__((__always_inline__))
    00427 #endif
    00428 extern __inline__ void scif_osc32_1kout_dis()
    00429 {
    00430   AVR32_SCIF.oscctrl32 &= ~AVR32_SCIF_EN1K_MASK;
    00431 }
    00432
    00436 #if __GNUC__
    00437 __attribute__((__always_inline__))
    00438 #endif
    00439 extern __inline__ void scif_osc32_32kout_ena()
    00440 {
    00441   AVR32_SCIF.oscctrl32 |= AVR32_SCIF_EN32K_MASK;
    00442 }
    00443
    00447 #if __GNUC__
    00448 __attribute__((__always_inline__))
    00449 #endif
    00450 extern __inline__ void scif_osc32_32kout_dis()
    00451 {
    00452   AVR32_SCIF.oscctrl32 &= ~AVR32_SCIF_EN32K_MASK;
    00453 }
    00454
    00461 extern long int scif_stop_osc32();
    00462
    00464
    00465
    00468
    00469
    00478 extern long int scif_dfll0_openloop_start(const scif_dfll_openloop_conf_t *pdfllconfig);
    00479
    00488 extern long int scif_dfll0_openloop_start_auto(unsigned long TargetFreqkHz);
    00489
    00498 extern long int scif_dfll0_openloop_updatefreq(const scif_dfll_openloop_conf_t *pdfllconfig);
    00499
    00508 extern long int scif_dfll0_openloop_updatefreq_auto(unsigned long TargetFreq);
    00509
    00516 extern long int scif_dfll0_openloop_stop(void);
    00517
    00527 extern long int scif_dfll0_ssg_gc_enable(void);
    00528
    00537 extern long int scif_dfll0_ssg_enable(scif_dfll_ssg_conf_t *pssg_conf);
    00538
    00545 #define scif_dfll0_closedloop_mainref_gc_enable(conf) scif_start_gclk(AVR32_SCIF_GCLK_DFLL0_REF, conf)
    00546
    00557 extern long int scif_dfll0_closedloop_start(const scif_dfll_closedloop_conf_t *pdfllconfig);
    00558
    00572 extern long int scif_dfll0_closedloop_configure_and_start( scif_dfll_clkref_t dfll_main_ref_gc,
    00573                                                     unsigned long long target_freq_hz,
    00574                                                     bool enable_ssg);
    00575
    00585 #define scif_dfll0_closedloop_dither_gc_enable()  scif_dfll0_ssg_gc_enable()
    00586
    00587
    00588
    00590
    00591
    00594
    00595
    00596
    00598
    00599
    00602
    00603
    00606 extern void scif_start_rc120M(void);
    00607
    00610 extern void scif_stop_rc120M(void);
    00611
    00613
    00614
    00617
    00618
    00621 extern void scif_start_rc32k(void);
    00622
    00625 extern void scif_stop_rc32k(void);
    00626
    00628
    00629
    00632
    00633
    00643 extern long int scif_start_gclk(unsigned int gclk, const scif_gclk_opt_t *opt);
    00644
    00656 extern long int scif_stop_gclk(unsigned int gclk);
    00657
    00672 extern long int scif_gc_setup(unsigned int gclk, scif_gcctrl_oscsel_t clk_src, unsigned int diven, unsigned int divfactor);
    00673
    00682 extern long int scif_gc_enable(unsigned int gclk);
    00683
    00685
    00686
    00689
    00690
    00691
    00693
    00694
    00697
    00698
    00707 long int scif_pclksr_statushigh_wait(unsigned long statusMask);
    00708
    00710
    00711 #ifdef __cplusplus
    00712 }
    00713 #endif
    00714
    00715 #endif  // _SCIF_UC3L_H_