# pico_power_uc3l064.c File Reference

DFLL and main clock configuration and generic clock configuration and sleep mode example. More...

`#include "board.h"`
`#include "gpio.h"`
`#include "scif_uc3l.h"`
`#include "power_clocks_lib.h"`

Go to the source code of this file.

## Functions
void | delayms (int ms)
void | disable_ast (void)
void | disable_por33_regulator (void)
void | enable_rtc32k_ast (void)
void | enableOSC32crystal (int pinsel, int mode, int startup)
void | flashc_hsben_command (void)
void | flashc_set_wait_state (void)
void | gpio_configuration (void)
void | gpio_enable_port0_pull_up (void)
void | gpio_enable_port1_pull_up (void)
static void | local_start_dfll_clock (void)
| Generate a high frequency clock with a DFLL running in closed-loop mode.
int | main (void)
void | pm_ppcr_rstpun_mode (void)
## Generic Clock Configuration
#define | EXAMPLE_FDFLL_HZ 50000000
| The target output frequency (50MHz) of the DFLL.
#define | EXAMPLE_FDFLL_KHZ 50000
| The target output frequency (50MHz) of the DFLL.
#define | PM_SLEEP(sleep_mode)
| The target output frequency (50MHz) of the DFLL.
volatile avr32_ast_t * | AST = &AVR32_AST
| The target output frequency (50MHz) of the DFLL.
U8 * | avr32_sram = AVR32_SRAM
| The target output frequency (50MHz) of the DFLL.
volatile int | i
| The target output frequency (50MHz) of the DFLL.
volatile avr32_scif_t * | SCIF = &AVR32_SCIF
| The target output frequency (50MHz) of the DFLL.

## Detailed Description

DFLL and main clock configuration and generic clock configuration and sleep mode example.

- Compiler: IAR EWAVR32 and GNU GCC for AVR32
- Supported devices: All AVR32 devices with the SCIF and PM modules.
- AppNote:

Author:
  Atmel Corporation: http://www.atmel.com
  Support and FAQ: http://support.atmel.no/

Definition in file pico_power_uc3l064.c.

## Define Documentation

#define EXAMPLE_FDFLL_HZ 50000000

The target output frequency (50MHz) of the DFLL.

Definition at line 93 of file pico_power_uc3l064.c.

Referenced by local_start_dfll_clock().

#define EXAMPLE_FDFLL_KHZ 50000

The target output frequency (50MHz) of the DFLL.

Definition at line 92 of file pico_power_uc3l064.c.

#define PM_SLEEP | ( | sleep_mode |  | ) |

Value:

    {__asm__ __volatile__ (\
            "MOV    R2, 0\n\t"\
            "SBR    R2, 28\n\t"\
            "sleep "STRINGZ(sleep_mode));}

The target output frequency (50MHz) of the DFLL.

Definition at line 101 of file pico_power_uc3l064.c.

Referenced by main().

## Function Documentation

void delayms | ( | int | ms | ) |

Definition at line 260 of file pico_power_uc3l064.c.

References i.

Referenced by main().

    00261 {
    00262   int delay;
    00263   delay=ms;
    00264   for(delay=ms;delay>=0;delay--)
    00265   {
    00266        for(i=10; i>0; i--);
    00267   }
    00268 }

void disable_ast | ( | void |  | ) |

Definition at line 232 of file pico_power_uc3l064.c.

References AST.

Referenced by main().

    00233 {
    00234    AST->cr=AST->cr&0xFFFFFFFE;//disable the ast
    00235 }

void disable_por33_regulator | ( | void |  | ) |

Definition at line 238 of file pico_power_uc3l064.c.

References SCIF.

Referenced by main().

    00239 {
    00240   SCIF->unlock=0xAA00006C;
    00241   SCIF->rc32kcr=0x01;
    00242
    00243   SCIF->unlock=0xAA000044;
    00244   SCIF->vregcr=0x00090807;
    00245   while(SCIF->vregcr&0x00040000!=0x00040000);
    00246
    00247   SCIF->unlock=0xAA000044;
    00248   SCIF->vregcr=0x00190807;
    00249   while(SCIF->vregcr&0x00100000!=0x00100000);
    00250   SCIF->unlock=0xAA00006C;
    00251   SCIF->rc32kcr=0x00;
    00252 }

void enable_rtc32k_ast | ( | void |  | ) |

Definition at line 213 of file pico_power_uc3l064.c.

References enableOSC32crystal().

Referenced by main().

    00214 {
    00215   enableOSC32crystal(0, 1, 5);          //enable the RTC
    00216   AVR32_AST.clock = 0x100;      // CLK CSEL
    00217   while((AVR32_AST.sr & 0x10000000));   // Wait on clkbusy
    00218   AVR32_AST.clock = 0x101;      // Enable clk
    00219   while((AVR32_AST.sr & 0x10000000));   // Wait on clkbusy
    00220   AVR32_AST.cv = 0;
    00221   while((AVR32_AST.sr & 0x01000000));
    00222   AVR32_AST.cr = 0x00000100;
    00223   while((AVR32_AST.sr & 0x01000000));
    00224   AVR32_AST.ar0 = 0x3FFFF;
    00225   while((AVR32_AST.sr & 0x01000000));
    00226   AVR32_AST.wer = 0x100;
    00227   while((AVR32_AST.sr & 0x01000000));
    00228   AVR32_AST.cr |= 1;
    00229   while((AVR32_AST.sr & 0x01000000));
    00230 }

void enableOSC32crystal | ( | int | pinsel,
|  | int | mode,
|  | int | startup |
| ) |  |  |

Definition at line 186 of file pico_power_uc3l064.c.

Referenced by enable_rtc32k_ast(), and main().

    00187 {
    00188   union {
    00189     unsigned long               oscctrl32;
    00190     avr32_scif_oscctrl32_t       OSCCTRL32;
    00191   } oscctrl32 ;
    00192   union {
    00193     unsigned long               icr;
    00194     avr32_scif_icr_t            ICR;
    00195   } icr;
    00196
    00197   // Read register
    00198   oscctrl32.oscctrl32 = AVR32_SCIF.oscctrl32;
    00199   // Modify
    00200   oscctrl32.OSCCTRL32.osc32en = 1;
    00201   oscctrl32.OSCCTRL32.startup = startup;
    00202   oscctrl32.OSCCTRL32.mode = mode;
    00203   oscctrl32.OSCCTRL32.en32k = 1;
    00204   oscctrl32.OSCCTRL32.en1k = 0;
    00205   oscctrl32.OSCCTRL32.pinsel = pinsel;
    00206   AVR32_SCIF.oscctrl32 = oscctrl32.oscctrl32;
    00207   while(((AVR32_SCIF.isr)&AVR32_SCIF_ISR_OSC32RDY_MASK)!=AVR32_SCIF_ISR_OSC32RDY_MASK);
    00208   icr.icr = 0;
    00209   icr.ICR.osc32rdy = 1;
    00210   AVR32_SCIF.icr = icr.icr;
    00211 }

void flashc_hsben_command | ( | void |  | ) |

Definition at line 150 of file pico_power_uc3l064.c.

Referenced by main().

    00151 {
    00152   volatile  avr32_flashcdw_t * AVR32_FLASHC = &AVR32_FLASHCDW;
    00153   //flashc_wait_until_ready();
    00154   while ((AVR32_FLASHC->fsr & 0x01)==0);
    00155   AVR32_FLASHC->fcmd = 0xA5000010;//High Speed Mode Enable
    00156   //flashc_wait_until_ready();
    00157    while ((AVR32_FLASHC->fsr & 0x01)==0);
    00158 }

void flashc_set_wait_state | ( | void |  | ) |

Definition at line 141 of file pico_power_uc3l064.c.

    00142 {
    00143   volatile  avr32_flashcdw_t * AVR32_FLASHC = &AVR32_FLASHCDW;
    00144   AVR32_FLASHC->fcr=AVR32_FLASHC->fcr|0x0040;
    00145   //u_avr32_flashc_fcr_t u_avr32_flashc_fcr = {AVR32_FLASHC.fcr};
    00146   //u_avr32_flashc_fcr.FCR.fws = wait_state;
    00147   //AVR32_FLASHC.fcr = u_avr32_flashc_fcr.fcr;
    00148 }

void gpio_configuration | ( | void |  | ) |

Definition at line 174 of file pico_power_uc3l064.c.

References gpio_clr_gpio_pin(), gpio_enable_port0_pull_up(), and gpio_enable_port1_pull_up().

Referenced by main().

    00175 {
    00176   gpio_enable_port0_pull_up();
    00177   gpio_enable_port1_pull_up();
    00178
    00179   gpio_clr_gpio_pin(AVR32_PIN_PA11);
    00180   gpio_clr_gpio_pin(AVR32_PIN_PB05);
    00181   gpio_clr_gpio_pin(AVR32_PIN_PA20);
    00182   gpio_clr_gpio_pin(AVR32_PIN_PA13);
    00183 }

void gpio_enable_port0_pull_up | ( | void |  | ) |

Definition at line 161 of file pico_power_uc3l064.c.

Referenced by gpio_configuration().

    00162 {
    00163   volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[0];
    00164   gpio_port->puers =0x004FD7FF;
    00165 }

void gpio_enable_port1_pull_up | ( | void |  | ) |

Definition at line 167 of file pico_power_uc3l064.c.

Referenced by gpio_configuration().

    00168 {
    00169   volatile avr32_gpio_port_t *gpio_port = &AVR32_GPIO.port[1];
    00170   gpio_port->puers =0x00001BDF;
    00171 }

static void local_start_dfll_clock | ( | void |  | ) | `[static]`

Generate a high frequency clock with a DFLL running in closed-loop mode.

Definition at line 115 of file pico_power_uc3l064.c.

References scif_gclk_opt_t::clock_source, scif_dfll_closedloop_conf_t::coarse, scif_gclk_opt_t::diven, EXAMPLE_FDFLL_HZ, scif_dfll_closedloop_conf_t::fmul, scif_dfll_closedloop_conf_t::maxstep, OFF, scif_dfll0_closedloop_mainref_gc_enable, scif_dfll0_closedloop_start(), SCIF_DFLL_MAXFREQ_HZ, SCIF_DFLL_MINFREQ_HZ, SCIF_GCCTRL_CLK32, and SCIF_RC32K_FREQ_HZ.

Referenced by main().

    00116 {
    00117   scif_dfll_closedloop_conf_t DfllConfig;
    00118   scif_gclk_opt_t             GcConf;
    00119
    00120
    00121   // 1) Configure and start the DFLL main reference generic clock:
    00122   // use the undivided RCOSC slow clock as source for the generic clock. The
    00123   // generic clock frequency will thus be ~115kHz.
    00124   GcConf.clock_source = SCIF_GCCTRL_CLK32;
    00125   GcConf.diven = OFF;
    00126   // Note: this function will start the AVR32_SCIF_GCLK_DFLL0_REF generic clock
    00127   // (i.e. the generic clock dedicated to be the DFLL main reference clock).
    00128   scif_dfll0_closedloop_mainref_gc_enable(&GcConf);
    00129
    00130   // 2) Configure and start the DFLL.
    00131   // The coarse value (= (fDFLL - SCIF_DFLL_MINFREQ_KHZ)*255/(SCIF_DFLL_MAXFREQ_KHZ - SCIF_DFLL_MINFREQ_KHZ))
    00132   DfllConfig.coarse = ((unsigned long long)(EXAMPLE_FDFLL_HZ - SCIF_DFLL_MINFREQ_HZ)*255)/(SCIF_DFLL_MAXFREQ_HZ - SCIF_DFLL_MINFREQ_HZ);
    00133   // The fmul value (= (fDFLL*2^16)/fref, with fref being the frequency of the
    00134   // DFLL main reference generic clock)
    00135   DfllConfig.fmul = ((unsigned long long)EXAMPLE_FDFLL_HZ<<16)/SCIF_RC32K_FREQ_HZ;
    00136   // The maxstep value
    00137   DfllConfig.maxstep = 1;
    00138   scif_dfll0_closedloop_start(&DfllConfig);
    00139 }

int main | ( | void |  | ) |

Definition at line 278 of file pico_power_uc3l064.c.

References avr32_sram, delayms(), disable_ast(), disable_por33_regulator(), enable_rtc32k_ast(), enableOSC32crystal(), flashc_hsben_command(), flashc_set_wait_state(), gpio_clr_gpio_pin(), gpio_configuration(), gpio_set_gpio_pin(), local_start_dfll_clock(), PM_CKSEL_DIVRATIO_8, PM_CLK_SRC_DFLL0, pm_ppcr_rstpun_mode(), pm_set_clk_domain_div(), pm_set_mclk_source(), PM_SLEEP, and scif_stop_osc32().

    00279 {
    00280   long int ast_value=1;
    00281   ast_value=*(avr32_sram+1);
    00282   if(ast_value==0x00)
    00283   {
    00284     *(avr32_sram+1)=0x01;
    00285     //enable the RTC
    00286     enableOSC32crystal(0, 1, 5);
    00287     // choose the Reset Pullup, active low mode
    00288     pm_ppcr_rstpun_mode();
    00289     //config the port0,port1 and the leds
    00290     //port0 pull up except PA11,PA13,PA20,PA21
    00291     //port1 pull up except PB05,PB10
    00292     //clear the four led pins
    00293     gpio_configuration();
    00294     //blink the led
    00295     gpio_set_gpio_pin(AVR32_PIN_PA11);
    00296     delayms(500);
    00297     gpio_clr_gpio_pin(AVR32_PIN_PA11);
    00298     //disable tht AST
    00299     disable_ast();
    00300
    00301     // Generate a high frequency clock with a DFLL in closed-loop mode
    00302     local_start_dfll_clock();
    00303     // set flash wait state enabled
    00304     flashc_set_wait_state();
    00305     // Flash high speed mode enabled
    00306     flashc_hsben_command();
    00307     // Set the division ratio to apply to the main clock to 8 for each clock domain
    00308     pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_8);
    00309     // Switch the main clock source to the DFLL.
    00310     pm_set_mclk_source(PM_CLK_SRC_DFLL0);
    00311     // disable the Regulator and POR33
    00312     disable_por33_regulator();
    00313
    00314    while(1);
    00315   }
    00316 if(ast_value==0x01)
    00317   {
    00318    *(avr32_sram+1)=0x02;
    00319     enableOSC32crystal(0, 1, 5);//enable the RTC
    00320     // choose the Reset Pullup, active low mode
    00321     pm_ppcr_rstpun_mode();
    00322     //config the port0,port1 and the leds
    00323     //port0 pull up except PA11,PA13,PA20,PA21
    00324     //port1 pull up except PB05,PB10
    00325     //clear the four led pins
    00326     gpio_configuration();
    00327     //blink the led
    00328     gpio_set_gpio_pin(AVR32_PIN_PA13);
    00329     delayms(500);
    00330     gpio_clr_gpio_pin(AVR32_PIN_PA13);
    00331
    00332     // Generate a high frequency clock with a DFLL in closed-loop mode
    00333     local_start_dfll_clock();
    00334     // set flash wait state enabled
    00335     flashc_set_wait_state();
    00336     // Flash high speed mode enabled
    00337     flashc_hsben_command();
    00338     // Set the division ratio to apply to the main clock to 8 for each clock domain
    00339     pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_8);
    00340     // Switch the main clock source to the DFLL.
    00341     pm_set_mclk_source(PM_CLK_SRC_DFLL0);
    00342     //disable the Regulator and POR33
    00343     disable_por33_regulator();
    00344     //enter the Idle mode
    00345     PM_SLEEP(0);
    00346
    00347    while(1);
    00348
    00349   }
    00350 if(ast_value==0x02)
    00351   {
    00352     *(avr32_sram+1)=0x03;
    00353     // choose the Reset Pullup, active low mode
    00354     pm_ppcr_rstpun_mode();
    00355     //config the port0,port1 and the leds
    00356     //port0 pull up except PA11,PA13,PA20,PA21
    00357     //port1 pull up except PB05,PB10
    00358     //clear the four led pins
    00359     gpio_configuration();
    00360     //blink the led
    00361     gpio_set_gpio_pin(AVR32_PIN_PA20);
    00362     delayms(500);
    00363     gpio_clr_gpio_pin(AVR32_PIN_PA20);
    00364     //disable the Regulator and POR33
    00365     disable_por33_regulator();
    00366     //enable the RTC32k and AST
    00367     enable_rtc32k_ast();
    00368     //enter the static mode with the RTC
    00369     PM_SLEEP(5);
    00370     // when the static mode waken up by the AST, go to the static mode again
    00371     while(1)
    00372       {
    00373     AVR32_AST.scr = 0x100;
    00374     while((AVR32_AST.sr & 0x01000000));
    00375     //enter the static mode with the RTC
    00376     PM_SLEEP(5);
    00377       }
    00378    }
    00379
    00380 if(ast_value==0x03)
    00381
    00382   {
    00383     *(avr32_sram+1)=0x00;
    00384     // choose the Reset Pullup, active low mode
    00385     pm_ppcr_rstpun_mode();
    00386     //config the port0,port1 and the leds
    00387     //port0 pull up except PA11,PA13,PA20,PA21
    00388     //port1 pull up except PB05,PB10
    00389     //clear the four led pins
    00390     gpio_configuration();
    00391     //blink the led
    00392     gpio_set_gpio_pin(AVR32_PIN_PB05);
    00393     delayms(500);
    00394     gpio_clr_gpio_pin(AVR32_PIN_PB05);
    00395     //disable the Regulator and POR33
    00396     disable_por33_regulator();
    00397     //disable tht AST
    00398     disable_ast();
    00399     //stop the osc32
    00400     scif_stop_osc32();
    00401     //enter the static mode without the RTC
    00402     PM_SLEEP(5);
    00403     while(1);
    00404   }
    00405 else
    00406    {
    00407     *(avr32_sram+1)=0x01;
    00408    enableOSC32crystal(0, 1, 5);//enable the RTC
    00409     // choose the Reset Pullup, active low mode
    00410     pm_ppcr_rstpun_mode();
    00411     //config the port0,port1 and the leds
    00412     //port0 pull up except PA11,PA13,PA20,PA21
    00413     //port1 pull up except PB05,PB10
    00414     //clear the four led pins
    00415     gpio_configuration();
    00416     //blink the led
    00417     gpio_set_gpio_pin(AVR32_PIN_PA11);
    00418     delayms(500);
    00419     gpio_clr_gpio_pin(AVR32_PIN_PA11);
    00420     //disable tht AST
    00421     disable_ast();
    00422
    00423     // Generate a high frequency clock with a DFLL in closed-loop mode
    00424     local_start_dfll_clock();
    00425     // set flash wait state enabled
    00426     flashc_set_wait_state();
    00427     //Flash high speed mode enabled
    00428     flashc_hsben_command();
    00429     // Set the division ratio to apply to the main clock to 8 for each clock domain
    00430     pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, PM_CKSEL_DIVRATIO_8);
    00431     // Switch the main clock source to the DFLL.
    00432     pm_set_mclk_source(PM_CLK_SRC_DFLL0);
    00433     //disable the Regulator and POR33
    00434     disable_por33_regulator();
    00435
    00436    while(1);
    00437   }
    00438 }

void pm_ppcr_rstpun_mode | ( | void |  | ) |

Definition at line 254 of file pico_power_uc3l064.c.

Referenced by main().

    00255 {
    00256   AVR32_PM.unlock = 0xAA000000 | AVR32_PM_PPCR;
    00257   AVR32_PM.ppcr = 0x0;
    00258 }

## Variable Documentation

volatile avr32_ast_t* AST = &AVR32_AST

The target output frequency (50MHz) of the DFLL.

Definition at line 97 of file pico_power_uc3l064.c.

Referenced by disable_ast().

U8* avr32_sram = AVR32_SRAM

The target output frequency (50MHz) of the DFLL.

Definition at line 98 of file pico_power_uc3l064.c.

Referenced by main().

volatile int i

The target output frequency (50MHz) of the DFLL.

Definition at line 95 of file pico_power_uc3l064.c.

Referenced by delayms(), flashcdw_memcpy(), flashcdw_memset64(), gpio_enable_gpio(), and gpio_enable_module().

volatile avr32_scif_t* SCIF = &AVR32_SCIF

The target output frequency (50MHz) of the DFLL.

Definition at line 96 of file pico_power_uc3l064.c.

Referenced by disable_por33_regulator().