# pm_uc3l.h File Reference

Power Manager(PM) driver interface. More...

`#include <avr32/io.h>`
`#include "compiler.h"`

Go to the source code of this file.

## Defines
#define | PM_NOT_SUPPORTED (-10000)
| Define "not supported" for the power manager features.
#define | PM_POLL_TIMEOUT 100000
| The timeguard used for polling (expressed in ticks).
#define | PM_UNLOCK(reg) (AVR32_PM.unlock = (unsigned long)(AVR32_PM_UNLOCK_KEY_VALUE << AVR32_PM_UNLOCK_KEY_OFFSET)|(reg))
| Unlock PM register macro.
## Enumerations
enum | pm_clk_domain_t { PM_CLK_DOMAIN_0 = AVR32_PM_CLK_GRP_CPU, PM_CLK_DOMAIN_1 = AVR32_PM_CLK_GRP_HSB, PM_CLK_DOMAIN_2 = AVR32_PM_CLK_GRP_PBA, PM_CLK_DOMAIN_3 = AVR32_PM_CLK_GRP_PBB, PM_CLK_DOMAIN_INVALID }
| The clock domains of the power manager. More...
enum | pm_clk_src_t { PM_CLK_SRC_SLOW = AVR32_PM_MCSEL_SLOW, PM_CLK_SRC_OSC0 = AVR32_PM_MCSEL_OSC0, PM_CLK_SRC_DFLL0 = AVR32_PM_MCSEL_DFLL0, PM_CLK_SRC_RC120M = AVR32_PM_MCSEL_RC120M, PM_CLK_SRC_INVALID }
| Device-specific data. More...
enum | pm_divratio_max_t { PM_CPUSEL_DIVRATIO_MAX = AVR32_PM_CPUSEL_CPUSEL_MASK >> AVR32_PM_CPUSEL_CPUSEL_OFFSET, PM_HSBSEL_DIVRATIO_MAX = AVR32_PM_HSBSEL_HSBSEL_MASK >> AVR32_PM_HSBSEL_HSBSEL_OFFSET, PM_PBASEL_DIVRATIO_MAX = AVR32_PM_PBASEL_PBSEL_MASK >> AVR32_PM_PBASEL_PBSEL_OFFSET, PM_PBBSEL_DIVRATIO_MAX = AVR32_PM_PBBSEL_PBSEL_MASK >> AVR32_PM_PBBSEL_PBSEL_OFFSET }
| The maximum synchronous clock division ratio for each clock domain. More...
enum | pm_divratio_t { PM_CKSEL_DIVRATIO_2 = 0, PM_CKSEL_DIVRATIO_4, PM_CKSEL_DIVRATIO_8, PM_CKSEL_DIVRATIO_16, PM_CKSEL_DIVRATIO_32, PM_CKSEL_DIVRATIO_64, PM_CKSEL_DIVRATIO_128, PM_CKSEL_DIVRATIO_256, PM_CKSEL_DIVRATIO_ERROR }
| The possible synchronous clock division ratio. More...
## Functions
Interrupt Functions
__inline__ void | pm_clear_interrupt_status (unsigned long mask)
| Clear raised interrupts from the power manager.
__inline__ void | pm_disable_interrupts (unsigned long mask)
| Disable power manager interrupts.
__inline__ void | pm_enable_interrupts (unsigned long mask)
| Enable power manager interrupts.
__inline__ unsigned long | pm_get_enabled_interrupts (void)
| Read the enabled power manager interrupts.
__inline__ unsigned long | pm_get_interrupts_status (void)
| Read the interrupts status of the power manager.
Clock Functions
long | pm_config_mainclk_safety (bool cfd, bool ocp, bool final)
| Configure the main clock safety mechanisms.
long | pm_disable_clk_domain_div (pm_clk_domain_t clock_domain)
| Disable the division ratio for a clock domain.
void | pm_set_all_cksel (unsigned long main_clock_f_hz, unsigned long cpu_f_hz, unsigned long pba_f_hz, unsigned long pbb_f_hz)
| Enable or Disable the division ratio for each clock domain depending on the main source clock frequency and each clock domain target frequency.
long | pm_set_clk_domain_div (pm_clk_domain_t clock_domain, pm_divratio_t divratio)
| Set the division ratio for a clock domain.
long | pm_set_mclk_source (pm_clk_src_t src)
| Set the main clock.
long | pm_wait_for_clk_ready (void)
| Wait actively for the clock settings to be effective.
Module Functions
long | pm_disable_module (unsigned long module)
| Disable the clock of a module.
long | pm_enable_module (unsigned long module)
| Enable the clock of a module.
Reset Functions
__inline__ unsigned long | pm_get_reset_cause (void)
| Returns MCU last reset cause.
Misc Functions
__inline__ unsigned long | pm_get_status (void)
| Get the PM status.
## Sleep Functions
#define | pm_sleep(sleep_mode) {__asm__ __volatile__ ("sleep "STRINGZ(sleep_mode));}
| Sets the MCU in the specified sleep mode.
#define | SLEEP(sleep_mode) pm_sleep(sleep_mode)
| Sets the MCU in the specified sleep mode.
__inline__ void | pm_asyn_wake_up_disable (unsigned long awen_mask)
| Disable one or several asynchronous wake-up sources.
__inline__ void | pm_asyn_wake_up_enable (unsigned long awen_mask)
| Enable one or several asynchronous wake-up source.
__inline__ unsigned long | pm_get_wake_cause (void)
| Returns MCU wake cause.

## Detailed Description

Power Manager(PM) driver interface.

- Compiler: IAR EWAVR32 and GNU GCC for AVR32
- Supported devices: All AVR32 UC3L devices.
- AppNote:

Author:
  Atmel Corporation: http://www.atmel.com
  Support and FAQ: http://support.atmel.no/

Definition in file pm_uc3l.h.

## Define Documentation

#define PM_NOT_SUPPORTED (-10000)

Define "not supported" for the power manager features.

Definition at line 111 of file pm_uc3l.h.

#define PM_POLL_TIMEOUT 100000

The timeguard used for polling (expressed in ticks).

Definition at line 108 of file pm_uc3l.h.

Referenced by pm_wait_for_clk_ready().

#define pm_sleep | ( | sleep_mode |  | ) | {__asm__ __volatile__ ("sleep "STRINGZ(sleep_mode));}

Sets the MCU in the specified sleep mode.

Note:
  Precautions should be taken before entering sleep mode. Refer to the datasheet chapter 'Power Manager'.

Parameters:

  | sleep_mode | The sleep mode index

Definition at line 250 of file pm_uc3l.h.

#define PM_UNLOCK | ( | reg |  | ) | (AVR32_PM.unlock = (unsigned long)(AVR32_PM_UNLOCK_KEY_VALUE << AVR32_PM_UNLOCK_KEY_OFFSET)|(reg))

Unlock PM register macro.

Definition at line 115 of file pm_uc3l.h.

Referenced by pm_config_mainclk_safety(), pm_disable_clk_domain_div(), pm_disable_module(), pm_enable_module(), pm_set_clk_domain_div(), and pm_set_mclk_source().

#define SLEEP | ( | sleep_mode |  | ) | pm_sleep(sleep_mode)

Sets the MCU in the specified sleep mode.

Note:
  Precautions should be taken before entering sleep mode. Refer to the datasheet chapter 'Power Manager'.

Parameters:

  | sleep_mode | The sleep mode index

Definition at line 252 of file pm_uc3l.h.

## Enumeration Type Documentation

enum pm_clk_domain_t

The clock domains of the power manager.

Enumerator:

  PM_CLK_DOMAIN_0 |
  PM_CLK_DOMAIN_1 |
  PM_CLK_DOMAIN_2 |
  PM_CLK_DOMAIN_3 |
  PM_CLK_DOMAIN_INVALID |

Definition at line 72 of file pm_uc3l.h.

    00073 {
    00074   PM_CLK_DOMAIN_0 = AVR32_PM_CLK_GRP_CPU,
    00075   PM_CLK_DOMAIN_1 = AVR32_PM_CLK_GRP_HSB,
    00076   PM_CLK_DOMAIN_2 = AVR32_PM_CLK_GRP_PBA,
    00077   PM_CLK_DOMAIN_3 = AVR32_PM_CLK_GRP_PBB,
    00078   PM_CLK_DOMAIN_INVALID
    00079 } pm_clk_domain_t;

enum pm_clk_src_t

Device-specific data.

The clock sources of the power manager.

Enumerator:

  PM_CLK_SRC_SLOW |
  PM_CLK_SRC_OSC0 |
  PM_CLK_SRC_DFLL0 |
  PM_CLK_SRC_RC120M |
  PM_CLK_SRC_INVALID |

Definition at line 62 of file pm_uc3l.h.

    00063 {
    00064   PM_CLK_SRC_SLOW = AVR32_PM_MCSEL_SLOW,
    00065   PM_CLK_SRC_OSC0 = AVR32_PM_MCSEL_OSC0,
    00066   PM_CLK_SRC_DFLL0 = AVR32_PM_MCSEL_DFLL0,
    00067   PM_CLK_SRC_RC120M = AVR32_PM_MCSEL_RC120M,
    00068   PM_CLK_SRC_INVALID
    00069 } pm_clk_src_t;

enum pm_divratio_max_t

The maximum synchronous clock division ratio for each clock domain.

Enumerator:

  PM_CPUSEL_DIVRATIO_MAX |
  PM_HSBSEL_DIVRATIO_MAX |
  PM_PBASEL_DIVRATIO_MAX |
  PM_PBBSEL_DIVRATIO_MAX |

Definition at line 97 of file pm_uc3l.h.

    00098 {
    00099   PM_CPUSEL_DIVRATIO_MAX = AVR32_PM_CPUSEL_CPUSEL_MASK >> AVR32_PM_CPUSEL_CPUSEL_OFFSET,
    00100   PM_HSBSEL_DIVRATIO_MAX = AVR32_PM_HSBSEL_HSBSEL_MASK >> AVR32_PM_HSBSEL_HSBSEL_OFFSET,
    00101   PM_PBASEL_DIVRATIO_MAX = AVR32_PM_PBASEL_PBSEL_MASK >> AVR32_PM_PBASEL_PBSEL_OFFSET,
    00102   PM_PBBSEL_DIVRATIO_MAX = AVR32_PM_PBBSEL_PBSEL_MASK >> AVR32_PM_PBBSEL_PBSEL_OFFSET
    00103 } pm_divratio_max_t;

enum pm_divratio_t

The possible synchronous clock division ratio.

Enumerator:

  PM_CKSEL_DIVRATIO_2 |
  PM_CKSEL_DIVRATIO_4 |
  PM_CKSEL_DIVRATIO_8 |
  PM_CKSEL_DIVRATIO_16 |
  PM_CKSEL_DIVRATIO_32 |
  PM_CKSEL_DIVRATIO_64 |
  PM_CKSEL_DIVRATIO_128 |
  PM_CKSEL_DIVRATIO_256 |
  PM_CKSEL_DIVRATIO_ERROR |

Definition at line 83 of file pm_uc3l.h.

    00084 {
    00085   PM_CKSEL_DIVRATIO_2 = 0,  // Divide the main clock by 2^1
    00086   PM_CKSEL_DIVRATIO_4,      // Divide the main clock by 2^2
    00087   PM_CKSEL_DIVRATIO_8,      // Divide the main clock by 2^3
    00088   PM_CKSEL_DIVRATIO_16,     // Divide the main clock by 2^4
    00089   PM_CKSEL_DIVRATIO_32,     // Divide the main clock by 2^5
    00090   PM_CKSEL_DIVRATIO_64,     // Divide the main clock by 2^6
    00091   PM_CKSEL_DIVRATIO_128,    // Divide the main clock by 2^7
    00092   PM_CKSEL_DIVRATIO_256,    // Divide the main clock by 2^8
    00093   PM_CKSEL_DIVRATIO_ERROR
    00094 } pm_divratio_t;

## Function Documentation

__inline__ void pm_asyn_wake_up_disable | ( | unsigned long | awen_mask | ) |

Disable one or several asynchronous wake-up sources.

Parameters:

  | awen_mask | Mask of asynchronous wake-up sources (use one of the defines AVR32_PM_AWEN_xxxxWEN_MASK in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/)

Definition at line 290 of file pm_uc3l.h.

    00291 {
    00292   AVR32_PM.awen &= ~awen_mask;
    00293 }

__inline__ void pm_asyn_wake_up_enable | ( | unsigned long | awen_mask | ) |

Enable one or several asynchronous wake-up source.

Parameters:

  | awen_mask | Mask of asynchronous wake-up sources (use one of the defines AVR32_PM_AWEN_xxxxWEN_MASK in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/)

Definition at line 276 of file pm_uc3l.h.

    00277 {
    00278   AVR32_PM.awen |= awen_mask;
    00279 }

__inline__ void pm_clear_interrupt_status | ( | unsigned long | mask | ) |

Clear raised interrupts from the power manager.

Parameters:

  | mask | The interrupts to clear.

Definition at line 381 of file pm_uc3l.h.

    00382 {
    00383   AVR32_PM.icr |= mask;
    00384 }

long pm_config_mainclk_safety | ( | bool | cfd,
|  | bool | ocp,
|  | bool | final |
| ) |  |  |

Configure the main clock safety mechanisms.

Note:
  Refer to the section Clock Failure Detector of the PM chapter in the datasheet

Warning:
  The Critical Path Oscillator (CRIPOSC) must be enabled before enabling the Over Clock Protection mechanism.

Parameters:

  | cfd | Enable/disable the Clock Failure Detection mechanism
  | ocp | Enable/disable the Over Clock Protection mechanism
  | final | If true, make this configuration definitive

Returns:
  Status.

Return values:

  | =0 | Success.
  | <0 | An error occured.

Definition at line 107 of file pm_uc3l.c.

References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, u_avr32_pm_cfdctrl_t::cfdctrl, u_avr32_pm_cfdctrl_t::CFDCTRL, PASS, and PM_UNLOCK.

    00108 {
    00109   u_avr32_pm_cfdctrl_t u_avr32_pm_cfdctrl = {AVR32_PM.cfdctrl};
    00110
    00111   // Check if the CFDCTRL register is read-only.
    00112   if(AVR32_PM.cfdctrl & AVR32_PM_CFDCTRL_SFV_MASK)
    00113     return -1;
    00114
    00115   // Modify
    00116   u_avr32_pm_cfdctrl.CFDCTRL.cfden = cfd;
    00117   u_avr32_pm_cfdctrl.CFDCTRL.ocpen = ocp;
    00118   u_avr32_pm_cfdctrl.CFDCTRL.sfv = final;
    00119   AVR32_ENTER_CRITICAL_REGION( );
    00120   // Unlock the write-protected CFDCTRL register
    00121   PM_UNLOCK(AVR32_PM_CFDCTRL);
    00122   // Write back
    00123   AVR32_PM.cfdctrl = u_avr32_pm_cfdctrl.cfdctrl;
    00124   AVR32_LEAVE_CRITICAL_REGION( );
    00125
    00126   return PASS;
    00127 }

long pm_disable_clk_domain_div | ( | pm_clk_domain_t | clock_domain | ) |

Disable the division ratio for a clock domain.

Parameters:

  | clock_domain | The clock domain to alter.

Warning:
  Care should be taken that each new frequency of the synchronous clocks does not exceed the maximum frequency for each clock domain.

Returns:
  Status.

Return values:

  | =0 | Success.
  | <0 | An error occured.

Definition at line 161 of file pm_uc3l.c.

References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, u_avr32_pm_cpusel_t::cpusel, u_avr32_pm_cpusel_t::CPUSEL, DISABLE, PASS, and PM_UNLOCK.

Referenced by pm_set_all_cksel().

    00162 {
    00163   u_avr32_pm_cpusel_t u_avr32_pm_cpusel = {AVR32_PM.cpusel};
    00164
    00165 //# Implementation note: the CPUSEL and PBASEL and PBBSEL registers all have the
    00166 //# same structure.
    00167
    00168 //# Implementation note: the ckSEL registers are contiguous and memory-mapped in
    00169 //# that order: CPUSEL, HSBSEL, PBASEL, PBBSEL.
    00170
    00171   // ckSEL must not be written while SR.CKRDY is 0.
    00172   while(!(AVR32_PM.sr & AVR32_PM_SR_CKRDY_MASK));
    00173
    00174   // Modify
    00175   u_avr32_pm_cpusel.CPUSEL.cpudiv= DISABLE;
    00176   AVR32_ENTER_CRITICAL_REGION( );
    00177   // Unlock the write-protected ckSEL register
    00178   PM_UNLOCK(AVR32_PM_CPUSEL + clock_domain*sizeof(avr32_pm_cpusel_t));
    00179   // Update
    00180   *(&(AVR32_PM.cpusel) + clock_domain)= u_avr32_pm_cpusel.cpusel;
    00181   AVR32_LEAVE_CRITICAL_REGION( );
    00182
    00183   return PASS;
    00184 }

__inline__ void pm_disable_interrupts | ( | unsigned long | mask | ) |

Disable power manager interrupts.

Parameters:

  | mask | the interrupts to disable.

Definition at line 345 of file pm_uc3l.h.

    00346 {
    00347   AVR32_PM.idr |= mask;
    00348 }

long pm_disable_module | ( | unsigned long | module | ) |

Disable the clock of a module.

Parameters:

  | module | The module to shut down (use one of the defines in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")

Returns:
  Status.

Return values:

  | 0 | Success.
  | <0 | An error occured.

Definition at line 280 of file pm_uc3l.c.

References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, PASS, and PM_UNLOCK.

    00281 {
    00282   unsigned long domain = module>>5;
    00283 //# Implementation note: the ckMASK registers are contiguous and memory-mapped
    00284 //# in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK.
    00285   volatile unsigned long *regptr = (volatile unsigned long*)(&(AVR32_PM.cpumask) + domain);
    00286   unsigned long regvalue;
    00287
    00288
    00289   // Read
    00290   regvalue = *regptr;
    00291   // Modify
    00292   regvalue &= ~(1<<(module%32));
    00293   AVR32_ENTER_CRITICAL_REGION( );
    00294   // Unlock the write-protected ckMASK register
    00295   PM_UNLOCK(AVR32_PM_CPUMASK + domain*sizeof(avr32_pm_cpumask_t));
    00296   // Write
    00297   *regptr = regvalue;
    00298   AVR32_LEAVE_CRITICAL_REGION( );
    00299
    00300   return PASS;
    00301 }

__inline__ void pm_enable_interrupts | ( | unsigned long | mask | ) |

Enable power manager interrupts.

Parameters:

  | mask | the interrupts to enable.

Definition at line 332 of file pm_uc3l.h.

    00333 {
    00334   AVR32_PM.ier |= mask;
    00335 }

long pm_enable_module | ( | unsigned long | module | ) |

Enable the clock of a module.

Parameters:

  | module | The module to clock (use one of the defines in the part-specific header file under "toolchain folder"/avr32/inc(lude)/avr32/; depending on the clock domain, look for the sections "CPU clocks", "HSB clocks", "PBx clocks")

Returns:
  Status.

Return values:

  | 0 | Success.
  | <0 | An error occured.

Definition at line 257 of file pm_uc3l.c.

References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, PASS, and PM_UNLOCK.

    00258 {
    00259   unsigned long domain = module>>5;
    00260 //# Implementation note: the ckMASK registers are contiguous and memory-mapped
    00261 //# in that order: CPUMASK, HSBMASK, PBAMASK, PBBMASK.
    00262   unsigned long *regptr = (unsigned long*)(&(AVR32_PM.cpumask) + domain);
    00263   unsigned long regvalue;
    00264
    00265
    00266   // Read
    00267   regvalue = *regptr;
    00268   // Modify
    00269   regvalue |= (1<<(module%32));
    00270   AVR32_ENTER_CRITICAL_REGION( );
    00271   // Unlock the write-protected ckMASK register
    00272   PM_UNLOCK(AVR32_PM_CPUMASK + domain*sizeof(avr32_pm_cpumask_t));
    00273   // Write
    00274   *regptr = regvalue;
    00275   AVR32_LEAVE_CRITICAL_REGION( );
    00276
    00277   return PASS;
    00278 }

__inline__ unsigned long pm_get_enabled_interrupts | ( | void |  | ) |

Read the enabled power manager interrupts.

Returns:
  mask of the enabled interrupts.

Definition at line 357 of file pm_uc3l.h.

    00358 {
    00359   return(AVR32_PM.imr);
    00360 }

__inline__ unsigned long pm_get_interrupts_status | ( | void |  | ) |

Read the interrupts status of the power manager.

Returns:
  mask of the interrupts that have been triggered.

Definition at line 369 of file pm_uc3l.h.

    00370 {
    00371   return(AVR32_PM.isr);
    00372 }

__inline__ unsigned long pm_get_reset_cause | ( | void |  | ) |

Returns MCU last reset cause.

Returns:
  The MCU last reset cause which can be masked with the `AVR32_PM_RCAUSE_x_MASK` bit-masks to isolate specific causes.

Definition at line 311 of file pm_uc3l.h.

    00312 {
    00313   return AVR32_PM.rcause;
    00314 }

__inline__ unsigned long pm_get_status | ( | void |  | ) |

Get the PM status.

Returns:
  The content of the PM Status register.

Definition at line 401 of file pm_uc3l.h.

    00402 {
    00403   return AVR32_PM.sr;
    00404 }

__inline__ unsigned long pm_get_wake_cause | ( | void |  | ) |

Returns MCU wake cause.

Returns:
  The MCU wake cause which can be masked with the `AVR32_PM_WCAUSE_x_MASK` bit-masks to isolate specific causes.

Definition at line 262 of file pm_uc3l.h.

    00263 {
    00264   return AVR32_PM.wcause;
    00265 }

void pm_set_all_cksel | ( | unsigned long | main_clock_f_hz,
|  | unsigned long | cpu_f_hz,
|  | unsigned long | pba_f_hz,
|  | unsigned long | pbb_f_hz |
| ) |  |  |

Enable or Disable the division ratio for each clock domain depending on the main source clock frequency and each clock domain target frequency.

Parameters:

  | main_clock_f_hz | The main source clock frequency
  | cpu_f_hz | The target CPU clock domain frequency
  | pba_f_hz | The target PBA clock domain frequency
  | pbb_f_hz | The target PBB clock domain frequency

Warning:
  Care should be taken that each new frequency of the synchronous clocks does not exceed the maximum frequency for each clock domain.

Definition at line 186 of file pm_uc3l.c.

References PM_CKSEL_DIVRATIO_ERROR, pm_disable_clk_domain_div(), pm_find_divratio(), and pm_set_clk_domain_div().

Referenced by pcl_configure_synchronous_clocks().

    00188 {
    00189   pm_divratio_t div_ratio;
    00190
    00191
    00192   // Find the divratio to apply to reach the target cpu_f frequency.
    00193   div_ratio = pm_find_divratio(main_clock_f_hz, cpu_f_hz);
    00194   // Apply the division ratio for the CPU clock domain.
    00195   if(PM_CKSEL_DIVRATIO_ERROR == div_ratio)
    00196     pm_disable_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU);
    00197   else
    00198     pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_CPU, div_ratio);
    00199
    00200   // Find the divratio to apply to reach the target pba_f frequency.
    00201   div_ratio = pm_find_divratio(main_clock_f_hz, pba_f_hz);
    00202   // Apply the division ratio for the PBA clock domain.
    00203   if(PM_CKSEL_DIVRATIO_ERROR == div_ratio)
    00204     pm_disable_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA);
    00205   else
    00206     pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBA, div_ratio);
    00207
    00208   // Find the divratio to apply to reach the target pbb_f frequency.
    00209   div_ratio = pm_find_divratio(main_clock_f_hz, pbb_f_hz);
    00210   // Apply the division ratio for the PBB clock domain.
    00211   if(PM_CKSEL_DIVRATIO_ERROR == div_ratio)
    00212     pm_disable_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB);
    00213   else
    00214     pm_set_clk_domain_div((pm_clk_domain_t)AVR32_PM_CLK_GRP_PBB, div_ratio);
    00215 }

long pm_set_clk_domain_div | ( | pm_clk_domain_t | clock_domain,
|  | pm_divratio_t | divratio |
| ) |  |  |

Set the division ratio for a clock domain.

Parameters:

  | clock_domain | The clock domain to alter.
  | divratio | The division ratio to set.

Warning:
  Care should be taken that each new frequency of the synchronous clocks does not exceed the maximum frequency for each clock domain.

Returns:
  Status.

Return values:

  | =0 | Success.
  | <0 | An error occured.

Definition at line 129 of file pm_uc3l.c.

References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, u_avr32_pm_cpusel_t::cpusel, u_avr32_pm_cpusel_t::CPUSEL, PASS, PM_CPUSEL_DIVRATIO_MAX, and PM_UNLOCK.

Referenced by main(), pcl_configure_clocks(), and pm_set_all_cksel().

    00130 {
    00131   u_avr32_pm_cpusel_t u_avr32_pm_cpusel = {AVR32_PM.cpusel};
    00132
    00133 //# Implementation note: the CPUSEL and PBASEL and PBBSEL registers all have the
    00134 //# same structure.
    00135
    00136 //# Implementation note: the ckSEL registers are contiguous and memory-mapped in
    00137 //# that order: CPUSEL, HSBSEL, PBASEL, PBBSEL.
    00138
    00139 #ifdef AVR32SFW_INPUT_CHECK
    00140   // Check the divratio
    00141   if((divratio > PM_CPUSEL_DIVRATIO_MAX)||(divratio < 0))
    00142     return -1;
    00143 #endif
    00144
    00145   // ckSEL must not be written while SR.CKRDY is 0.
    00146   while(!(AVR32_PM.sr & AVR32_PM_SR_CKRDY_MASK));
    00147
    00148   // Modify
    00149   u_avr32_pm_cpusel.CPUSEL.cpudiv= 1;
    00150   u_avr32_pm_cpusel.CPUSEL.cpusel = divratio;
    00151   AVR32_ENTER_CRITICAL_REGION( );
    00152   // Unlock the write-protected ckSEL register
    00153   PM_UNLOCK(AVR32_PM_CPUSEL + clock_domain*sizeof(avr32_pm_cpusel_t));
    00154   // Update
    00155   *(&(AVR32_PM.cpusel) + clock_domain)= u_avr32_pm_cpusel.cpusel;
    00156   AVR32_LEAVE_CRITICAL_REGION( );
    00157
    00158   return PASS;
    00159 }

long pm_set_mclk_source | ( | pm_clk_src_t | src | ) |

Set the main clock.

Parameters:

  | src | The clock to use as the main clock.

Warning:
  The input clock to use as the main clock must be enabled before calling this function, otherwise a deadlock will occur.

Returns:
  Status.

Return values:

  | 0 | Success.
  | <0 | An error occured when trying to set the main clock.

Definition at line 96 of file pm_uc3l.c.

References AVR32_ENTER_CRITICAL_REGION, AVR32_LEAVE_CRITICAL_REGION, PASS, and PM_UNLOCK.

Referenced by main(), pcl_configure_clocks(), pcl_configure_synchronous_clocks(), and pcl_switch_to_osc().

    00097 {
    00098   AVR32_ENTER_CRITICAL_REGION( );
    00099   // Unlock the write-protected MCCTRL register
    00100   PM_UNLOCK(AVR32_PM_MCCTRL);
    00101   AVR32_PM.mcctrl = src;
    00102   AVR32_LEAVE_CRITICAL_REGION( );
    00103
    00104   return PASS;
    00105 }

long pm_wait_for_clk_ready | ( | void |  | ) |

Wait actively for the clock settings to be effective.

Note:
  To avoid an infinite loop, this function checks the clock ready flag PM_POLL_TIMEOUT times.

Returns:
  Status.

Return values:

  | 0 | Success.
  | <0 | Unable to reach a clock ready status within the polling limit.

Definition at line 217 of file pm_uc3l.c.

References PASS, and PM_POLL_TIMEOUT.

    00218 {
    00219   unsigned int timeout = PM_POLL_TIMEOUT;
    00220   while (!(AVR32_PM.sr & AVR32_PM_SR_CKRDY_MASK))
    00221   {
    00222     if(--timeout == 0)
    00223       return -1;
    00224   }
    00225   return PASS;
    00226 }