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# intc.c

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    00001 /*This file is prepared for Doxygen automatic documentation generation.*/
    00017 /* Copyright (c) 2009 Atmel Corporation. All rights reserved.
    00018  *
    00019  * Redistribution and use in source and binary forms, with or without
    00020  * modification, are permitted provided that the following conditions are met:
    00021  *
    00022  * 1. Redistributions of source code must retain the above copyright notice, this
    00023  * list of conditions and the following disclaimer.
    00024  *
    00025  * 2. Redistributions in binary form must reproduce the above copyright notice,
    00026  * this list of conditions and the following disclaimer in the documentation
    00027  * and/or other materials provided with the distribution.
    00028  *
    00029  * 3. The name of Atmel may not be used to endorse or promote products derived
    00030  * from this software without specific prior written permission.
    00031  *
    00032  * 4. This software may only be redistributed and used in connection with an Atmel
    00033  * AVR product.
    00034  *
    00035  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
    00036  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    00037  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
    00038  * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR
    00039  * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
    00040  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
    00041  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
    00042  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    00043  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
    00044  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE
    00045  *
    00046  */
    00047
    00048 #include <avr32/io.h>
    00049 #include "compiler.h"
    00050 #include "preprocessor.h"
    00051 #include "intc.h"
    00052
    00053 // define _evba from exception.S
    00054 extern void _evba;
    00055
    00057 extern const unsigned int ipr_val[AVR32_INTC_NUM_INT_LEVELS];
    00058
    00061 #if (defined __GNUC__)
    00062 #define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
    00063 static volatile __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
    00064 #elif (defined __ICCAVR32__)
    00065 #define DECL_INT_LINE_HANDLER_TABLE(GRP, unused) \
    00066 static volatile __no_init __int_handler _int_line_handler_table_##GRP[Max(AVR32_INTC_NUM_IRQS_PER_GRP##GRP, 1)];
    00067 #endif
    00068 MREPEAT(AVR32_INTC_NUM_INT_GRPS, DECL_INT_LINE_HANDLER_TABLE, ~);
    00069 #undef DECL_INT_LINE_HANDLER_TABLE
    00070
    00073 static const struct
    00074 {
    00075   unsigned int num_irqs;
    00076   volatile __int_handler *_int_line_handler_table;
    00077 } _int_handler_table[AVR32_INTC_NUM_INT_GRPS] =
    00078 {
    00079 #define INSERT_INT_LINE_HANDLER_TABLE(GRP, unused) \
    00080   {AVR32_INTC_NUM_IRQS_PER_GRP##GRP, _int_line_handler_table_##GRP},
    00081   MREPEAT(AVR32_INTC_NUM_INT_GRPS, INSERT_INT_LINE_HANDLER_TABLE, ~)
    00082 #undef INSERT_INT_LINE_HANDLER_TABLE
    00083 };
    00084
    00085
    00090 #if (defined __GNUC__)
    00091 __attribute__((__interrupt__))
    00092 #elif (defined __ICCAVR32__)
    00093 __interrupt
    00094 #endif
    00095 static void _unhandled_interrupt(void)
    00096 {
    00097   // Catch unregistered interrupts.
    00098   while (TRUE);
    00099 }
    00100
    00101
    00111 __int_handler _get_interrupt_handler(unsigned int int_level)
    00112 {
    00113   // ICR3 is mapped first, ICR0 last.
    00114   // Code in exception.S puts int_level in R12 which is used by AVR32-GCC to
    00115   // pass a single argument to a function.
    00116   unsigned int int_grp = AVR32_INTC.icr[AVR32_INTC_INT3 - int_level];
    00117   unsigned int int_req = AVR32_INTC.irr[int_grp];
    00118
    00119   // As an interrupt may disappear while it is being fetched by the CPU
    00120   // (spurious interrupt caused by a delayed response from an MCU peripheral to
    00121   // an interrupt flag clear or interrupt disable instruction), check if there
    00122   // are remaining interrupt lines to process.
    00123   // If a spurious interrupt occurs, the status register (SR) contains an
    00124   // execution mode and interrupt level masks corresponding to a level 0
    00125   // interrupt, whatever the interrupt priority level causing the spurious
    00126   // event. This behavior has been chosen because a spurious interrupt has not
    00127   // to be a priority one and because it may not cause any trouble to other
    00128   // interrupts.
    00129   // However, these spurious interrupts place the hardware in an unstable state
    00130   // and could give problems in other/future versions of the CPU, so the
    00131   // software has to be written so that they never occur. The only safe way of
    00132   // achieving this is to always clear or disable peripheral interrupts with the
    00133   // following sequence:
    00134   // 1: Mask the interrupt in the CPU by setting GM (or IxM) in SR.
    00135   // 2: Perform the bus access to the peripheral register that clears or
    00136   //    disables the interrupt.
    00137   // 3: Wait until the interrupt has actually been cleared or disabled by the
    00138   //    peripheral. This is usually performed by reading from a register in the
    00139   //    same peripheral (it DOES NOT have to be the same register that was
    00140   //    accessed in step 2, but it MUST be in the same peripheral), what takes
    00141   //    bus system latencies into account, but peripheral internal latencies
    00142   //    (generally 0 cycle) also have to be considered.
    00143   // 4: Unmask the interrupt in the CPU by clearing GM (or IxM) in SR.
    00144   // Note that steps 1 and 4 are useless inside interrupt handlers as the
    00145   // corresponding interrupt level is automatically masked by IxM (unless IxM is
    00146   // explicitly cleared by the software).
    00147   //
    00148   // Get the right IRQ handler.
    00149   //
    00150   // If several interrupt lines are active in the group, the interrupt line with
    00151   // the highest number is selected. This is to be coherent with the
    00152   // prioritization of interrupt groups performed by the hardware interrupt
    00153   // controller.
    00154   //
    00155   // If no handler has been registered for the pending interrupt,
    00156   // _unhandled_interrupt will be selected thanks to the initialization of
    00157   // _int_line_handler_table_x by INTC_init_interrupts.
    00158   //
    00159   // exception.S will provide the interrupt handler with a clean interrupt stack
    00160   // frame, with nothing more pushed onto the stack. The interrupt handler must
    00161   // manage the `rete' instruction, what can be done thanks to pure assembly,
    00162   // inline assembly or the `__attribute__((__interrupt__))' C function
    00163   // attribute.
    00164   return (int_req) ? _int_handler_table[int_grp]._int_line_handler_table[32 - clz(int_req) - 1] : NULL;
    00165 }
    00166
    00168 static __inline__ void INTC_init_evba(void)
    00169 {
    00170   Set_system_register(AVR32_EVBA, (int)&_evba );
    00171 }
    00172
    00173 void INTC_init_interrupts(void)
    00174 {
    00175   unsigned int int_grp, int_req;
    00176
    00177   INTC_init_evba();
    00178
    00179   // For all interrupt groups,
    00180   for (int_grp = 0; int_grp < AVR32_INTC_NUM_INT_GRPS; int_grp++)
    00181   {
    00182     // For all interrupt request lines of each group,
    00183     for (int_req = 0; int_req < _int_handler_table[int_grp].num_irqs; int_req++)
    00184     {
    00185       // Assign _unhandled_interrupt as default interrupt handler.
    00186       _int_handler_table[int_grp]._int_line_handler_table[int_req] = &_unhandled_interrupt;
    00187     }
    00188
    00189     // Set the interrupt group priority register to its default value.
    00190     // By default, all interrupt groups are linked to the interrupt priority
    00191     // level 0 and to the interrupt vector _int0.
    00192     AVR32_INTC.ipr[int_grp] = ipr_val[AVR32_INTC_INT0];
    00193   }
    00194 }
    00195
    00196
    00197 void INTC_register_interrupt(__int_handler handler, unsigned int irq, unsigned int int_level)
    00198 {
    00199   // Determine the group of the IRQ.
    00200   unsigned int int_grp = irq / AVR32_INTC_MAX_NUM_IRQS_PER_GRP;
    00201
    00202   // Store in _int_line_handler_table_x the pointer to the interrupt handler, so
    00203   // that _get_interrupt_handler can retrieve it when the interrupt is vectored.
    00204   _int_handler_table[int_grp]._int_line_handler_table[irq % AVR32_INTC_MAX_NUM_IRQS_PER_GRP] = handler;
    00205
    00206   // Program the corresponding IPRX register to set the interrupt priority level
    00207   // and the interrupt vector offset that will be fetched by the core interrupt
    00208   // system.
    00209   // NOTE: The _intx functions are intermediate assembly functions between the
    00210   // core interrupt system and the user interrupt handler.
    00211   AVR32_INTC.ipr[int_grp] = ipr_val[int_level & (AVR32_INTC_IPR_INTLEVEL_MASK >> AVR32_INTC_IPR_INTLEVEL_OFFSET)];
    00212 }