sdram.c File Reference

#include "sdram.h"

Include dependency graph for sdram.c:

Go to the source code of this file.

Defines

#define MODE_AUTOREFRESH   4
#define MODE_EXT_LOAD_MR   5
#define MODE_LOAD_MR   3
#define MODE_NOP   1
#define MODE_NORMAL   0
#define MODE_POWER_DOWN   6
#define MODE_PRECHARGE   2

Functions

static void sdram_delay (int us)
void sdramc_init (const sdram_info *info)


Define Documentation

#define MODE_AUTOREFRESH   4

Definition at line 42 of file sdram.c.

Referenced by mt481c2m32b2tg_init().

#define MODE_EXT_LOAD_MR   5

Definition at line 43 of file sdram.c.

#define MODE_LOAD_MR   3

Definition at line 41 of file sdram.c.

Referenced by mt481c2m32b2tg_init().

#define MODE_NOP   1

Definition at line 39 of file sdram.c.

#define MODE_NORMAL   0

Definition at line 38 of file sdram.c.

Referenced by mt481c2m32b2tg_init().

#define MODE_POWER_DOWN   6

Definition at line 44 of file sdram.c.

#define MODE_PRECHARGE   2

Definition at line 40 of file sdram.c.

Referenced by mt481c2m32b2tg_init().


Function Documentation

static void sdram_delay ( int  us  )  [static]

Definition at line 46 of file sdram.c.

Referenced by sdramc_init().

00047 {
00048   int i, loop_limit;
00049 
00050   loop_limit = us * 20;
00051 
00052   for (i=0; i<loop_limit;i++);
00053 
00054 }

void sdramc_init ( const sdram_info info  ) 

This function will initialize the AVR32 SDRAM Controller

Parameters:
*info The setup and timing variables for the controller
Returns:
Nothing

Definition at line 56 of file sdram.c.

References sdram_info::banks, sdram_info::cas, sdram_info::cols, sdram_info::rows, sdram_delay(), sdram_info::tras, sdram_info::trc, sdram_info::trcd, sdram_info::trp, sdram_info::twr, and sdram_info::txsr.

Referenced by main().

00057 {
00058 
00059   volatile avr32_sdramc_t *hsdramc = &AVR32_SDRAMC;
00060   volatile avr32_hmatrix_t *hmatrix = &AVR32_HMATRIX;
00061   volatile avr32_pio_t *pio = &AVR32_PIOE;
00062 
00063   // Enable SDRAM mode for CS1 in the BAMBI mux 
00064   hmatrix->sfr[4] |= 0x0002;
00065   hmatrix->sfr[4] |= 0x0100;
00066 
00067   // Initialize data bus bits 31-16 (muxed with the LCDC).
00068   pio->asr |= 0x0000FFFF;
00069   pio->pdr |= 0x0000FFFF;
00070   
00071   // Setup SDRAM info
00072   hsdramc->cr = ( (info->cols-8) << AVR32_SDRAMC_CR_NC ) |
00073     ( (info->rows-11) << AVR32_SDRAMC_CR_NR ) |
00074     ( (info->banks-1) << AVR32_SDRAMC_CR_NB ) |
00075     ( info->cas << AVR32_SDRAMC_CR_CAS ) |
00076     ( info->twr << AVR32_SDRAMC_CR_TWR ) |
00077     ( info->trc << AVR32_SDRAMC_CR_TRC ) |
00078     ( info->trp << AVR32_SDRAMC_CR_TRP ) |
00079     ( info->trcd << AVR32_SDRAMC_CR_TRCD ) |
00080     ( info->tras << AVR32_SDRAMC_CR_TRAS ) |
00081     ( info->txsr << AVR32_SDRAMC_CR_TXSR );
00082 
00083   sdram_delay(200);
00084 
00085 }

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Generated on Thu May 10 13:52:44 2007 for AVR32102 - Using the AVR32 SDRAM controller by  doxygen 1.5.1