mt48lc2m32b2tg.h File Reference

#include "sdram.h"

Include dependency graph for mt48lc2m32b2tg.h:

Go to the source code of this file.

Defines
#define	mt481c2m32b2tg_banks   2
#define	mt481c2m32b2tg_cas   3
#define	mt481c2m32b2tg_cols   8
#define	mt481c2m32b2tg_rows   11
#define	mt481c2m32b2tg_tr   (156 * (cpu_hz / 1000) ) / 10000
#define	mt481c2m32b2tg_tras   5
#define	mt481c2m32b2tg_trc   7
#define	mt481c2m32b2tg_trcd   2
#define	mt481c2m32b2tg_trp   2
#define	mt481c2m32b2tg_twr   2
#define	mt481c2m32b2tg_txsr   5
Functions
void	mt481c2m32b2tg_init (const sdram_info *info)

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Define Documentation

#define mt481c2m32b2tg_banks   2

Definition at line 20 of file mt48lc2m32b2tg.h.

#define mt481c2m32b2tg_cas   3

Definition at line 32 of file mt48lc2m32b2tg.h.

#define mt481c2m32b2tg_cols   8

Definition at line 14 of file mt48lc2m32b2tg.h.

#define mt481c2m32b2tg_rows   11

Definition at line 17 of file mt48lc2m32b2tg.h.

#define mt481c2m32b2tg_tr   (156 * (cpu_hz / 1000) ) / 10000

Definition at line 27 of file mt48lc2m32b2tg.h.

#define mt481c2m32b2tg_tras   5

Definition at line 47 of file mt48lc2m32b2tg.h.

#define mt481c2m32b2tg_trc   7

Definition at line 38 of file mt48lc2m32b2tg.h.

#define mt481c2m32b2tg_trcd   2

Definition at line 44 of file mt48lc2m32b2tg.h.

#define mt481c2m32b2tg_trp   2

Definition at line 41 of file mt48lc2m32b2tg.h.

#define mt481c2m32b2tg_twr   2

Definition at line 35 of file mt48lc2m32b2tg.h.

#define mt481c2m32b2tg_txsr   5

Definition at line 50 of file mt48lc2m32b2tg.h.

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Function Documentation

void mt481c2m32b2tg_init

(

const sdram_info *

info

)

This function will initialize the mt481c2m32b2tg sdram.

Parameters:

*info

The mt481c2m32b2tg hardware specific info

Returns:

Nothing

Definition at line 39 of file mt481c2m32b2tg.c.

References MODE_AUTOREFRESH, MODE_LOAD_MR, MODE_NORMAL, MODE_PRECHARGE, mt481c2m32b2tg_tr, and sdram_info::physical_address.

Referenced by main().

{
    volatile unsigned long *sdram = (unsigned long *) info->physical_address;
    unsigned long dummy_read;
    unsigned int i;

    volatile avr32_sdramc_t *sdramc = &AVR32_SDRAMC;

    // Precharge All command is issued to the SDRAM
    sdramc->mr = MODE_PRECHARGE;
    dummy_read = sdramc->mr;
    sdram[0] = 0;

    // Provide eight auto-refresh (CBR) cycles
    sdramc->mr = MODE_AUTOREFRESH;
    dummy_read = sdramc->mr;
    for (i = 0; i < 8; i++)
      {
        sdram[0] = 0;
      }

    // A mode register set (MRS) cycle is issued to program
    // SDRAM parameters, in particular CAS latency and burst
    // length.
    
    // CAS from info struct, burst length 1, serial burst type
    sdramc->mr = MODE_LOAD_MR;
    dummy_read = sdramc->mr;
    sdram[0x020] = 0;

    // A Normal Mode command is provided, 3 clocks after tMRD is met.
    dummy_read = sdramc->mr;
    sdramc->mr = MODE_NORMAL;
    dummy_read = sdramc->mr;
    sdram[0] = 0;

    // Write refresh rate into SDRAMC refresh timer count register
    sdramc->tr =  mt481c2m32b2tg_tr;
}

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