mt481c2m32b2tg.h File Reference

#include "sdram.h"

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Defines
#define	mt481c2m32b2tg_banks   2
#define	mt481c2m32b2tg_cas   3
#define	mt481c2m32b2tg_cols   8
#define	mt481c2m32b2tg_rows   11
#define	mt481c2m32b2tg_tr   312
#define	mt481c2m32b2tg_tras   5
#define	mt481c2m32b2tg_trc   7
#define	mt481c2m32b2tg_trcd   2
#define	mt481c2m32b2tg_trp   2
#define	mt481c2m32b2tg_twr   2
#define	mt481c2m32b2tg_txsr   5
Functions
void	mt481c2m32b2tg_init (const sdram_info *info)

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Define Documentation

#define mt481c2m32b2tg_banks   2

The number of banks for this sdram.

Definition at line 62 of file mt481c2m32b2tg.h.

Referenced by main().

#define mt481c2m32b2tg_cas   3

The CAS latency for this sdram.

Definition at line 81 of file mt481c2m32b2tg.h.

Referenced by main().

#define mt481c2m32b2tg_cols   8

The number of columns for this sdram.

Definition at line 50 of file mt481c2m32b2tg.h.

Referenced by main().

#define mt481c2m32b2tg_rows   11

The number of rows for this sdram.

Definition at line 56 of file mt481c2m32b2tg.h.

Referenced by main().

#define mt481c2m32b2tg_tr   312

The refresh rate. NOTE: This is dependant on the clock frequency

Definition at line 73 of file mt481c2m32b2tg.h.

Referenced by mt481c2m32b2tg_init().

#define mt481c2m32b2tg_tras   5

Minimal ACTIVE to PRECHARGE command. NOTE: This setting is dependant on the clock frequency.

Definition at line 111 of file mt481c2m32b2tg.h.

Referenced by main().

#define mt481c2m32b2tg_trc   7

Minimal ACTIVE to ACTIVE command period. NOTE: This setting is dependant on the clock frequency

Definition at line 94 of file mt481c2m32b2tg.h.

Referenced by main().

#define mt481c2m32b2tg_trcd   2

Minimal ACTIVE to READ or WRITE delay. NOTE: This setting is dependant on the clock frequency

Definition at line 105 of file mt481c2m32b2tg.h.

Referenced by main().

#define mt481c2m32b2tg_trp   2

Minimal PRECHARGE command period. NOTE: This setting is dependant on the clock frequency

Definition at line 100 of file mt481c2m32b2tg.h.

Referenced by main().

#define mt481c2m32b2tg_twr   2

The write recovery time. NOTE: This setting is dependant on the clock frequency

Definition at line 87 of file mt481c2m32b2tg.h.

Referenced by main().

#define mt481c2m32b2tg_txsr   5

Minimal exit SELF REFREASH to ACTIVE command. NOTE: This setting is dependant on the clock frequency

Definition at line 117 of file mt481c2m32b2tg.h.

Referenced by main().

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Function Documentation

void mt481c2m32b2tg_init

(

const sdram_info *

info

)

This function will initialize the mt481c2m32b2tg sdram.

Parameters:

*info

The mt481c2m32b2tg hardware specific info

Returns:

Nothing

Definition at line 39 of file mt481c2m32b2tg.c.

{
    volatile unsigned long *sdram = (unsigned long *) info->physical_address;
    unsigned long dummy_read;
    unsigned int i;

    volatile avr32_sdramc_t *sdramc = &AVR32_SDRAMC;

    // Precharge All command is issued to the SDRAM
    sdramc->mr = MODE_PRECHARGE;
    dummy_read = sdramc->mr;
    sdram[0] = 0;

    // Provide eight auto-refresh (CBR) cycles
    sdramc->mr = MODE_AUTOREFRESH;
    dummy_read = sdramc->mr;
    for (i = 0; i < 8; i++)
      {
        sdram[0] = 0;
      }

    // A mode register set (MRS) cycle is issued to program
    // SDRAM parameters, in particular CAS latency and burst
    // length.
    
    // CAS from info struct, burst length 1, serial burst type
    sdramc->mr = MODE_LOAD_MR;
    dummy_read = sdramc->mr;
    sdram[0x020] = 0;

    // A Normal Mode command is provided, 3 clocks after tMRD is met.
    dummy_read = sdramc->mr;
    sdramc->mr = MODE_NORMAL;
    dummy_read = sdramc->mr;
    sdram[0] = 0;

    // Write refresh rate into SDRAMC refresh timer count register
    sdramc->tr =  mt481c2m32b2tg_tr;
}

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