mt481c2m32b2tg.h

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#ifndef _MT481C2M32B2TG_H_
#define _MT481C2M32B2TG_H_

#include "sdram.h"

/*
These values are device specific. Consult the datasheet for
the given device for more information
*/

// number of cols = 256  ->  8 col bits
#define mt481c2m32b2tg_cols  8

// number of rows = 2048 -> 11 row bits
#define mt481c2m32b2tg_rows  11

// number of banks = 4   ->  2 bank bits
#define mt481c2m32b2tg_banks 2


// Refresh rate
// Use 15.6 uS = 15600 ns.
// With cpu hz 20 MHz = 50 ns clock cycle : 
// Refresh rate = 15600 ns / 50 ns = 312 clock cycles
// Generic formula for chip (156 * (CPU_HZ / 1000) ) / 10000
#define  mt481c2m32b2tg_tr 312


// CAS Latency: 3
// Should be 3 for Speed grade -5 part (up to 200Mhz)
#define mt481c2m32b2tg_cas 3

// Min: 2ck
#define mt481c2m32b2tg_twr 2

// Min 55 ns -> 55 / 50 ~=  2
#define mt481c2m32b2tg_trc 7

// 15 ns -> 15 / 50 ~= 1
#define mt481c2m32b2tg_trp 2

//15 ns -> 15 / 50 ~= 1
#define mt481c2m32b2tg_trcd 2

// 42 ns -> 42 / 50 ~= 1
#define mt481c2m32b2tg_tras 5

// 55 ns -> 55 / 50 ~= 2
#define mt481c2m32b2tg_txsr 5

void mt481c2m32b2tg_init( const sdram_info *info );

#endif

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