mt481c2m32b2tg.c

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/* ***********************************************************************

Copyright (c) 2006, Atmel Corporation All rights reserved.

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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A
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************************************************************************ */

#include "sdram.h"
#include "mt481c2m32b2tg.h"

void mt481c2m32b2tg_init(const sdram_info *info)
{
    volatile unsigned long *sdram = (unsigned long *) info->physical_address;
    unsigned long dummy_read;
    unsigned int i;

    volatile avr32_sdramc_t *sdramc = &AVR32_SDRAMC;

    // Precharge All command is issued to the SDRAM
    sdramc->mr = MODE_PRECHARGE;
    dummy_read = sdramc->mr;
    sdram[0] = 0;

    // Provide eight auto-refresh (CBR) cycles
    sdramc->mr = MODE_AUTOREFRESH;
    dummy_read = sdramc->mr;
    for (i = 0; i < 8; i++)
      {
        sdram[0] = 0;
      }

    // A mode register set (MRS) cycle is issued to program
    // SDRAM parameters, in particular CAS latency and burst
    // length.
    
    // CAS from info struct, burst length 1, serial burst type
    sdramc->mr = MODE_LOAD_MR;
    dummy_read = sdramc->mr;
    sdram[0x020] = 0;

    // A Normal Mode command is provided, 3 clocks after tMRD is met.
    dummy_read = sdramc->mr;
    sdramc->mr = MODE_NORMAL;
    dummy_read = sdramc->mr;
    sdram[0] = 0;

    // Write refresh rate into SDRAMC refresh timer count register
    sdramc->tr =  mt481c2m32b2tg_tr;
}

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