pm.c

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#include "pm.h"

/* reset all clocks and set mclk to osc0 */
int pm_reset( void )
{
        avr32_sm_t *sm = (void *) AVR32_SM_ADDRESS;
        unsigned int status = PM_SUCCESS;
        int disable_clock_mask = 0xFFFFffff;

        pm_set_mclk_source(PM_OSC0);

        sm->pm_cksel = 0x00000000;
        status |= pm_wait_for_lock(AVR32_SM_PM_ISR_CKRDY);

        sm->pm_cpu_mask = disable_clock_mask;
        status |= pm_wait_for_lock(AVR32_SM_PM_ISR_MSKRDY);

        sm->pm_ahb_mask = disable_clock_mask;
        status |= pm_wait_for_lock(AVR32_SM_PM_ISR_MSKRDY);

        sm->pm_apba_mask = disable_clock_mask;
        status |= pm_wait_for_lock(AVR32_SM_PM_ISR_MSKRDY);

        sm->pm_apbb_mask = disable_clock_mask;
        status |= pm_wait_for_lock(AVR32_SM_PM_ISR_MSKRDY);

        sm->pm_ier = 0x7F; /* enable all interrupts*/
        sm->pm_icr |= 0x7F; /* clear all interrupts */

        return status;
}

int pm_wait_for_lock(unsigned int lockbit)
{
        unsigned int timeout = PM_TIMEOUT;
        unsigned int lockStatus=0;

        while (!lockStatus){
                lockStatus =  pm_interrupt_status(lockbit);
                --timeout;
                if (timeout==0)
                        return PM_LOCK_ERROR;
        }

        pm_interrupt_clear(lockbit);

        return PM_SUCCESS;
}

/* Modify a specific pll */
int pm_set_pll(volatile struct pll_opt_t *opt)
{
        volatile avr32_sm_t *sm = (void *) AVR32_SM_ADDRESS;
        unsigned int pllreg, lockbit;

        /* Ensure that mclk is driven by the current pll */
        if(pm_read_mclk_source()==PM_PLL0)
                pm_set_mclk_source(PM_OSC0);

        if ( (opt->multiplier == 0) | (opt->divider == 0) )
                return PM_INVALID_ARGUMENT;

        pllreg = (1<<AVR32_SM_PM_PLL0_PLLCOUNT_OFFSET)|(1<<AVR32_SM_PM_PLL0_PLLEN_OFFSET);

        // add multiplier
        if (opt->multiplier != 0)
        pllreg = pllreg | (((opt->multiplier) -1 ) << AVR32_SM_PLLMUL_OFFSET);
        // add divider
        if(opt->divider != 0)
        pllreg = pllreg | (((opt->divider) - 1) << AVR32_SM_PLLDIV_OFFSET);
        // select oscillator
        if(opt->oscillator <= 1)
        pllreg = pllreg | ((opt->oscillator) << AVR32_SM_PLLOSC_OFFSET);


        /* CHECK FOR VALID ARGUMENTS*/
        if( opt->pll == PM_PLL0 )
                sm->pm_pll0 = pllreg;
        else if ( opt->pll == PM_PLL1 )
                sm->pm_pll1 = pllreg;
        else
                return PM_INVALID_ARGUMENT;

        // Get lock bit
        if(opt->pll == PM_PLL0){
                lockbit =  AVR32_SM_PM_ISR_LOCK0;
        }
        else{
                lockbit =  AVR32_SM_PM_ISR_LOCK1;
        }

        return pm_wait_for_lock(lockbit);
}

int pm_read_pll_frequency( unsigned int pll )
{
        volatile avr32_sm_t *sm = (void *) AVR32_SM_ADDRESS;
        unsigned int mul,div,osc;

        if ( pll==PM_PLL0 ){
                mul = ( (sm->pm_pll0&AVR32_SM_PM_PLL0_PLLMUL_MASK)>>AVR32_SM_PM_PLL0_PLLMUL_OFFSET)+1;
                div = ( (sm->pm_pll0&AVR32_SM_PM_PLL0_PLLDIV_MASK)>>AVR32_SM_PM_PLL0_PLLDIV_OFFSET)+1;
                if((sm->pm_pll0&AVR32_SM_PM_PLL0_PLLOSC_MASK)>>AVR32_SM_PM_PLL0_PLLOSC_OFFSET) /* Oscillator #1 */
                        osc = PM_OSC1_HZ;
                else
                        osc = PM_OSC0_HZ;
        }
        else if ( pll==PM_PLL1 ){
                mul = ( (sm->pm_pll1&AVR32_SM_PM_PLL1_PLLMUL_MASK)>>AVR32_SM_PM_PLL1_PLLMUL_OFFSET)+1;
                div = ( (sm->pm_pll1&AVR32_SM_PM_PLL1_PLLDIV_MASK)>>AVR32_SM_PM_PLL1_PLLDIV_OFFSET)+1;
                if((sm->pm_pll1&AVR32_SM_PM_PLL1_PLLOSC_MASK)>>AVR32_SM_PM_PLL1_PLLOSC_OFFSET) /* Oscillator #1 */
                        osc = PM_OSC1_HZ;
                else
                        osc = PM_OSC0_HZ;
        }
        else
                return PM_INVALID_ARGUMENT;

        return (mul*osc)/div;
}


/*Read a specific oscillator value*/
int pm_read_osc( unsigned int osc )
{
        if(osc == 0)
                return PM_OSC0_HZ;
        else if(osc == 1)
                return PM_OSC1_HZ;
        else
                return PM_INVALID_ARGUMENT;
}

/* Set the source for the main clock */
int pm_set_mclk_source(unsigned int source)
{
        volatile avr32_sm_t *sm = (void *) AVR32_SM_ADDRESS;

        if( (source == PM_OSC0) ){
                sm->pm_mcctrl = (0 << AVR32_SM_PLLSEL_OFFSET);
        }
        else if( source ==PM_PLL0 ){
                sm->pm_mcctrl = (1 << AVR32_SM_PLLSEL_OFFSET);
        }
        else
                return PM_INVALID_ARGUMENT;

        return pm_wait_for_lock(AVR32_SM_PM_ISR_CKRDY);

}



/* Read the main clock src */
int pm_read_mclk_source( void )
{
        int source;
        avr32_sm_t *sm = (void *) AVR32_SM_ADDRESS;

        source = (sm->pm_mcctrl)&AVR32_SM_PLLSEL_MASK;

        if(source==0)
                return PM_OSC0;
        else if(source==AVR32_SM_PLLSEL_MASK)
                return PM_PLL0;
        else
                return PM_INVALID_ARGUMENT;
}



/* Read the main clock frequency*/
int pm_read_mclk( void )
{
        unsigned int f_hz, source;

        /* Get mclk clock source */
        source = pm_read_mclk_source();

        /* check wheter oscillator 0 is used */
        if( source == PM_OSC0 )
                f_hz = PM_OSC0_HZ;
        /* check wheter pll 0 is used */
        else if ( source == PM_PLL0 )
                f_hz = pm_read_pll_frequency(PM_PLL0);
        else
                return PM_INVALID_ARGUMENT;

        return f_hz;
} /* End pm_read_mclk() */



/* Get the clock frequency for the given clock domain */
int pm_read_clock_domain_scaler(unsigned int clock_domain)
{
        static avr32_sm_t *sm = (void *) AVR32_SM_ADDRESS;
        int divider, offset;

        /* Get offset for divider */
        if(clock_domain == PM_APBB_DOMAIN)
                offset = AVR32_SM_PM_CKSEL_APBBSEL_OFFSET;
        else if(clock_domain == PM_APBA_DOMAIN)
                offset = AVR32_SM_PM_CKSEL_APBASEL_OFFSET;
        else if(clock_domain == PM_AHB_DOMAIN)
                offset = AVR32_SM_PM_CKSEL_AHBSEL_OFFSET;
        else if(clock_domain == PM_CPU_DOMAIN)
                offset = AVR32_SM_PM_CKSEL_CPUSEL_OFFSET;
        else
                return PM_INVALID_ARGUMENT;


        divider = sm->pm_cksel & (AVR32_SM_PM_CKSEL_CPUSEL_MASK<<offset);
        divider = divider >> offset;

        return (divider+1);

} /* End pm_read_clock_domain_scaler() */



/* Select clocks for different domains of the system */
int pm_set_clock_domain_scaler(volatile struct clk_sel_opt_t *opt)
{
        volatile avr32_sm_t *sm = (void *) AVR32_SM_ADDRESS;
        int offset,new_settings;

        // Check for invalid division factor
        if( (opt->div_enable == 1) & ((opt->divider == 0)|(opt->divider >= (1<<AVR32_SM_PM_CKSEL_CPUSEL_SIZE))) )
                return PM_INVALID_ARGUMENT;

        // Get offset for bitfields
        switch (opt->clock){
                case PM_APBB_DOMAIN:
                        offset = AVR32_SM_PM_CKSEL_APBBSEL_OFFSET;
                        break;
                case PM_APBA_DOMAIN:
                        offset = AVR32_SM_PM_CKSEL_APBASEL_OFFSET;
                        break;
                case PM_AHB_DOMAIN:
                        offset = AVR32_SM_PM_CKSEL_AHBSEL_OFFSET;
                        break;
                case PM_CPU_DOMAIN:
                        offset = AVR32_SM_PM_CKSEL_CPUSEL_OFFSET;
                        break;
                default:
                        return PM_INVALID_ARGUMENT;
                        break;
        } /* end switch */

        // Check whether division should be disabled
        if(opt->div_enable == 0){
                new_settings = 0x00;
        }

        // Division is to be used
        else if (opt->div_enable == 1) {
                new_settings = 1<<AVR32_SM_PM_CKSEL_CPUDIV;
                new_settings |= ((opt->divider)-1);
        }

        // Error. div_enable >1
        else
                return PM_INVALID_ARGUMENT;

        sm->pm_cksel &=  ~((AVR32_SM_PM_CKSEL_CPUDIV_MASK|AVR32_SM_PM_CKSEL_CPUSEL_MASK)<<offset);
    sm->pm_cksel |= (new_settings<<offset);

        pm_wait_for_lock(AVR32_SM_PM_ISR_CKRDY);

        return PM_SUCCESS;

} /* End pm_set_clock_domain_scaler() */

/* Return the value of the scaling register */
int pm_read_scaling_register(void)
{
        volatile avr32_sm_t *sm = (void *) AVR32_SM_ADDRESS;

        return sm->pm_cksel;
}

/* Start a single module clock part of a clock domain */
int pm_unmask_module_clock( unsigned int clock )
{
        avr32_sm_t *sm = (void *)AVR32_SM_ADDRESS;

        switch (clock % 32){
                case PM_CPU_DOMAIN:
                        /* Check whether the clock is out of bounds */
                        if( (clock/32) > PM_CPU_DOMAIN_SIZE )
                                return PM_INVALID_ARGUMENT;
                        else{
                                sm->pm_cpu_mask |= ( 1<<(clock/32) );
                                break;
                        }
                case PM_AHB_DOMAIN:
                        /* Check whether the clock is out of bounds */
                        if( (clock/32) > PM_AHB_DOMAIN_SIZE )
                                return PM_INVALID_ARGUMENT;
                        else{
                                sm->pm_ahb_mask |= ( 1<<(clock/32) );
                                break;
                        }
                case PM_APBA_DOMAIN:
                        /* Check whether the clock is out of bounds */
                        if( (clock/32) > PM_APBA_DOMAIN_SIZE )
                                return PM_INVALID_ARGUMENT;
                        else{
                                sm->pm_apba_mask |= ( 1<<(clock/32) );
                                break;
                        }
                case PM_APBB_DOMAIN:
                        /* Check whether the clock is out of bounds */
                        if( (clock/32) > PM_APBB_DOMAIN_SIZE )
                                return PM_INVALID_ARGUMENT;
                        else{
                                sm->pm_apbb_mask |= ( 1<<(clock/32) );
                                break;
                        }
                default:
                        return PM_INVALID_ARGUMENT;
        }
        return 0;
} /* End pm_start_clock() */



/* Stop a single module clock part of a clock domain */
int pm_mask_module_clock( unsigned int clock )
{
        avr32_sm_t *sm = (void *)AVR32_SM_ADDRESS;

        switch (clock % 32){
                case PM_CPU_DOMAIN:
                        /* Check whether the clock is out of bounds */
                        if( (clock/32) > PM_CPU_DOMAIN_SIZE )
                                return PM_INVALID_ARGUMENT;
                        else{
                                sm->pm_cpu_mask &= ~( 1<<(clock/32) );
                                break;
                        }
                case PM_AHB_DOMAIN:
                        /* Check whether the clock is out of bounds */
                        if( (clock/32) > PM_AHB_DOMAIN_SIZE )
                                return PM_INVALID_ARGUMENT;
                        else{
                                sm->pm_ahb_mask &= ~( 1<<(clock/32) );
                                break;
                        }
                case PM_APBA_DOMAIN:
                        /* Check whether the clock is out of bounds */
                        if( (clock/32) > PM_APBA_DOMAIN_SIZE )
                                return PM_INVALID_ARGUMENT;
                        else{
                                sm->pm_apba_mask &= ~( 1<<(clock/32) );
                                break;
                        }
                case PM_APBB_DOMAIN:
                        /* Check whether the clock is out of bounds */
                        if( (clock/32) > PM_APBB_DOMAIN_SIZE )
                                return PM_INVALID_ARGUMENT;
                        else{
                                sm->pm_apbb_mask &= ~( 1<<(clock/32) );
                                break;
                        }
                default:
                        return PM_INVALID_ARGUMENT;
        }
        return 0;
} /* End pm_stop_clock */

/* Unmask all module clocks */
void pm_unmask_all_module_clocks ( void )
{
        avr32_sm_t *sm = (void *)AVR32_SM_ADDRESS;

        sm->pm_cpu_mask = 0x00000000;
        sm->pm_ahb_mask = 0x00000000;
        sm->pm_apba_mask = 0x00000000;
        sm->pm_apbb_mask = 0x00000000;
        pm_wait_for_lock(AVR32_SM_PM_ISR_MSKRDY);
}

/* Mask all module clocks */
void pm_mask_all_module_clocks ( void )
{
        avr32_sm_t *sm = (void *)AVR32_SM_ADDRESS;

        sm->pm_cpu_mask = 0xFFFFffff;
        sm->pm_ahb_mask = 0xFFFFffff;
        sm->pm_apba_mask = 0xFFFFffff;
        sm->pm_apbb_mask = 0xFFFFffff;

        pm_wait_for_lock(AVR32_SM_PM_ISR_MSKRDY);
}

int pm_read_module_frequency(int module)
{
        int clk, domain, divider;

        clk = pm_read_mclk();

        divider = pm_read_clock_domain_scaler(PM_AHB_DOMAIN);

        domain = module/32;
        if( domain==PM_APBA_DOMAIN)
                divider = divider * pm_read_clock_domain_scaler(PM_APBA_DOMAIN);
        else if( domain==PM_APBB_DOMAIN)
                divider = divider * pm_read_clock_domain_scaler(PM_APBB_DOMAIN);
        else
                return PM_INVALID_ARGUMENT;

        /* CHECK WHETHER THE CLOCK IS MASKED */

        return clk/divider;
}

/* Enable interrupt */
int pm_interrupt_enable( unsigned int source )
{
        avr32_sm_t *sm = (void *)AVR32_SM_ADDRESS;

        if( source > (PM_INT_SOURCES-1) )
                return PM_INVALID_ARGUMENT;
        else{
                sm->pm_ier |= (1 << source);
                return 0;
        }
}



/* Disable interrupt*/
int pm_interrupt_disable( unsigned int source )
{
        avr32_sm_t *sm = (void *)AVR32_SM_ADDRESS;

        if( source > (PM_INT_SOURCES-1) )
                return PM_INVALID_ARGUMENT;
        else{
                sm->pm_idr |= (1 << source);
                return 0;
        }
}



/* Status of interrupt*/
int pm_interrupt_status( unsigned int source )
{
        avr32_sm_t *sm = (void *)AVR32_SM_ADDRESS;

        if ( source > (PM_INT_SOURCES-1) )
                return PM_INVALID_ARGUMENT;
        else
                return (sm->pm_isr & source)>>source;
}



/* Clear interrupt */
int pm_interrupt_clear( unsigned int source )
{
        avr32_sm_t *sm = (void *)AVR32_SM_ADDRESS;

        if( source > (PM_INT_SOURCES-1) )
                return PM_INVALID_ARGUMENT;
        else{
                sm->pm_icr |= (1 << source);
                return 0;
        }
}



/* Clear interrupt */
int pm_interrupt_mask( unsigned int source )
{
        avr32_sm_t *sm = (void *)AVR32_SM_ADDRESS;

        if( source > (PM_INT_SOURCES-1) )
                return PM_INVALID_ARGUMENT;
        else{
                return (sm->pm_ier & source ) >> source ;
        }
}



/* Modify the generic clock */
int pm_generic_clock_control( struct gen_clk_opt_t *opt)
{
        avr32_sm_t *sm = (void *)AVR32_SM_ADDRESS;

        /* Check whether div-field is larger than 8 bits */
        if( opt->div > 0xFF)
                return PM_INVALID_ARGUMENT;
        /* Check for valid single bits */
        if ( ((opt->diven)|(opt->cen)|(opt->pllsel)|(opt->oscsel)) > 1)
                return PM_INVALID_ARGUMENT;
        else
                sm->pm_gcctrl = (opt->div << AVR32_SM_PM_GCCTRL_DIV_OFFSET)| \
                        (opt->diven << AVR32_SM_PM_GCCTRL_DIVEN_OFFSET)|\
                        (opt->cen << AVR32_SM_PM_GCCTRL_CEN_OFFSET)|\
                        (opt->pllsel << AVR32_SM_PM_GCCTRL_PLLSEL_OFFSET)|\
                        (opt->oscsel << AVR32_SM_PM_GCCTRL_OSCSEL_OFFSET);

        return 0;
} /* End pm_generic_clock_control() */

/* RC errors */
int pm_rc_errors(void)
{
        avr32_sm_t *sm = (void *)AVR32_SM_ADDRESS;
        /* return the bitfield */
        return  sm->rtc_icr;
}

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