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# ctrl_access.h

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    00001 /*This file has been prepared for Doxygen automatic documentation generation.*/
    00016
    00017 /* Copyright (c) 2007, Atmel Corporation All rights reserved.
    00018  *
    00019  * Redistribution and use in source and binary forms, with or without
    00020  * modification, are permitted provided that the following conditions are met:
    00021  *
    00022  * 1. Redistributions of source code must retain the above copyright notice,
    00023  * this list of conditions and the following disclaimer.
    00024  *
    00025  * 2. Redistributions in binary form must reproduce the above copyright notice,
    00026  * this list of conditions and the following disclaimer in the documentation
    00027  * and/or other materials provided with the distribution.
    00028  *
    00029  * 3. The name of ATMEL may not be used to endorse or promote products derived
    00030  * from this software without specific prior written permission.
    00031  *
    00032  * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
    00033  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    00034  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE EXPRESSLY AND
    00035  * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
    00036  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
    00037  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
    00038  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
    00039  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    00040  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
    00041  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    00042  */
    00043
    00044 #ifndef _MEM_CTRL_H_
    00045 #define _MEM_CTRL_H_
    00046
    00047 #include "conf/conf_access.h"
    00048 #include "ctrl_status.h"
    00049
    00050 // Active interface between MEMORIES and RAM (e.g. Embedded File System)
    00051 #ifndef  ACCESS_MEM_TO_RAM
    00052 #  define  ACCESS_MEM_TO_RAM    DISABLE
    00053 #endif
    00054
    00055 // Active the Logical Unit
    00056 #ifndef  LUN_0
    00057 #  define  LUN_0                DISABLE
    00058 #endif
    00059 #ifndef  LUN_1
    00060 #  define  LUN_1                DISABLE
    00061 #endif
    00062 #ifndef  LUN_2
    00063 #  define  LUN_2                DISABLE
    00064 #endif
    00065 #ifndef  LUN_3
    00066 #  define  LUN_3                DISABLE
    00067 #endif
    00068 #ifndef  LUN_4
    00069 #  define  LUN_4                DISABLE
    00070 #endif
    00071 #ifndef  LUN_5
    00072 #  define  LUN_5                DISABLE
    00073 #endif
    00074 #ifndef  LUN_6
    00075 #  define  LUN_6                DISABLE
    00076 #endif
    00077 #ifndef  LUN_7
    00078 #  define  LUN_7                DISABLE
    00079 #endif
    00080 #ifndef  LUN_USB
    00081 #  define  LUN_USB              DISABLE
    00082 #endif
    00083
    00084 // LUN 0 DEFINE
    00085 #define  LUN_ID_VIRTUAL                          LUN_ID_0
    00086 #define  LUN_0_INCLUDE                           "lib_mem\virtual_mem\virtual_mem.h"
    00087 #define  Lun_0_test_unit_ready()                 virtual_test_unit_ready()
    00088 #define  Lun_0_read_capacity(nb_sect)            virtual_read_capacity(nb_sect)
    00089 #define  Lun_0_wr_protect()                      virtual_wr_protect()
    00090 #define  Lun_0_removal()                         virtual_removal()
    00091 #define  Lun_0_read_10(ad, sec)                  virtual_read_10(ad, sec)
    00092 #define  Lun_0_write_10(ad, sec)                 virtual_write_10(ad, sec)
    00093 #define  Lun_0_ram_2_mem(addr , ram)             virtual_ram_2_mem(addr, ram)
    00094 #define  Lun_0_mem_2_ram(addr , ram)             virtual_mem_2_ram(addr, ram)
    00095 #define  LUN_0_NAME                              "VIRTUAL_MEM_ON_CHIP"
    00096
    00097 // LUN 1 DEFINE
    00098 #define  LUN_ID_NF                               LUN_ID_1
    00099 #define  LUN_1_INCLUDE                           "lib_mem\nf\nf_mngt.h"
    00100 #define  Lun_1_test_unit_ready()                 nf_test_unit_ready()
    00101 #define  Lun_1_read_capacity(nb_sect)            nf_read_capacity(nb_sect)
    00102 #define  Lun_1_wr_protect()                      nf_wr_protect()
    00103 #define  Lun_1_removal()                         nf_removal()
    00104 #define  Lun_1_read_10(ad, sec)                  nf_read_10(ad, sec)
    00105 #define  Lun_1_write_10(ad, sec)                 nf_write_10(ad, sec)
    00106 #define  Lun_1_ram_2_mem(addr , ram)             nf_ram_2_nf(addr, ram)
    00107 #define  Lun_1_mem_2_ram(addr , ram)             nf_nf_2_ram(addr, ram)
    00108 #define  LUN_1_NAME                               "\"NAND Flash\""
    00109
    00110 // LUN 2 DEFINE
    00111 #define  LUN_ID_DF                               LUN_ID_2
    00112 #define  LUN_2_INCLUDE                           "lib_mem\df\df_mem.h"
    00113 #define  Lun_2_test_unit_ready()                 df_test_unit_ready()
    00114 #define  Lun_2_read_capacity(nb_sect)            df_read_capacity(nb_sect)
    00115 #define  Lun_2_wr_protect()                      df_wr_protect()
    00116 #define  Lun_2_removal()                         df_removal()
    00117 #define  Lun_2_read_10(ad, sec)                  df_read_10(ad, sec)
    00118 #define  Lun_2_write_10(ad, sec)                 df_write_10(ad, sec)
    00119 #define  Lun_2_ram_2_mem(addr , ram)             df_ram_2_df(addr, ram)
    00120 #define  Lun_2_mem_2_ram(addr , ram)             df_df_2_ram(addr, ram)
    00121 #define  LUN_2_NAME                               "\"On board data flash\""
    00122
    00123 // LUN 3 DEFINE
    00124 #define  LUN_ID_MMC_SD                           LUN_ID_3
    00125 #define  LUN_3_INCLUDE                           "lib_mem\mmc_sd\mmc_sd_mem.h"
    00126 #define  Lun_3_test_unit_ready()                 mmc_sd_test_unit_ready()
    00127 #define  Lun_3_read_capacity(nb_sect)            mmc_sd_read_capacity(nb_sect)
    00128 #define  Lun_3_wr_protect()                      mmc_sd_wr_protect()
    00129 #define  Lun_3_removal()                         mmc_sd_removal()
    00130 #define  Lun_3_read_10(ad, sec)                  mmc_sd_read_10(ad, sec)
    00131 #define  Lun_3_write_10(ad, sec)                 mmc_sd_write_10(ad, sec)
    00132 #define  Lun_3_ram_2_mem(addr , ram)             mmc_ram_2_mmc(addr, ram)
    00133 #define  Lun_3_mem_2_ram(addr , ram)             mmc_mmc_2_ram(addr, ram)
    00134 #define  LUN_3_NAME                               "\"MMC\""
    00135
    00136 // LUN USB DEFINE
    00137 #define  LUN_USB_INCLUDE                           "lib_mem\host_mem\host_mem.h"
    00138 #define  Lun_usb_get_lun()                         host_mem_get_lun()
    00139 #define  Lun_usb_test_unit_ready(lun)              host_mem_test_unit_ready(lun)
    00140 #define  Lun_usb_read_capacity(lun,nb_sect)        host_mem_read_capacity(lun,nb_sect)
    00141 #define  Lun_usb_read_sector_size(lun)             host_mem_read_sector_size(lun)
    00142 #define  Lun_usb_wr_protect(lun)                   host_mem_wr_protect_cache(lun)
    00143 #define  Lun_usb_removal()                         host_mem_removal()
    00144 #define  Lun_usb_ram_2_mem(lun, addr , ram)        host_mem_ram_2_mem(lun,addr,ram)
    00145 #define  Lun_usb_mem_2_ram(lun, addr , ram)        host_mem_mem_2_ram(lun,addr,ram)
    00146 #define  LUN_USB_NAME                              "\"USB Remote memory\""
    00147
    00148
    00149 // FYC: Memory = Logical Unit
    00150 #if (LUN_0 == ENABLE)
    00151    #include    LUN_0_INCLUDE
    00152 #endif
    00153 #if (LUN_1 == ENABLE)
    00154    #include    LUN_1_INCLUDE
    00155 #endif
    00156 #if (LUN_2 == ENABLE)
    00157    #include    LUN_2_INCLUDE
    00158 #endif
    00159 #if (LUN_3 == ENABLE)
    00160    #include    LUN_3_INCLUDE
    00161 #endif
    00162 #if (LUN_4 == ENABLE)
    00163    #include    LUN_4_INCLUDE
    00164 #endif
    00165 #if (LUN_5 == ENABLE)
    00166    #include    LUN_5_INCLUDE
    00167 #endif
    00168 #if (LUN_6 == ENABLE)
    00169    #include    LUN_6_INCLUDE
    00170 #endif
    00171 #if (LUN_7 == ENABLE)
    00172    #include    LUN_7_INCLUDE
    00173 #endif
    00174 #if (LUN_USB == ENABLE)
    00175    #include    LUN_USB_INCLUDE
    00176 #endif
    00177
    00178
    00179 //_____ D E F I N I T I O N S ______________________________________________
    00180
    00181
    00182 //**** Listing of commun interface ****************************************
    00183
    00184 U8             get_nb_lun();
    00185 U8             get_cur_lun();
    00186 Ctrl_status    mem_test_unit_ready( U8 lun );
    00187 Ctrl_status    mem_read_capacity( U8 lun , U32 _MEM_TYPE_SLOW_ *u32_nb_sector );
    00188 U8             mem_sector_size( U8 lun );
    00189 Bool           mem_wr_protect( U8 lun );
    00190 Bool           mem_removal( U8 lun );
    00191 U8 code*       mem_name( U8 lun );
    00192
    00193
    00194 //**** Listing of READ/WRITE interface ************************************
    00195
    00196 //---- Interface for USB ---------------------------------------------------
    00197 Ctrl_status memory_2_usb( U8 lun , U32 addr , U16 nb_sector );
    00198 Ctrl_status usb_2_memory( U8 lun , U32 addr , U16 nb_sector );
    00199
    00200 //---- Interface for RAM to MEM --------------------------------------------
    00201 Ctrl_status    memory_2_ram( U8 lun , const U32 _MEM_TYPE_SLOW_ addr , U8 _MEM_TYPE_SLOW_ *ram );
    00202 Ctrl_status    ram_2_memory( U8 lun , const U32 _MEM_TYPE_SLOW_ addr , U8 _MEM_TYPE_SLOW_ * ram );
    00203
    00204 #define  ID_STREAM_ERR        0xFF
    00205 U8             stream_mem_to_mem( U8 src_lun , U32 src_addr , U8 dest_lun , U32 dest_addr , U16 nb_sector );
    00206 Ctrl_status    stream_state( U8 Id );
    00207 U16            stream_stop( U8 Id );
    00208
    00209 #endif   // _MEM_CTRL_H_
    00210