psc_drv.h File Reference

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Detailed Description

Copyright (c) 2004This file contains the low level macros and definition for the PSC use.

Please read file license.txt for copyright notice.

Version:

1.7 (mc100_bldc_sensorless_0_1_0)

Todo:

Bug:

Definition in file psc_drv.h.

#include "lib_mcu/pll/pll_drv.h"

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Go to the source code of this file.

Data Structures
struct	st_psc_comparison_values
struct	st_psc_fifty_percent_comparison_values
Defines
#define	Clear_psc0_end_of_cycle_interrupt_flag()   (PIFR0 &= ~(1<<PEOP2) )
	Clear PEOP2 bit in PIFR0 register.
#define	Clear_psc0_external_event_a_interrupt_flag()   (PIFR0 &= ~(1<<PEV0A) )
	Clear PEV0A bit in PIFR0 register.
#define	Clear_psc0_external_event_b_interrupt_flag()   (PIFR0 &= ~(1<<PEV0B) )
	Clear PEV0B bit in PIFR0 register.
#define	Clear_psc0_synchro_error_interrupt_flag()   (PIFR0 &= ~(1<<PSEI0) )
	Clear PSEI0 bit in PIFR0 register.
#define	Clear_psc1_end_of_cycle_interrupt_flag()   (PIFR1 &= ~(1<<PEOP1) )
	Clear PEOP1 bit in PIFR1 register.
#define	Clear_psc1_external_event_a_interrupt_flag()   (PIFR1 &= ~(1<<PEV0A) )
	Clear PEV0A bit in PIFR1 register.
#define	Clear_psc1_external_event_b_interrupt_flag()   (PIFR1 &= ~(1<<PEV0B) )
	Clear PEV0B bit in PIFR1 register.
#define	Clear_psc1_synchro_error_interrupt_flag()   (PIFR1 &= ~(1<<PSEI0) )
	Clear PSEI0 bit in PIFR1 register.
#define	Clear_psc2_end_of_cycle_interrupt_flag()   (PIFR2 &= ~(1<<PEOP2) )
	Clear PEOP2 bit in PIFR2 register.
#define	Clear_psc2_external_event_a_interrupt_flag()   (PIFR2 &= ~(1<<PEV0A) )
	Clear PEV0A bit in PIFR2 register.
#define	Clear_psc2_external_event_b_interrupt_flag()   (PIFR2 &= ~(1<<PEV0B) )
	Clear PEV0B bit in PIFR2 register.
#define	Clear_psc2_synchro_error_interrupt_flag()   (PIFR2 &= ~(1<<PSEI0) )
	Clear PSEI0 bit in PIFR2 register.
#define	Disable_both_psc0_outputs()   (PSOC0 &= ~((1<<POEN0A) | (1<<POEN0B)))
	Disable Both PSC0 Waveform Generator A and B.
#define	Disable_both_psc1_outputs()   (PSOC1 &= ~((1<<POEN1A) | (1<<POEN1B)))
	Disable Both PSC1 Waveform Generator A and B.
#define	Disable_both_psc2_outputs()   (PSOC2 &= ~((1<<POEN2A) | (1<<POEN2B)))
	Disable Both PSC2 Waveform Generator A and B.
#define	Disable_psc0_autolock_mode()   (PCNF0 &= ~(1<<PALOCK0) )
	The update will be procced according to PLOCK0 bit.
#define	Disable_psc0_autorun()   (PCTL0 &= ~(1<<PARUN0) )
	No synchronization between PSC2 and PSC0 exists.
#define	Disable_psc0_end_of_cycle_interrupt()   (PIM0 &= ~(1<<PEOPE0) )
	No interrupt is generated when PSC0 reaches the end of the whole cycle.
#define	Disable_psc0_external_event_a_interrupt()   (PIM0 &= ~(1<<PEVE0A) )
	An external event which can generate a capture from retrigger/fault block A doesn't generate any interrupt.
#define	Disable_psc0_external_event_b_interrupt()   (PIM0 &= ~(1<<PEVE0B) )
	An external event which can generate a capture from retrigger/fault block B doesn't generate any interrupt.
#define	Disable_psc0_fifty_percent_mode()   (PCNF0 &= ~(1<<PFIFTY0) )
	OCR0R/SAH/L and OCR0R/SBH/L are fully independant.
#define	Disable_psc0_prescaler()   (PCTL0 &= ~( (1<<PPRE01) | (1<<PPRE00) ) )
	No PSC0prescaler.
#define	Disable_psc0_synchro_error_interrupt()   (PIM0 &= ~(1<<PSEIE0) )
	No interrupt is generated when the PSEI0 bit is set.
#define	Disable_psc1_autolock_mode()   (PCNF1 &= ~(1<<PALOCK1) )
	The update will be procced according to PLOCK1 bit.
#define	Disable_psc1_autorun()   (PCTL1 &= ~(1<<PARUN1) )
	No synchronization between PSC2 and PSC1 exists.
#define	Disable_psc1_end_of_cycle_interrupt()   (PIM1 &= ~(1<<PEVE1A) )
	No interrupt is generated when PSC1 reaches the end of the whole cycle.
#define	Disable_psc1_external_event_a_interrupt()   (PIM1 &= ~(1<<PEVE1A) )
	An external event which can generate a capture from retrigger/fault block A doesn't generate any interrupt.
#define	Disable_psc1_external_event_b_interrupt()   (PIM1 &= ~(1<<PEVE1B) )
	An external event which can generate a capture from retrigger/fault block B doesn't generate any interrupt.
#define	Disable_psc1_fifty_percent_mode()   (PCNF1 &= ~(1<<PFIFTY1) )
	OCR1R/SAH/L and OCR1R/SBH/L are fully independant.
#define	Disable_psc1_prescaler()   (PCTL1 &= ~( (1<<PPRE11) | (1<<PPRE10) ) )
	No PSC1prescaler.
#define	Disable_psc1_synchro_error_interrupt()   (PIM1 &= ~(1<<PSEIE1) )
	No interrupt is generated when the PSEI0 bit is set.
#define	Disable_psc2_autolock_mode()   (PCNF2 &= ~(1<<PALOCK2) )
	The update will be procced according to PLOCK2 bit.
#define	Disable_psc2_autorun()   (PCTL2 &= ~(1<<PARUN2) )
	No synchronization between PSC2 and PSC2 exists.
#define	Disable_psc2_end_of_cycle_interrupt()   (PIM2 &= ~(1<<PEOPE2) )
	No interrupt is generated when PSC2 reaches the end of the whole cycle.
#define	Disable_psc2_external_event_a_interrupt()   (PIM2 &= ~(1<<PEVE2A) )
	An external event which can generate a capture from retrigger/fault block A doesn't generate any interrupt.
#define	Disable_psc2_external_event_b_interrupt()   (PIM2 &= ~(1<<PEVE2B) )
	An external event which can generate a capture from retrigger/fault block B doesn't generate any interrupt.
#define	Disable_psc2_fifty_percent_mode()   (PCNF2 &= ~(1<<PFIFTY2) )
	OCR2R/SAH/L and OCR2R/SBH/L are fully independant.
#define	Disable_psc2_prescaler()   (PCTL2 &= ~( (1<<PPRE21) | (1<<PPRE20) ) )
	No PSC2prescaler.
#define	Disable_psc2_synchro_error_interrupt()   (PIM2 &= ~(1<<PSEIE2) )
	No interrupt is generated when the PSEI0 bit is set.
#define	Disable_pscout00()   (PSOC0 &= ~(1<<POEN0A) )
	Disable PSC0 Waveform Generator A.
#define	Disable_pscout00_fault_mode()   (PCTL0 &= ~(1<<PAOC0A) )
	No fault or retrigger management on PSCOUT00.
#define	Disable_pscout01()   (PSOC0 &= ~(1<<POEN0B) )
	Disable PSC0 Waveform Generator B.
#define	Disable_pscout01_fault_mode()   (PCTL0 &= ~(1<<PAOC0B) )
	No fault or retrigger management on PSCOUT01.
#define	Disable_pscout10()   (PSOC1 &= ~(1<<POEN1A) )
	Disable PSC1 Waveform Generator A.
#define	Disable_pscout10_fault_mode()   (PCTL1 &= ~(1<<PAOC1A) )
	No fault or retrigger management on PSCOUT00.
#define	Disable_pscout11()   (PSOC1 &= ~(1<<POEN1B) )
	Disable PSC1 Waveform Generator B.
#define	Disable_pscout11_fault_mode()   (PCTL1 &= ~(1<<PAOC1B) )
	No fault or retrigger management on PSCOUT01.
#define	Disable_pscout20()   (PSOC2 &= ~(1<<POEN2A) )
	Disable PSC2 Waveform Generator A.
#define	Disable_pscout20_fault_mode()   (PCTL2 &= ~(1<<PAOC2A) )
	No fault or retrigger management on PSCOUT00.
#define	Disable_pscout21()   (PSOC2 &= ~(1<<POEN2B) )
	Disable PSC2 Waveform Generator B.
#define	Disable_pscout21_fault_mode()   (PCTL2 &= ~(1<<PAOC2B) )
	No fault or retrigger management on PSCOUT01.
#define	Divide_psc0_input_clock_by_16()
	PSC0 clock is internally divided by 16.
#define	Divide_psc0_input_clock_by_4()
	PSC0 clock is internally divided by 4.
#define	Divide_psc0_input_clock_by_64()   (PCTL0 |= ((1<<PPRE01) | (1<<PPRE00)) )
	PSC0 clock is internally divided by 64.
#define	Divide_psc1_input_clock_by_16()
	PSC1 clock is internally divided by 16.
#define	Divide_psc1_input_clock_by_4()
	PSC1 clock is internally divided by 4.
#define	Divide_psc1_input_clock_by_64()   (PCTL1 |= ((1<<PPRE11) | (1<<PPRE10)) )
	PSC1 clock is internally divided by 64.
#define	Divide_psc2_input_clock_by_16()
	PSC2 clock is internally divided by 16.
#define	Divide_psc2_input_clock_by_4()
	PSC2 clock is internally divided by 4.
#define	Divide_psc2_input_clock_by_64()   (PCTL2 |= ((1<<PPRE21) | (1<<PPRE20)) )
	PSC2 clock is internally divided by 64.
#define	Enable_both_psc0_outputs()   (PSOC0 |= ((1<<POEN0A) | (1<<POEN0B)))
	Enable Both PSC0 Waveform Generator A and B.
#define	Enable_both_psc1_outputs()   (PSOC1 |= ((1<<POEN1A) | (1<<POEN1B)))
	Enable Both PSC1 Waveform Generator A and B.
#define	Enable_both_psc2_outputs()   (PSOC2 |= ((1<<POEN2A) | (1<<POEN2B)))
	Enable Both PSC2 Waveform Generator A and B.
#define	Enable_psc0_autolock_mode()   (PCNF0 |= (1<<PALOCK0) )
	OCR0R/SAH/L and OCR0R/SBH/L can be written without disturbing the PSC cycle. The update of these registers will be proceed at the end of the PSC cycle if the OCR0RB has been last written.
#define	Enable_psc0_autorun()   (PCTL0 |= (1<<PARUN0) )
	Setting PRUN2 in PCTL2 register or setting both PARUN2 in PCTL2 register and PRUN1 in PCTL1 register will make the two PSC start simultaneously.
#define	Enable_psc0_end_of_cycle_interrupt()   (PIM0 |= (1<<PEOPE0) )
	An interrupt is generated when PSC0 reaches the end of the whole cycle.
#define	Enable_psc0_external_event_a_interrupt()   (PIM0 |= (1<<PEVE0A) )
	An external event which can generate a capture from retrigger/fault block A generates an interrupt.
#define	Enable_psc0_external_event_b_interrupt()   (PIM0 |= (1<<PEVE0B) )
	An external event which can generate a capture from retrigger/fault block B generates an interrupt.
#define	Enable_psc0_fifty_percent_mode()   (PCNF0 |= (1<<PFIFTY0) )
	PSC0 is in 50% mode: Only OCR0RBH/L and OCR0SBH/L are used. They are duplicated in OCR0R/SAH/L during the update of OCR0BH/L.
#define	Enable_psc0_synchro_error_interrupt()   (PIM0 |= (1<<PSEIE0) )
	An interrupt is generated when the PSEI0 bit is set.
#define	Enable_psc1_autolock_mode()   (PCNF1 |= (1<<PALOCK1) )
	OCR1R/SAH/L and OCR1R/SBH/L can be written without disturbing the PSC cycle. The update of these registers will be proceed at the end of the PSC cycle if the OCR1RB has been last written.
#define	Enable_psc1_autorun()   (PCTL1 |= (1<<PARUN1) )
	Setting PRUN0 in PCTL0 register or setting both PARUN0 in PCTL0 register and PRUN2 in PCTL2 register will make the two PSC start simultaneously.
#define	Enable_psc1_end_of_cycle_interrupt()   (PIM1 |= (1<<PEVE1A) )
	An interrupt is generated when PSC1 reaches the end of the whole cycle.
#define	Enable_psc1_external_event_a_interrupt()   (PIM1 |= (1<<PEVE1A) )
	An external event which can generate a capture from retrigger/fault block A generates an interrupt.
#define	Enable_psc1_external_event_b_interrupt()   (PIM1 |= (1<<PEVE1B) )
	An external event which can generate a capture from retrigger/fault block B generates an interrupt.
#define	Enable_psc1_fifty_percent_mode()   (PCNF1 |= (1<<PFIFTY1) )
	PSC1 is in 50% mode: Only OCR1RBH/L and OCR1SBH/L are used. They are duplicated in OCR1R/SAH/L during the update of OCR1BH/L.
#define	Enable_psc1_synchro_error_interrupt()   (PIM1 |= (1<<PSEIE1) )
	An interrupt is generated when the PSEI0 bit is set.
#define	Enable_psc2_autolock_mode()   (PCNF2 |= (1<<PALOCK2) )
	OCR2R/SAH/L and OCR2R/SBH/L can be written without disturbing the PSC cycle. The update of these registers will be proceed at the end of the PSC cycle if the OCR2RB has been last written.
#define	Enable_psc2_autorun()   (PCTL2 |= (1<<PARUN2) )
	Setting PRUN1 in PCTL1 register or setting both PARUN1 in PCTL1 register and PRUN0 in PCTL0 register will make the two PSC start simultaneously.
#define	Enable_psc2_end_of_cycle_interrupt()   (PIM2 |= (1<<PEOPE2) )
	An interrupt is generated when PSC2 reaches the end of the whole cycle.
#define	Enable_psc2_external_event_a_interrupt()   (PIM2 |= (1<<PEVE2A) )
	An external event which can generate a capture from retrigger/fault block A generates an interrupt.
#define	Enable_psc2_external_event_b_interrupt()   (PIM2 |= (1<<PEVE2B) )
	An external event which can generate a capture from retrigger/fault block B generates an interrupt.
#define	Enable_psc2_fifty_percent_mode()   (PCNF2 |= (1<<PFIFTY2) )
	PSC2 is in 50% mode: Only OCR2RBH/L and OCR2SBH/L are used. They are duplicated in OCR2R/SAH/L during the update of OCR2BH/L.
#define	Enable_psc2_synchro_error_interrupt()   (PIM2 |= (1<<PSEIE2) )
	An interrupt is generated when the PSEI0 bit is set.
#define	Enable_pscout00()   (PSOC0 |= (1<<POEN0A) )
	Enable PSC0 Waveform Generator A.
#define	Enable_pscout00_fault_mode()   (PCTL0 |= (1<<PAOC0A) )
	Fault input select to block A can act directly to PSCOUT00 output.
#define	Enable_pscout01()   (PSOC0 |= (1<<POEN0B) )
	Enable PSC0 Waveform Generator B.
#define	Enable_pscout01_fault_mode()   (PCTL0 |= (1<<PAOC0B) )
	Fault input select to block A can act directly to PSCOUT00 output.
#define	Enable_pscout10()   (PSOC1 |= (1<<POEN1A) )
	Enable PSC1 Waveform Generator A.
#define	Enable_pscout10_fault_mode()   (PCTL1 |= (1<<PAOC1A) )
	Fault input select to block A can act directly to PSCOUT00 output.
#define	Enable_pscout11()   (PSOC1 |= (1<<POEN1B) )
	Enable PSC1 Waveform Generator B.
#define	Enable_pscout11_fault_mode()   (PCTL1 |= (1<<PAOC1B) )
	Fault input select to block A can act directly to PSCOUT00 output.
#define	Enable_pscout20()   (PSOC2 |= (1<<POEN2A) )
	Enable PSC2 Waveform Generator A.
#define	Enable_pscout20_fault_mode()   (PCTL2 |= (1<<PAOC2A) )
	Fault input select to block A can act directly to PSCOUT00 output.
#define	Enable_pscout21()   (PSOC2 |= (1<<POEN2B) )
	Enable PSC2 Waveform Generator B.
#define	Enable_pscout21_fault_mode()   (PCTL2 |= (1<<PAOC2B) )
	Fault input select to block A can act directly to PSCOUT00 output.
#define	Init_psc0_all_compare_values(PSC0_DEADTIME0, PSC0_ONTIME0, PSC0_DEADTIME1, PSC0_ONTIME1)
	Init all PSC0 comparison values.
#define	Init_psc0_fifty_percent_compare_values(PSC0_DEADTIME1, PSC0_ONTIME1)
	Init PSC0 fifty percent comparison values (usefull for 50% mode).
#define	Init_psc1_all_compare_values(PSC1_DEADTIME0, PSC1_ONTIME0, PSC1_DEADTIME1, PSC1_ONTIME1)
	Init all PSC1 comparison values.
#define	Init_psc1_fifty_percent_compare_values(PSC1_DEADTIME1, PSC1_ONTIME1)
	Init PSC1 fifty percent comparison values (usefull for 50% mode).
#define	Init_psc2_all_compare_values(PSC2_DEADTIME0, PSC2_ONTIME0, PSC2_DEADTIME1, PSC2_ONTIME1)
	Init all PSC2 comparison values.
#define	Init_psc2_fifty_percent_compare_values(PSC2_DEADTIME1, PSC2_ONTIME1)
	Init PSC2 fifty percent comparison values (usefull for 50% mode).
#define	Is_psc0_end_of_cycle_interrupt_flag_set()   (PIFR0 & (1<<PEOP2) )
	Return 1 if the PE0P2 bit in PIFR0 is set.
#define	Is_psc0_external_event_a_interrupt_flag_set()   (PIFR0 & (1<<PEV0A) )
	Return 1 if the PEV0A bit in PIFR0 is set.
#define	Is_psc0_external_event_b_interrupt_flag_set()   (PIFR0 & (1<<PEV0B) )
	Return 1 if the PEV0B bit in PIFR0 is set.
#define	Is_psc0_started()   (PCTL0 & (1<<PRUN0) )
#define	Is_psc0_synchro_error_interrupt_flag_set()   (PIFR0 & (1<<PSEI0) )
	Return 1 if the PSEI0 bit in PIFR0 is set.
#define	Is_psc1_end_of_cycle_interrupt_flag_set()   (PIFR1 & (1<<PEOP1) )
	Return 1 if the PEOP1 bit in PIFR1 is set.
#define	Is_psc1_external_event_a_interrupt_flag_set()   (PIFR1 & (1<<PEV0A) )
	Return 1 if the PEV0A bit in PIFR1 is set.
#define	Is_psc1_external_event_b_interrupt_flag_set()   (PIFR1 & (1<<PEV0B) )
	Return 1 if the PEV0B bit in PIFR1 is set.
#define	Is_psc1_started()   (PCTL1 & (1<<PRUN1) )
#define	Is_psc1_synchro_error_interrupt_flag_set()   (PIFR1 & (1<<PSEI0) )
	Return 1 if the PSEI0 bit in PIFR1 is set.
#define	Is_psc2_end_of_cycle_interrupt_flag_set()   (PIFR2 & (1<<PEOP2) )
	Return 1 if the PE2P2 bit in PIFR2 is set.
#define	Is_psc2_external_event_a_interrupt_flag_set()   (PIFR2 & (1<<PEV0A) )
	Return 1 if the PEV0A bit in PIFR2 is set.
#define	Is_psc2_external_event_b_interrupt_flag_set()   (PIFR2 & (1<<PEV0B) )
	Return 1 if the PEV0B bit in PIFR2 is set.
#define	Is_psc2_started()   (PCTL2 & (1<<PRUN2) )
#define	Is_psc2_synchro_error_interrupt_flag_set()   (PIFR2 & (1<<PSEI0) )
	Return 1 if the PSEI0 bit in PIFR2 is set.
#define	Lock_psc0_compare_values()   (PCNF0 |= (1<<PLOCK0) )
	Take care that the lock is active only if you have disabled the autolock mode.
#define	Lock_psc1_compare_values()   (PCNF1 |= (1<<PLOCK1) )
	Take care that the lock is active only if you have disabled the autolock mode.
#define	Lock_psc2_compare_values()   (PCNF2 |= (1<<PLOCK2) )
	Take care that the lock is active only if you have disabled the autolock mode.
#define	Psc0_complete_waveform_and_stop()
	Turn Off PSC0 and the end of cycle.
#define	Psc0_end_of_cycle_flank_width_modulation()   (PCTL0 &= ~(1<<PBFM0) )
	PSC0 Flank width modulation operates only on OCR0RB.
#define	Psc0_in_1_ramp_mode()   (PCNF0 &= ~( (1<<PMODE01) | (1<<PMODE00) ) )
#define	Psc0_in_2_ramps_mode()
	PSC0 is configured in two ramp mode, it means that the internal counter counts from 0 up to OCR0RA then from 0 to OCR0RB.
#define	Psc0_in_4_ramps_mode()
	PSC0 is configured in for ramp mode, it means that the internal counter counts from 0 up to OCR0SA then from 0 to OCR0RA then from 0 to OCR0SB then from 0 to OCR0RB.
#define	Psc0_in_centered_aligned_mode()   (PCNF0 |= ( (1<<PMODE01) | (1<<PMODE00) ) )
	PSC0 is configured in for ramp mode, it means that the internal counter counts from 0 up to OCR0RB then from OCR0RB downto 0.
#define	Psc0_outputs_active_high()   (PCNF0 |= (1<<POP0) )
	PSC0 outputs are active low.
#define	Psc0_outputs_active_low()   (PCNF0 &= ~(1<<POP0) )
	PSC0 outputs are active high.
#define	Psc0_symetrical_flank_width_modulation()   (PCTL0 |= (1<<PBFM0) )
	PSC0 Flank width modulation operates on both OCR0RA and OCR0RB.
#define	Psc0_synchro_on_waveform_generator_a_leading_edge()   (PSCO0 &= ~( (1<<PSYNC01) | (1<<PSYNC00) ) )
	The PSC0 synchronization signal is sent to the ADC/Amplifier on waveform generator A leading edge.
#define	Psc0_synchro_on_waveform_generator_a_trailing_edge()
	The PSC0 synchronization signal is sent to the ADC/Amplifier on waveform generator A trailing edge.
#define	Psc0_synchro_on_waveform_generator_b_leading_edge()
	The PSC0 synchronization signal is sent to the ADC/Amplifier on waveform generator B leading edge.
#define	Psc0_synchro_on_waveform_generator_b_trailing_edge()   (PSCO0 |= ( (1<<PSYNC01) | (1<<PSYNC00) ) )
	The PSC0 synchronization signal is sent to the ADC/Amplifier on waveform generator B trailing edge.
#define	Psc0_use_32_mega_pll_clock()
	Start the PLL at 32MHz and connect it to PSC0.
#define	Psc0_use_64_mega_pll_clock()
	Start the PLL at 64MHz and connect it to PSC0.
#define	Psc0_use_io_clock()   (PCNF0 &= ~(1<<PCLKSEL0) )
	Connect the PSC0 input clock to the I/O clock.
#define	Psc0_use_pll_clock()   (PCNF0 |= (1<<PCLKSEL0) )
	Connect the PSC0 input clock to the PLL.
#define	Psc1_complete_waveform_and_stop()
	Turn Off PSC1 and the end of cycle.
#define	Psc1_end_of_cycle_flank_width_modulation()   (PCTL1 &= ~(1<<PBFM1) )
	PSC1 Flank width modulation operates only on OCR1RB.
#define	Psc1_in_1_ramp_mode()   (PCNF1 &= ~( (1<<PMODE11) | (1<<PMODE10) ) )
#define	Psc1_in_2_ramps_mode()
	PSC1 is configured in two ramp mode, it means that the internal counter counts from 0 up to OCR1RA then from 0 to OCR1RB.
#define	Psc1_in_4_ramps_mode()
	PSC1 is configured in for ramp mode, it means that the internal counter counts from 0 up to OCR1SA then from 0 to OCR1RA then from 0 to OCR1SB then from 0 to OCR1RB.
#define	Psc1_in_centered_aligned_mode()   (PCNF1 |= ( (1<<PMODE11) | (1<<PMODE10) ) )
	PSC1 is configured in for ramp mode, it means that the internal counter counts from 0 up to OCR1RB then from OCR1RB downto 0.
#define	Psc1_outputs_active_high()   (PCNF1 |= (1<<POP1) )
	PSC1 outputs are active low.
#define	Psc1_outputs_active_low()   (PCNF1 &= ~(1<<POP1) )
	PSC1 outputs are active high.
#define	Psc1_symetrical_flank_width_modulation()   (PCTL1 |= (1<<PBFM1) )
	PSC1 Flank width modulation operates on both OCR1RA and OCR1RB.
#define	Psc1_synchro_on_waveform_generator_a_leading_edge()   (PSCO1 &= ~( (1<<PSYNC11) | (1<<PSYNC10) ) )
	The PSC1 synchronization signal is sent to the ADC/Amplifier on waveform generator A leading edge.
#define	Psc1_synchro_on_waveform_generator_a_trailing_edge()
	The PSC1 synchronization signal is sent to the ADC/Amplifier on waveform generator A trailing edge.
#define	Psc1_synchro_on_waveform_generator_b_leading_edge()
	The PSC1 synchronization signal is sent to the ADC/Amplifier on waveform generator B leading edge.
#define	Psc1_synchro_on_waveform_generator_b_trailing_edge()   (PSCO1 |= ( (1<<PSYNC11) | (1<<PSYNC10) ) )
	The PSC1 synchronization signal is sent to the ADC/Amplifier on waveform generator B trailing edge.
#define	Psc1_use_32_mega_pll_clock()
	Start the PLL at 32MHz and connect it to PSC1.
#define	Psc1_use_64_mega_pll_clock()
	Start the PLL at 64MHz and connect it to PSC1.
#define	Psc1_use_io_clock()   (PCNF1 &= ~(1<<PCLKSEL0) )
	Connect the PSC1 input clock to the I/O clock.
#define	Psc1_use_pll_clock()   (PCNF1 |= (1<<PCLKSEL0) )
	Connect the PSC1 input clock to the PLL.
#define	Psc2_complete_waveform_and_stop()
	Turn Off PSC2 and the end of cycle.
#define	Psc2_end_of_cycle_flank_width_modulation()   (PCTL2 &= ~(1<<PBFM2) )
	PSC2 Flank width modulation operates only on OCR2RB.
#define	Psc2_in_1_ramp_mode()   (PCNF2 &= ~( (1<<PMODE21) | (1<<PMODE20) ) )
#define	Psc2_in_2_ramps_mode()
	PSC2 is configured in two ramp mode, it means that the internal counter counts from 0 up to OCR2RA then from 0 to OCR2RB.
#define	Psc2_in_4_ramps_mode()
	PSC2 is configured in for ramp mode, it means that the internal counter counts from 0 up to OCR2SA then from 0 to OCR2RA then from 0 to OCR2SB then from 0 to OCR2RB.
#define	Psc2_in_centered_aligned_mode()   (PCNF2 |= ( (1<<PMODE21) | (1<<PMODE20) ) )
	PSC2 is configured in for ramp mode, it means that the internal counter counts from 0 up to OCR2RB then from OCR2RB downto 0.
#define	Psc2_outputs_active_high()   (PCNF2 |= (1<<POP2) )
	PSC2 outputs are active low.
#define	Psc2_outputs_active_low()   (PCNF2 &= ~(1<<POP2) )
	PSC2 outputs are active high.
#define	Psc2_symetrical_flank_width_modulation()   (PCTL2 |= (1<<PBFM2) )
	PSC2 Flank width modulation operates on both OCR2RA and OCR2RB.
#define	Psc2_synchro_on_waveform_generator_a_leading_edge()   (PSCO2 &= ~( (1<<PSYNC21) | (1<<PSYNC20) ) )
	The PSC2 synchronization signal is sent to the ADC/Amplifier on waveform generator A leading edge.
#define	Psc2_synchro_on_waveform_generator_a_trailing_edge()
	The PSC2 synchronization signal is sent to the ADC/Amplifier on waveform generator A trailing edge.
#define	Psc2_synchro_on_waveform_generator_b_leading_edge()
	The PSC2 synchronization signal is sent to the ADC/Amplifier on waveform generator B leading edge.
#define	Psc2_synchro_on_waveform_generator_b_trailing_edge()   (PSCO2 |= ( (1<<PSYNC21) | (1<<PSYNC20) ) )
	The PSC2 synchronization signal is sent to the ADC/Amplifier on waveform generator B trailing edge.
#define	Psc2_use_32_mega_pll_clock()
	Start the PLL at 32MHz and connect it to PSC2.
#define	Psc2_use_64_mega_pll_clock()
	Start the PLL at 64MHz and connect it to PSC2.
#define	Psc2_use_io_clock()   (PCNF2 &= ~(1<<PCLKSEL0) )
	Connect the PSC2 input clock to the I/O clock.
#define	Psc2_use_pll_clock()   (PCNF2 |= (1<<PCLKSEL0) )
	Connect the PSC2 input clock to the PLL.
#define	Start_psc0()   (PCTL0 |= (1<<PRUN0) )
	Turn On PSC0.
#define	Start_psc1()   (PCTL1 |= (1<<PRUN1) )
	Turn On PSC1.
#define	Start_psc2()   (PCTL2 |= (1<<PRUN2) )
	Turn On PSC2.
#define	Stop_psc0()   (PCTL0 &= ~(1<<PRUN0) )
	Turn Off PSC0.
#define	Stop_psc1()   (PCTL1 &= ~(1<<PRUN1) )
	Turn Off PSC1.
#define	Stop_psc2()   (PCTL2 &= ~(1<<PRUN2) )
	Turn Off PSC2.
#define	Update_psc0_compare_values()   (PCNF0 &= ~(1<<PLOCK0) )
	The compare registers will be updated with the content of OCR0ARH/L and OCR0BRH.
#define	Update_psc1_compare_values()   (PCNF1 &= ~(1<<PLOCK1) )
	The compare registers will be updated with the content of OCR1AH/L and OCR1BH.
#define	Update_psc2_compare_values()   (PCNF2 &= ~(1<<PLOCK2) )
	The compare registers will be updated with the content of OCR2AH/L and OCR2BH.
Typedefs
typedef st_psc_comparison_values	Psc_comparison_values
typedef st_psc_fifty_percent_comparison_values	Psc_fifty_percent_comparison_values
Functions
void	init_psc0 (void)
	Configures the PSC0 accordingly to the PSC0 Define Configuration values, Then Init the PSC0 comparison values and start it.
void	init_psc1 (void)
	Configures the PSC1 accordingly to the PSC1 Define Configuration values, Then Init the PSC1 comparison values and start it.
void	init_psc2 (void)
	Configures the PSC2 accordingly to the PSC2 Define Configuration values, Then Init the PSC2 comparison values and start it.
void	update_psc0 (Psc_comparison_values *psc0_comparison_values)
	Update all the PSC0 comparison values accordingly to the four values passed as U16 parameters.
void	update_psc0_fifty (Psc_fifty_percent_comparison_values *psc0_fifty_percent_comparison_values)
	Update half the PSC0 comparison values accordingly to the two values passed as U16 parameters.
void	update_psc1 (Psc_comparison_values *psc1_comparison_values)
	Update all the PSC1 comparison values accordingly to the four values passed as U16 parameters.
void	update_psc1_fifty (Psc_fifty_percent_comparison_values *psc1_fifty_percent_comparison_values)
	Update half the PSC1 comparison values accordingly to the two values passed as U16 parameters.
void	update_psc2 (Psc_comparison_values *psc2_comparison_values)
	Update all the PSC2 comparison values accordingly to the four values passed as U16 parameters.
void	update_psc2_fifty (Psc_fifty_percent_comparison_values *psc2_fifty_percent_comparison_values)
	Update half the PSC2 comparison values accordingly to the two values passed as U16 parameters.

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