00001
00002
00003
00004
00005
00006
00007
00008
00009
00010
00011
00012
00013
00014 #ifndef PSC_DRV_H
00015 #define PSC_DRV_H
00016
00017
00018 #include "lib_mcu/pll/pll_drv.h"
00019
00023
00024
00025
00029
00033 #define Enable_pscout00() (PSOC0 |= (1<<POEN0A) )
00034 #define Disable_pscout00() (PSOC0 &= ~(1<<POEN0A) )
00035
00036 #define Enable_pscout01() (PSOC0 |= (1<<POEN0B) )
00037 #define Disable_pscout01() (PSOC0 &= ~(1<<POEN0B) )
00038
00039 #define Enable_both_psc0_outputs() \
00040 (PSOC0 |= ((1<<POEN0A) | (1<<POEN0B)))
00042 #define Disable_both_psc0_outputs() \
00043 (PSOC0 &= ~((1<<POEN0A) | (1<<POEN0B)))
00044
00045 #define Psc0_outputs_active_high() (PCNF0 |= (1<<POP0) )
00046 #define Psc0_outputs_active_low() (PCNF0 &= ~(1<<POP0) )
00047
00048
00052 #define Enable_psc0_fifty_percent_mode() (PCNF0 |= (1<<PFIFTY0) )
00053 #define Disable_psc0_fifty_percent_mode() (PCNF0 &= ~(1<<PFIFTY0) )
00054
00055 #define Enable_psc0_autolock_mode() (PCNF0 |= (1<<PALOCK0) )
00056 #define Disable_psc0_autolock_mode() (PCNF0 &= ~(1<<PALOCK0) )
00057
00058 #define Lock_psc0_compare_values() (PCNF0 |= (1<<PLOCK0) )
00059 #define Update_psc0_compare_values() (PCNF0 &= ~(1<<PLOCK0) )
00060
00061
00065
00070 #define Psc0_use_pll_clock() (PCNF0 |= (1<<PCLKSEL0) )
00072 #define Psc0_use_io_clock() (PCNF0 &= ~(1<<PCLKSEL0) )
00074 #define Psc0_use_64_mega_pll_clock() \
00075 (Start_pll_64_mega(), \
00076 Wait_pll_ready(), \
00077 Psc0_use_pll_clock() )
00079 #define Psc0_use_32_mega_pll_clock() \
00080 (Start_pll_32_mega(), \
00081 Wait_pll_ready(), \
00082 Psc0_use_pll_clock() )
00084
00089 #define Disable_psc0_prescaler() \
00090 (PCTL0 &= ~( (1<<PPRE01) | (1<<PPRE00) ) )
00092 #define Divide_psc0_input_clock_by_4() \
00093 (PCTL0 &= ~(1<<PPRE01), \
00094 PCTL0 |= (1<<PPRE00) )
00096 #define Divide_psc0_input_clock_by_16() \
00097 (PCTL0 |= (1<<PPRE01), \
00098 PCTL0 &= ~(1<<PPRE00) )
00100 #define Divide_psc0_input_clock_by_64() \
00101 (PCTL0 |= ((1<<PPRE01) | (1<<PPRE00)) )
00103
00105
00111 #define Psc0_in_1_ramp_mode() \
00112 (PCNF0 &= ~( (1<<PMODE01) | (1<<PMODE00) ) )
00115 #define Psc0_in_2_ramps_mode() \
00116 (PCNF0 &= ~(1<<PMODE01), \
00117 PCNF0 |= (1<<PMODE00) )
00120 #define Psc0_in_4_ramps_mode() \
00121 (PCNF0 |= (1<<PMODE01), \
00122 PCNF0 &= ~(1<<PMODE00) )
00125 #define Psc0_in_centered_aligned_mode() \
00126 (PCNF0 |= ( (1<<PMODE01) | (1<<PMODE00) ) )
00128
00132 #define Psc0_symetrical_flank_width_modulation() (PCTL0 |= (1<<PBFM0) )
00133 #define Psc0_end_of_cycle_flank_width_modulation() (PCTL0 &= ~(1<<PBFM0) )
00134
00135
00140 #define Psc0_synchro_on_waveform_generator_a_leading_edge() \
00141 (PSCO0 &= ~( (1<<PSYNC01) | (1<<PSYNC00) ) )
00143 #define Psc0_synchro_on_waveform_generator_a_trailing_edge() \
00144 (PSCO0 &= ~(1<<PSYNC01), \
00145 PSCO0 |= (1<<PSYNC00) )
00147 #define Psc0_synchro_on_waveform_generator_b_leading_edge() \
00148 (PSCO0 |= (1<<PSYNC01), \
00149 PSCO0 &= ~(1<<PSYNC00) )
00151 #define Psc0_synchro_on_waveform_generator_b_trailing_edge() \
00152 (PSCO0 |= ( (1<<PSYNC01) | (1<<PSYNC00) ) )
00154
00158 #define Start_psc0() (PCTL0 |= (1<<PRUN0) )
00159 #define Stop_psc0() (PCTL0 &= ~(1<<PRUN0) )
00160
00161 #define Psc0_complete_waveform_and_stop() (PCTL0 |= (1<<PCCYC0), \
00162 PCTL0 &= ~(1<<PRUN0) )
00163 #define Is_psc0_started() (PCTL0 & (1<<PRUN0) )
00165
00169 #define Enable_pscout00_fault_mode() (PCTL0 |= (1<<PAOC0A) )
00170 #define Disable_pscout00_fault_mode() (PCTL0 &= ~(1<<PAOC0A) )
00171
00172 #define Enable_pscout01_fault_mode() (PCTL0 |= (1<<PAOC0B) )
00173 #define Disable_pscout01_fault_mode() (PCTL0 &= ~(1<<PAOC0B) )
00174
00175 #define Enable_psc0_autorun() (PCTL0 |= (1<<PARUN0) )
00176 #define Disable_psc0_autorun() (PCTL0 &= ~(1<<PARUN0) )
00177
00178
00182 #define Enable_psc0_synchro_error_interrupt() (PIM0 |= (1<<PSEIE0) )
00183 #define Disable_psc0_synchro_error_interrupt() (PIM0 &= ~(1<<PSEIE0) )
00184
00185 #define Enable_psc0_external_event_a_interrupt() (PIM0 |= (1<<PEVE0A) )
00186 #define Disable_psc0_external_event_a_interrupt() (PIM0 &= ~(1<<PEVE0A) )
00187
00188 #define Enable_psc0_external_event_b_interrupt() (PIM0 |= (1<<PEVE0B) )
00189 #define Disable_psc0_external_event_b_interrupt() (PIM0 &= ~(1<<PEVE0B) )
00190
00191 #define Enable_psc0_end_of_cycle_interrupt() (PIM0 |= (1<<PEOPE0) )
00192 #define Disable_psc0_end_of_cycle_interrupt() (PIM0 &= ~(1<<PEOPE0) )
00193
00194
00198 #define Is_psc0_synchro_error_interrupt_flag_set() (PIFR0 & (1<<PSEI0) )
00199 #define Clear_psc0_synchro_error_interrupt_flag() (PIFR0 &= ~(1<<PSEI0) )
00200
00201 #define Is_psc0_external_event_a_interrupt_flag_set() (PIFR0 & (1<<PEV0A) )
00202 #define Clear_psc0_external_event_a_interrupt_flag() (PIFR0 &= ~(1<<PEV0A) )
00203
00204 #define Is_psc0_external_event_b_interrupt_flag_set() (PIFR0 & (1<<PEV0B) )
00205 #define Clear_psc0_external_event_b_interrupt_flag() (PIFR0 &= ~(1<<PEV0B) )
00206
00207 #define Is_psc0_end_of_cycle_interrupt_flag_set() (PIFR0 & (1<<PEOP2) )
00208 #define Clear_psc0_end_of_cycle_interrupt_flag() (PIFR0 &= ~(1<<PEOP2) )
00209
00210
00215 #define Init_psc0_all_compare_values(PSC0_DEADTIME0, PSC0_ONTIME0, PSC0_DEADTIME1, PSC0_ONTIME1) \
00216 (OCR0SAH = HIGH((U16)PSC0_DEADTIME0), \
00217 OCR0SAL = LOW ((U16)PSC0_DEADTIME0), \
00218 OCR0RAH = HIGH((U16)PSC0_ONTIME0), \
00219 OCR0RAL = LOW ((U16)PSC0_ONTIME0), \
00220 OCR0SBH = HIGH((U16)PSC0_DEADTIME1), \
00221 OCR0SBL = LOW ((U16)PSC0_DEADTIME1), \
00222 OCR0RBH = HIGH((U16)PSC0_ONTIME1), \
00223 OCR0RBL = LOW ((U16)PSC0_ONTIME1) )
00225 #define Init_psc0_fifty_percent_compare_values(PSC0_DEADTIME1, PSC0_ONTIME1) \
00226 (OCR0SBH = HIGH((U16)PSC0_DEADTIME1), \
00227 OCR0SBL = LOW ((U16)PSC0_DEADTIME1), \
00228 OCR0RBH = HIGH((U16)PSC0_ONTIME1), \
00229 OCR0RBL = LOW ((U16)PSC0_ONTIME1) )
00231
00233
00234
00238
00242 #define Enable_pscout10() (PSOC1 |= (1<<POEN1A) )
00243 #define Disable_pscout10() (PSOC1 &= ~(1<<POEN1A) )
00244
00245 #define Enable_pscout11() (PSOC1 |= (1<<POEN1B) )
00246 #define Disable_pscout11() (PSOC1 &= ~(1<<POEN1B) )
00247
00248 #define Enable_both_psc1_outputs() \
00249 (PSOC1 |= ((1<<POEN1A) | (1<<POEN1B)))
00251 #define Disable_both_psc1_outputs() \
00252 (PSOC1 &= ~((1<<POEN1A) | (1<<POEN1B)))
00253
00254 #define Psc1_outputs_active_high() (PCNF1 |= (1<<POP1) )
00255 #define Psc1_outputs_active_low() (PCNF1 &= ~(1<<POP1) )
00256
00257
00261 #define Enable_psc1_fifty_percent_mode() (PCNF1 |= (1<<PFIFTY1) )
00262 #define Disable_psc1_fifty_percent_mode() (PCNF1 &= ~(1<<PFIFTY1) )
00263
00264 #define Enable_psc1_autolock_mode() (PCNF1 |= (1<<PALOCK1) )
00265 #define Disable_psc1_autolock_mode() (PCNF1 &= ~(1<<PALOCK1) )
00266
00267 #define Lock_psc1_compare_values() (PCNF1 |= (1<<PLOCK1) )
00268 #define Update_psc1_compare_values() (PCNF1 &= ~(1<<PLOCK1) )
00269
00270
00274
00279 #define Psc1_use_pll_clock() (PCNF1 |= (1<<PCLKSEL0) )
00281 #define Psc1_use_io_clock() (PCNF1 &= ~(1<<PCLKSEL0) )
00283 #define Psc1_use_64_mega_pll_clock() \
00284 (Start_pll_64_mega(), \
00285 Wait_pll_ready(), \
00286 Psc1_use_pll_clock() )
00288 #define Psc1_use_32_mega_pll_clock() \
00289 (Start_pll_32_mega(), \
00290 Wait_pll_ready(), \
00291 Psc1_use_pll_clock() )
00293
00298 #define Disable_psc1_prescaler() \
00299 (PCTL1 &= ~( (1<<PPRE11) | (1<<PPRE10) ) )
00301 #define Divide_psc1_input_clock_by_4() \
00302 (PCTL1 &= ~(1<<PPRE11), \
00303 PCTL1 |= (1<<PPRE10) )
00305 #define Divide_psc1_input_clock_by_16() \
00306 (PCTL1 |= (1<<PPRE11), \
00307 PCTL1 &= ~(1<<PPRE10) )
00309 #define Divide_psc1_input_clock_by_64() \
00310 (PCTL1 |= ((1<<PPRE11) | (1<<PPRE10)) )
00312
00314
00320 #define Psc1_in_1_ramp_mode() \
00321 (PCNF1 &= ~( (1<<PMODE11) | (1<<PMODE10) ) )
00324 #define Psc1_in_2_ramps_mode() \
00325 (PCNF1 &= ~(1<<PMODE11), \
00326 PCNF1 |= (1<<PMODE10) )
00329 #define Psc1_in_4_ramps_mode() \
00330 (PCNF1 |= (1<<PMODE11), \
00331 PCNF1 &= ~(1<<PMODE10) )
00334 #define Psc1_in_centered_aligned_mode() \
00335 (PCNF1 |= ( (1<<PMODE11) | (1<<PMODE10) ) )
00337
00341 #define Psc1_symetrical_flank_width_modulation() (PCTL1 |= (1<<PBFM1) )
00342 #define Psc1_end_of_cycle_flank_width_modulation() (PCTL1 &= ~(1<<PBFM1) )
00343
00344
00349 #define Psc1_synchro_on_waveform_generator_a_leading_edge() \
00350 (PSCO1 &= ~( (1<<PSYNC11) | (1<<PSYNC10) ) )
00352 #define Psc1_synchro_on_waveform_generator_a_trailing_edge() \
00353 (PSCO1 &= ~(1<<PSYNC11), \
00354 PSCO1 |= (1<<PSYNC10) )
00356 #define Psc1_synchro_on_waveform_generator_b_leading_edge() \
00357 (PSCO1 |= (1<<PSYNC11), \
00358 PSCO1 &= ~(1<<PSYNC10) )
00360 #define Psc1_synchro_on_waveform_generator_b_trailing_edge() \
00361 (PSCO1 |= ( (1<<PSYNC11) | (1<<PSYNC10) ) )
00363
00367 #define Start_psc1() (PCTL1 |= (1<<PRUN1) )
00368 #define Stop_psc1() (PCTL1 &= ~(1<<PRUN1) )
00369
00370 #define Psc1_complete_waveform_and_stop() (PCTL1 |= (1<<PCCYC1), \
00371 PCTL1 &= ~(1<<PRUN1) )
00372 #define Is_psc1_started() (PCTL1 & (1<<PRUN1) )
00374
00378 #define Enable_pscout10_fault_mode() (PCTL1 |= (1<<PAOC1A) )
00379 #define Disable_pscout10_fault_mode() (PCTL1 &= ~(1<<PAOC1A) )
00380
00381 #define Enable_pscout11_fault_mode() (PCTL1 |= (1<<PAOC1B) )
00382 #define Disable_pscout11_fault_mode() (PCTL1 &= ~(1<<PAOC1B) )
00383
00384 #define Enable_psc1_autorun() (PCTL1 |= (1<<PARUN1) )
00385 #define Disable_psc1_autorun() (PCTL1 &= ~(1<<PARUN1) )
00386
00387
00391 #define Enable_psc1_synchro_error_interrupt() (PIM1 |= (1<<PSEIE1) )
00392 #define Disable_psc1_synchro_error_interrupt() (PIM1 &= ~(1<<PSEIE1) )
00393
00394 #define Enable_psc1_external_event_a_interrupt() (PIM1 |= (1<<PEVE1A) )
00395 #define Disable_psc1_external_event_a_interrupt() (PIM1 &= ~(1<<PEVE1A) )
00396
00397 #define Enable_psc1_external_event_b_interrupt() (PIM1 |= (1<<PEVE1B) )
00398 #define Disable_psc1_external_event_b_interrupt() (PIM1 &= ~(1<<PEVE1B) )
00399
00400 #define Enable_psc1_end_of_cycle_interrupt() (PIM1 |= (1<<PEVE1A) )
00401 #define Disable_psc1_end_of_cycle_interrupt() (PIM1 &= ~(1<<PEVE1A) )
00402
00403
00407 #define Is_psc1_synchro_error_interrupt_flag_set() (PIFR1 & (1<<PSEI0) )
00408 #define Clear_psc1_synchro_error_interrupt_flag() (PIFR1 &= ~(1<<PSEI0) )
00409
00410 #define Is_psc1_external_event_a_interrupt_flag_set() (PIFR1 & (1<<PEV0A) )
00411 #define Clear_psc1_external_event_a_interrupt_flag() (PIFR1 &= ~(1<<PEV0A) )
00412
00413 #define Is_psc1_external_event_b_interrupt_flag_set() (PIFR1 & (1<<PEV0B) )
00414 #define Clear_psc1_external_event_b_interrupt_flag() (PIFR1 &= ~(1<<PEV0B) )
00415
00416 #define Is_psc1_end_of_cycle_interrupt_flag_set() (PIFR1 & (1<<PEOP1) )
00417 #define Clear_psc1_end_of_cycle_interrupt_flag() (PIFR1 &= ~(1<<PEOP1) )
00418
00419
00424 #define Init_psc1_all_compare_values(PSC1_DEADTIME0, PSC1_ONTIME0, PSC1_DEADTIME1, PSC1_ONTIME1) \
00425 (OCR1SAH = HIGH((U16)PSC1_DEADTIME0), \
00426 OCR1SAL = LOW ((U16)PSC1_DEADTIME0), \
00427 OCR1RAH = HIGH((U16)PSC1_ONTIME0), \
00428 OCR1RAL = LOW ((U16)PSC1_ONTIME0), \
00429 OCR1SBH = HIGH((U16)PSC1_DEADTIME1), \
00430 OCR1SBL = LOW ((U16)PSC1_DEADTIME1), \
00431 OCR1RBH = HIGH((U16)PSC1_ONTIME1), \
00432 OCR1RBL = LOW ((U16)PSC1_ONTIME1) )
00434 #define Init_psc1_fifty_percent_compare_values(PSC1_DEADTIME1, PSC1_ONTIME1) \
00435 (OCR1SBH = HIGH((U16)PSC1_DEADTIME1), \
00436 OCR1SBL = LOW ((U16)PSC1_DEADTIME1), \
00437 OCR1RBH = HIGH((U16)PSC1_ONTIME1), \
00438 OCR1RBL = LOW ((U16)PSC1_ONTIME1) )
00441
00442
00446
00450 #define Enable_pscout20() (PSOC2 |= (1<<POEN2A) )
00451 #define Disable_pscout20() (PSOC2 &= ~(1<<POEN2A) )
00452
00453 #define Enable_pscout21() (PSOC2 |= (1<<POEN2B) )
00454 #define Disable_pscout21() (PSOC2 &= ~(1<<POEN2B) )
00455
00456 #define Enable_both_psc2_outputs() \
00457 (PSOC2 |= ((1<<POEN2A) | (1<<POEN2B)))
00459 #define Disable_both_psc2_outputs() \
00460 (PSOC2 &= ~((1<<POEN2A) | (1<<POEN2B)))
00461
00462 #define Psc2_outputs_active_high() (PCNF2 |= (1<<POP2) )
00463 #define Psc2_outputs_active_low() (PCNF2 &= ~(1<<POP2) )
00464
00465
00469 #define Enable_psc2_fifty_percent_mode() (PCNF2 |= (1<<PFIFTY2) )
00470 #define Disable_psc2_fifty_percent_mode() (PCNF2 &= ~(1<<PFIFTY2) )
00471
00472 #define Enable_psc2_autolock_mode() (PCNF2 |= (1<<PALOCK2) )
00473 #define Disable_psc2_autolock_mode() (PCNF2 &= ~(1<<PALOCK2) )
00474
00475 #define Lock_psc2_compare_values() (PCNF2 |= (1<<PLOCK2) )
00476 #define Update_psc2_compare_values() (PCNF2 &= ~(1<<PLOCK2) )
00477
00478
00482
00487 #define Psc2_use_pll_clock() (PCNF2 |= (1<<PCLKSEL0) )
00489 #define Psc2_use_io_clock() (PCNF2 &= ~(1<<PCLKSEL0) )
00491 #define Psc2_use_64_mega_pll_clock() \
00492 (Start_pll_64_mega(), \
00493 Wait_pll_ready(), \
00494 Psc2_use_pll_clock() )
00496 #define Psc2_use_32_mega_pll_clock() \
00497 (Start_pll_32_mega(), \
00498 Wait_pll_ready(), \
00499 Psc2_use_pll_clock() )
00501
00506 #define Disable_psc2_prescaler() \
00507 (PCTL2 &= ~( (1<<PPRE21) | (1<<PPRE20) ) )
00509 #define Divide_psc2_input_clock_by_4() \
00510 (PCTL2 &= ~(1<<PPRE21), \
00511 PCTL2 |= (1<<PPRE20) )
00513 #define Divide_psc2_input_clock_by_16() \
00514 (PCTL2 |= (1<<PPRE21), \
00515 PCTL2 &= ~(1<<PPRE20) )
00517 #define Divide_psc2_input_clock_by_64() \
00518 (PCTL2 |= ((1<<PPRE21) | (1<<PPRE20)) )
00520
00522
00528 #define Psc2_in_1_ramp_mode() \
00529 (PCNF2 &= ~( (1<<PMODE21) | (1<<PMODE20) ) )
00532 #define Psc2_in_2_ramps_mode() \
00533 (PCNF2 &= ~(1<<PMODE21), \
00534 PCNF2 |= (1<<PMODE20) )
00537 #define Psc2_in_4_ramps_mode() \
00538 (PCNF2 |= (1<<PMODE21), \
00539 PCNF2 &= ~(1<<PMODE20) )
00542 #define Psc2_in_centered_aligned_mode() \
00543 (PCNF2 |= ( (1<<PMODE21) | (1<<PMODE20) ) )
00545
00549 #define Psc2_symetrical_flank_width_modulation() (PCTL2 |= (1<<PBFM2) )
00550 #define Psc2_end_of_cycle_flank_width_modulation() (PCTL2 &= ~(1<<PBFM2) )
00551
00552
00557 #define Psc2_synchro_on_waveform_generator_a_leading_edge() \
00558 (PSCO2 &= ~( (1<<PSYNC21) | (1<<PSYNC20) ) )
00560 #define Psc2_synchro_on_waveform_generator_a_trailing_edge() \
00561 (PSCO2 &= ~(1<<PSYNC21), \
00562 PSCO2 |= (1<<PSYNC20) )
00564 #define Psc2_synchro_on_waveform_generator_b_leading_edge() \
00565 (PSCO2 |= (1<<PSYNC21), \
00566 PSCO2 &= ~(1<<PSYNC20) )
00568 #define Psc2_synchro_on_waveform_generator_b_trailing_edge() \
00569 (PSCO2 |= ( (1<<PSYNC21) | (1<<PSYNC20) ) )
00571
00575 #define Start_psc2() (PCTL2 |= (1<<PRUN2) )
00576 #define Stop_psc2() (PCTL2 &= ~(1<<PRUN2) )
00577
00578 #define Psc2_complete_waveform_and_stop() (PCTL2 |= (1<<PCCYC2), \
00579 PCTL2 &= ~(1<<PRUN2) )
00580 #define Is_psc2_started() (PCTL2 & (1<<PRUN2) )
00582
00586 #define Enable_pscout20_fault_mode() (PCTL2 |= (1<<PAOC2A) )
00587 #define Disable_pscout20_fault_mode() (PCTL2 &= ~(1<<PAOC2A) )
00588
00589 #define Enable_pscout21_fault_mode() (PCTL2 |= (1<<PAOC2B) )
00590 #define Disable_pscout21_fault_mode() (PCTL2 &= ~(1<<PAOC2B) )
00591
00592 #define Enable_psc2_autorun() (PCTL2 |= (1<<PARUN2) )
00593 #define Disable_psc2_autorun() (PCTL2 &= ~(1<<PARUN2) )
00594
00595
00599 #define Enable_psc2_synchro_error_interrupt() (PIM2 |= (1<<PSEIE2) )
00600 #define Disable_psc2_synchro_error_interrupt() (PIM2 &= ~(1<<PSEIE2) )
00601
00602 #define Enable_psc2_external_event_a_interrupt() (PIM2 |= (1<<PEVE2A) )
00603 #define Disable_psc2_external_event_a_interrupt() (PIM2 &= ~(1<<PEVE2A) )
00604
00605 #define Enable_psc2_external_event_b_interrupt() (PIM2 |= (1<<PEVE2B) )
00606 #define Disable_psc2_external_event_b_interrupt() (PIM2 &= ~(1<<PEVE2B) )
00607
00608 #define Enable_psc2_end_of_cycle_interrupt() (PIM2 |= (1<<PEOPE2) )
00609 #define Disable_psc2_end_of_cycle_interrupt() (PIM2 &= ~(1<<PEOPE2) )
00610
00611
00615 #define Is_psc2_synchro_error_interrupt_flag_set() (PIFR2 & (1<<PSEI0) )
00616 #define Clear_psc2_synchro_error_interrupt_flag() (PIFR2 &= ~(1<<PSEI0) )
00617
00618 #define Is_psc2_external_event_a_interrupt_flag_set() (PIFR2 & (1<<PEV0A) )
00619 #define Clear_psc2_external_event_a_interrupt_flag() (PIFR2 &= ~(1<<PEV0A) )
00620
00621 #define Is_psc2_external_event_b_interrupt_flag_set() (PIFR2 & (1<<PEV0B) )
00622 #define Clear_psc2_external_event_b_interrupt_flag() (PIFR2 &= ~(1<<PEV0B) )
00623
00624 #define Is_psc2_end_of_cycle_interrupt_flag_set() (PIFR2 & (1<<PEOP2) )
00625 #define Clear_psc2_end_of_cycle_interrupt_flag() (PIFR2 &= ~(1<<PEOP2) )
00626
00627
00632 #define Init_psc2_all_compare_values(PSC2_DEADTIME0, PSC2_ONTIME0, PSC2_DEADTIME1, PSC2_ONTIME1) \
00633 (OCR2SAH = HIGH((U16)PSC2_DEADTIME0), \
00634 OCR2SAL = LOW ((U16)PSC2_DEADTIME0), \
00635 OCR2RAH = HIGH((U16)PSC2_ONTIME0), \
00636 OCR2RAL = LOW ((U16)PSC2_ONTIME0), \
00637 OCR2SBH = HIGH((U16)PSC2_DEADTIME1), \
00638 OCR2SBL = LOW ((U16)PSC2_DEADTIME1), \
00639 OCR2RBH = HIGH((U16)PSC2_ONTIME1), \
00640 OCR2RBL = LOW ((U16)PSC2_ONTIME1) )
00642 #define Init_psc2_fifty_percent_compare_values(PSC2_DEADTIME1,PSC2_ONTIME1) \
00643 (OCR2SBH = HIGH((U16)PSC2_DEADTIME1), \
00644 OCR2SBL = LOW ((U16)PSC2_DEADTIME1), \
00645 OCR2RBH = HIGH((U16)PSC2_ONTIME1), \
00646 OCR2RBL = LOW ((U16)PSC2_ONTIME1) )
00648
00649
00650
00654 typedef struct st_psc_comparison_values {
00655 U16 deadtime0;
00656 U16 ontime0;
00657 U16 deadtime1;
00658 U16 ontime1;
00659 }Psc_comparison_values;
00660
00661 typedef struct st_psc_fifty_percent_comparison_values {
00662 U16 deadtime1;
00663 U16 ontime1;
00664 }Psc_fifty_percent_comparison_values;
00666
00667
00673 void init_psc0 (void);
00676 void update_psc0 ( Psc_comparison_values *psc0_comparison_values );
00679 void update_psc0_fifty ( Psc_fifty_percent_comparison_values *psc0_fifty_percent_comparison_values );
00681
00687 void init_psc1 (void);
00690 void update_psc1 ( Psc_comparison_values *psc1_comparison_values );
00693 void update_psc1_fifty ( Psc_fifty_percent_comparison_values *psc1_fifty_percent_comparison_values );
00695
00701 void init_psc2 (void);
00704 void update_psc2 ( Psc_comparison_values *psc2_comparison_values );
00707 void update_psc2_fifty ( Psc_fifty_percent_comparison_values *psc2_fifty_percent_comparison_values );
00709
00711 #endif // PSC_DRV_H
