Atmel BLDC Sensorless on ATAVRMC100: mcu.h Source File

00001 /*H**************************************************************************
00002 * $RCSfile: mcu.h,v $
00003 *----------------------------------------------------------------------------
00004 * Copyright (c) 2003 Atmel.
00005 *----------------------------------------------------------------------------
00006 * RELEASE:      $Name: mc100_bldc_sensorless_0_1_0 $
00007 * REVISION:     $Revision: 1.6.6.2.2.19 $
00008 * FILE_CVSID:   $Id: mcu.h,v 1.6.6.2.2.19 2005/11/28 15:23:21 jberthy Exp $
00009 *----------------------------------------------------------------------------
00010 * PURPOSE:
00011 * SFR Description file for Atmegabalast.
00012 *****************************************************************************/
00013 #ifndef MCU_H
00014 #define MCU_H
00015 
00016 #define IRQ_MEM_SPACE   2
00017 
00018 /*==========================*/
00019 /* Predefined SFR Addresses */
00020 /*==========================*/
00021 
00022 /******************************************************************************/
00023 #ifdef __IAR_SYSTEMS_ICC__
00024 /******************************************************************************/
00025 SFR_B(PINB,    0x03)    /* Input Pins, Port B */
00026 SFR_B(DDRB,    0x04)    /* Data Direction Register, Port B */
00027 SFR_B(PORTB,   0x05)    /* Data Register, Port B */
00028 
00029 SFR_B(PINC,    0x06)    /* Input Pins, Port C */
00030 SFR_B(DDRC,    0x07)    /* Data Direction Register, Port C */
00031 SFR_B(PORTC,   0x08)    /* Data Register, Port C */
00032 
00033 SFR_B(PIND,    0x09)    /* Input Pins, Port D */
00034 SFR_B(DDRD,    0x0A)    /* Data Direction Register, Port D */
00035 SFR_B(PORTD,   0x0B)    /* Data Register, Port D */
00036 
00037 SFR_B(PINE,    0x0C)    /* Input Pins, Port E */
00038 SFR_B(DDRE,    0x0D)    /* Data Direction Register, Port E */
00039 SFR_B(PORTE,   0x0E)    /* Data Register, Port E */
00040 
00041 SFR_B(TIFR0,   0x15)    /* Timer/Counter Interrupt Flag register 0*/
00042 SFR_B(TIFR1,   0x16)    /* Timer/Counter Interrupt Flag register 1*/
00043 
00044 SFR_B(GPIOR1,  0x19)    /* General Purpose Register 1 */
00045 SFR_B(GPIOR2,  0x1A)    /* General Purpose Register 2 */
00046 SFR_B(GPIOR3,  0x1B)    /* General Purpose Register 3 */
00047 
00048 SFR_B(EIFR,    0x1C)    /* External Interrupt Flag Register */
00049 SFR_B(EIMSK,   0x1D)    /* External Interrupt Mask Register */
00050 
00051 SFR_B(GPIOR0,  0x1E)    /* General Purpose Register 0 */
00052 
00053 SFR_B(EECR,    0x1F)    /* EEPROM Control Register */
00054 SFR_B(EEDR,    0x20)    /* EEPROM Data Register */
00055 SFR_W(EEAR,    0x21)    /* EEPROM Address Register */
00056 
00057 SFR_B(GTCCR,   0x23)    /* General Purpose Register */
00058 
00059 SFR_B(TCCR0A,  0x24)    /* Timer/Counter 0 Control Register */
00060 SFR_B(TCCR0B,  0x25)    /* Timer/Counter 0 Control Register */
00061 
00062 SFR_B(TCNT0,   0x26)    /* Timer/Counter 0 */
00063 SFR_B(OCR0A,   0x27)    /* Timer/Counter 0 Output Compare Register */
00064 SFR_B(OCR0B,   0x28)    /* Timer/Counter 0 Output Compare Register */
00065 
00066 SFR_B(PLLCSR,  0x29)    /* Pll Control and status register */
00067 
00068 SFR_B(SPCR,    0x2C)    /* SPI Control Register */
00069 SFR_B(SPSR,    0x2D)    /* SPI Status Register */
00070 SFR_B(SPDR,    0x2E)    /* SPI I/O Data Register */
00071 
00072 SFR_B(ACSR,    0x30)    /* Analog Comparator Control and Status Register */
00073 
00074 SFR_B(MONDR,   0x31)    /* On-Chip Debug Register */
00075 SFR_B(MSMCR,   0x32)    /* Monitor stop mode ctrl register */
00076 
00077 SFR_B(SMCR,    0x33)    /* Sleep Mode Control Register */
00078 
00079 SFR_B(MCUSR,   0x34)    /* MCU Status Register */
00080 SFR_B(MCUCR,   0x35)    /* MCU Control Register */
00081 
00082 SFR_B(SPMCSR,  0x37)    /* Store Program Memory Control and Status Register */
00083 
00084 SFR_W(SP,      0x3D)    /* Stack Pointer */
00085 
00086 SFR_B(SREG,    0x3F)    /* Status Register */
00087 
00088 SFR_B_EXT(WDTCSR,  0x60) /* Watchdog Timer Control Register */
00089 SFR_B_EXT(CLKPR,  0x61) /* Clock Prescale Register */
00090 SFR_B_EXT(PRR,    0x64) /* Power Reduction Register */
00091 
00092 SFR_B_EXT(OSCCAL, 0x66) /* Oscillator Calibration Register */
00093 
00094 SFR_B_EXT(EICRA,  0x69) /* External Interrupt Control Register A */
00095 
00096 SFR_B_EXT(TIMSK0, 0x6E) /* Timer/Counter 0 Interrupt Mask Register */
00097 SFR_B_EXT(TIMSK1, 0x6F) /* Timer/Counter 1 Interrupt Mask Register */
00098 
00099 SFR_B_EXT(AMP0CSR,0x76) /* Amplifier 0 ctrl and status register */
00100 SFR_B_EXT(AMP1CSR,0x77) /* Amplifier 1 ctrl and status register */
00101 
00102 SFR_W_EXT(ADC,    0x78) /* ADC Data register  */
00103 SFR_B_EXT(ADCSRA, 0x7A) /* ADC Control and Status Register A */
00104 SFR_B_EXT(ADCSRB, 0x7B) /* ADC Control and Status Register B */
00105 SFR_B_EXT(ADMUX,  0x7C) /* ADC Multiplexer Selection Register */
00106 
00107 SFR_B_EXT(DIDR0,  0x7E) /* Digital Input Disable Register 0 */
00108 SFR_B_EXT(DIDR1,  0x7F) /* Digital Input Disable Register 1 */
00109 
00110 SFR_B_EXT(TCCR1A, 0x80) /* Timer/Counter 1 Control Register A */
00111 SFR_B_EXT(TCCR1B, 0x81) /* Timer/Counter 1 Control Register B */
00112 SFR_B_EXT(TCCR1C, 0x82) /* Timer/Counter 1 Control Register C */
00113 SFR_W_EXT(TCNT1,  0x84) /* Timer/Counter 1 Register */
00114 SFR_W_EXT(ICR1,   0x86) /* Timer/Counter 1 Input Capture Register */
00115 SFR_W_EXT(OCR1A,  0x88) /* Timer/Counter 1 Output Compare Register A */
00116 SFR_W_EXT(OCR1B,  0x8A) /* Timer/Counter 1 Output Compare Register B */
00117 
00118 SFR_B_EXT(PIFR0,  0xA0) /* PSC 0 Interrupt Flag Register */
00119 SFR_B_EXT(PIM0,   0xA1) /* PSC 0 Interrupt Mask Register */
00120 
00121 SFR_B_EXT(PIFR1,  0xA2) /* PSC 1 Interrupt Flag Register */
00122 SFR_B_EXT(PIM1,   0xA3) /* PSC 1 Interrupt Mask Register */
00123 
00124 SFR_B_EXT(PIFR2,  0xA4) /* PSC 2 Interrupt Flag Register */
00125 SFR_B_EXT(PIM2,   0xA5) /* PSC 2 Interrupt Mask Register */
00126 
00127 SFR_B_EXT(DACON,  0xAA) /* DAC Control Register*/
00128 SFR_W_EXT(DAC,    0xAB) /* DAC Data Register*/
00129 
00130 SFR_B_EXT(AC0CON, 0xAD) /* Analog Comparator 0 status register */
00131 SFR_B_EXT(AC1CON, 0xAE) /* Analog Comparator 1 status register */
00132 SFR_B_EXT(AC2CON, 0xAF) /* Analog Comparator 2 status register */
00133 
00134 SFR_B_EXT(UCSRA,  0xC0) /* USART Control and Status Register A */
00135 SFR_B_EXT(UCSRB,  0xC1) /* USART Control and Status Register B */
00136 SFR_B_EXT(UCSRC,  0xC2) /* USART Control and Status Register C */
00137 SFR_W_EXT(UBRR,   0xC4) /* USART Baud Rate Register Low */
00138 SFR_B_EXT(UDR,    0xC6) /* USART0 I/O Data Register */
00139 
00140 /* UCSR0x left for software compatibility*/
00141 SFR_B_EXT(UCSR0A, 0xC0) /* USART Control and Status Register A */
00142 SFR_B_EXT(UCSR0B, 0xC1) /* USART Control and Status Register B */
00143 SFR_B_EXT(UCSR0C, 0xC2) /* USART Control and Status Register C */
00144 SFR_W_EXT(UBRR0,  0xC4) /* USART Baud Rate Register Low */
00145 SFR_B_EXT(UDR0,   0xC6) /* USART0 I/O Data Register */
00146 
00147 SFR_B_EXT(EUCSRA, 0xC8) /* EUSART Control and Status Register A */
00148 SFR_B_EXT(EUCSRB, 0xC9) /* EUSART Control and Status Register B */
00149 SFR_B_EXT(EUCSRC, 0xCA) /* EUSART Control and Status Register C */
00150 SFR_W_EXT(MUBRR,  0xCC) /* EUSART Manchester counter max value */
00151 SFR_B_EXT(EUDR,   0xCE) /* USART0 I/O Data Register */
00152 
00153 SFR_B_EXT(PSOC0,  0xD0) /* PSC 0 Synchro & Output Configuration */
00154 SFR_W_EXT(OCR0SA, 0xD2) /* PSC 0 Output Compare Register SA */
00155 SFR_W_EXT(OCR0RA, 0xD4) /* PSC 0 Output Compare Register RA */
00156 SFR_W_EXT(OCR0SB, 0xD6) /* PSC 0 Output Compare Register SB */
00157 SFR_W_EXT(OCR0RB, 0xD8) /* PSC 0 Output Compare Register RB */
00158 SFR_B_EXT(PCNF0,  0xDA) /* PSC 0 Configuration Register */
00159 SFR_B_EXT(PCTL0,  0xDB) /* PSC 0 Control Register */
00160 SFR_B_EXT(PFRC0A, 0xDC) /* PSC 0 Input A Control Register */
00161 SFR_B_EXT(PFRC0B, 0xDD) /* PSC 0 Input B Control Register */
00162 SFR_W_EXT(PICR0,  0xDE) /* PSC 0 Input Capture Register */
00163 
00164 SFR_B_EXT(PSOC1,  0xE0) /* PSC 1 Synchro & Output Configuration */
00165 SFR_W_EXT(OCR1SA, 0xE2) /* PSC 1 Output Compare Register SA */
00166 SFR_W_EXT(OCR1RA, 0xE4) /* PSC 1 Output Compare Register RA */
00167 SFR_W_EXT(OCR1SB, 0xE6) /* PSC 1 Output Compare Register SB */
00168 SFR_W_EXT(OCR1RB, 0xE8) /* PSC 1 Output Compare Register RB */
00169 SFR_B_EXT(PCNF1,  0xEA) /* PSC 1 Configuration Register */
00170 SFR_B_EXT(PCTL1,  0xEB) /* PSC 1 Control Register */
00171 SFR_B_EXT(PFRC1A, 0xEC) /* PSC 1 Input A Control Register */
00172 SFR_B_EXT(PFRC1B, 0xED) /* PSC 1 Input B Control Register */
00173 SFR_W_EXT(PICR1,  0xEE) /* PSC 1 Input Capture Register */
00174 
00175 SFR_B_EXT(PSOC2,  0xF0) /* PSC 2 Synchro & Output Configuration */
00176 SFR_B_EXT(POM2,   0xF1) /* PSC 2 Output Matrix Register */
00177 SFR_W_EXT(OCR2SA, 0xF2) /* PSC 2 Output Compare Register SA */
00178 SFR_W_EXT(OCR2RA, 0xF4) /* PSC 2 Output Compare Register RA */
00179 SFR_W_EXT(OCR2SB, 0xF6) /* PSC 2 Output Compare Register SB */
00180 SFR_W_EXT(OCR2RB, 0xF8) /* PSC 2 Output Compare Register RB */
00181 SFR_B_EXT(PCNF2,  0xFA) /* PSC 2 Configuration Register */
00182 SFR_B_EXT(PCTL2,  0xFB) /* PSC 2 Control Register */
00183 SFR_B_EXT(PFRC2A, 0xFC) /* PSC 2 Input A Control Register */
00184 SFR_B_EXT(PFRC2B, 0xFD) /* PSC 2 Input B Control Register */
00185 SFR_W_EXT(PICR2,  0xFE) /* PSC 2 Input Capture Register */
00186 
00187 /*==============================*/
00188 /* Interrupt Vector Definitions */
00189 /*==============================*/
00190 /* NB! vectors are specified as byte addresses */
00191 #define    RESET_vect         (0x00*IRQ_MEM_SPACE)
00192 #define    PSC2_CAPT_vect     (0x01*IRQ_MEM_SPACE)
00193 #define    PSC2EC_vect        (0x02*IRQ_MEM_SPACE)
00194 #define    PSC1_CAPT_vect       (0x03*IRQ_MEM_SPACE)
00195 #define    PSC1EC_vect          (0x04*IRQ_MEM_SPACE)
00196 #define    PSC0_CAPT_vect       (0x05*IRQ_MEM_SPACE)
00197 #define    PSC0EC_vect          (0x06*IRQ_MEM_SPACE)
00198 #define    ANACOMP_0_vect     (0x07*IRQ_MEM_SPACE)
00199 #define    ANACOMP_1_vect       (0x08*IRQ_MEM_SPACE)
00200 #define    ANACOMP_2_vect       (0x09*IRQ_MEM_SPACE)
00201 #define    INT0_vect          (0x0A*IRQ_MEM_SPACE)
00202 #define    TIMER1_CAPT_vect   (0x0B*IRQ_MEM_SPACE)
00203 #define    TIMER1_COMPA_vect  (0x0C*IRQ_MEM_SPACE)
00204 #define    TIMER1_COMPB_vect  (0x0D*IRQ_MEM_SPACE)
00205 #define    TIMER1_OVF_vect    (0x0F*IRQ_MEM_SPACE)
00206 #define    TIMER0_COMPA_vect  (0x10*IRQ_MEM_SPACE)
00207 #define    TIMER0_OVF_vect    (0x11*IRQ_MEM_SPACE)
00208 #define    ADC_vect           (0x12*IRQ_MEM_SPACE)
00209 #define    INT1_vect          (0x13*IRQ_MEM_SPACE)
00210 #define    SPI_STC_vect       (0x14*IRQ_MEM_SPACE)
00211 #define    USART_RXC_vect     (0x15*IRQ_MEM_SPACE)
00212 #define    USART_UDRE_vect    (0x16*IRQ_MEM_SPACE)
00213 #define    USART_TXC_vect     (0x17*IRQ_MEM_SPACE)
00214 #define    INT2_vect          (0x18*IRQ_MEM_SPACE)
00215 #define    WDT_vect           (0x19*IRQ_MEM_SPACE)
00216 #define    EE_RDY_vect        (0x1A*IRQ_MEM_SPACE)
00217 #define    TIMER0_COMPB_vect  (0x1B*IRQ_MEM_SPACE)
00218 #define    INT3_vect          (0x1C*IRQ_MEM_SPACE)
00219 #define    SPM_READY_vect     (0x1F*IRQ_MEM_SPACE)
00220 
00221 #endif /* _IAR_ */
00222 /******************************************************************************/
00223 #ifdef _ICC_
00224 /******************************************************************************/
00225 
00226 #define PINB    (*(volatile unsigned char *)0x23) /* Input Pins, Port B */
00227 #define DDRB    (*(volatile unsigned char *)0x24) /* Data Direction Register, Port B */
00228 #define PORTB   (*(volatile unsigned char *)0x25) /* Data Register, Port B */
00229 
00230 #define PINC    (*(volatile unsigned char *)0x26) /* Input Pins, Port C */
00231 #define DDRC    (*(volatile unsigned char *)0x27) /* Data Direction Register, Port C */
00232 #define PORTC   (*(volatile unsigned char *)0x28) /* Data Register, Port C */
00233 
00234 #define PIND    (*(volatile unsigned char *)0x29) /* Input Pins, Port D */
00235 #define DDRD    (*(volatile unsigned char *)0x2A) /* Data Direction Register, Port D */
00236 #define PORTD   (*(volatile unsigned char *)0x2B) /* Data Register, Port D */
00237 
00238 #define PINE    (*(volatile unsigned char *)0x2C) /* Input Pins, Port E */
00239 #define DDRE    (*(volatile unsigned char *)0x2D) /* Data Direction Register, Port E */
00240 #define PORTE   (*(volatile unsigned char *)0x2E) /* Data Register, Port E */
00241 
00242 #define TIFR0   (*(volatile unsigned char *)0x35) /* Timer/Counter Interrupt Flag register 0*/
00243 #define TIFR1   (*(volatile unsigned char *)0x36) /* Timer/Counter Interrupt Flag register 1*/
00244 
00245 #define GPIOR1  (*(volatile unsigned char *)0x39)     /* General Purpose Register 1 */
00246 #define GPIOR2  (*(volatile unsigned char *)0x3A)     /* General Purpose Register 2 */
00247 #define GPIOR3  (*(volatile unsigned char *)0x3B)     /* General Purpose Register 3 */
00248 
00249 #define EIFR    (*(volatile unsigned char *)0x3C)     /* External Interrupt Flag Register */
00250 #define EIMSK   (*(volatile unsigned char *)0x3D)     /* External Interrupt Mask Register */
00251 
00252 #define GPIOR0  (*(volatile unsigned char *)0x3E)     /* General Purpose Register 0 */
00253 
00254 #define EECR    (*(volatile unsigned char *)0x3F)     /* EEPROM Control Register */
00255 #define EEDR    (*(volatile unsigned char *)0x40)     /* EEPROM Data Register */
00256 #define EEAR    (*(volatile unsigned int *)0x41)      /* EEPROM Address Register */
00257 
00258 #define GTCCR   (*(volatile unsigned char *)0x43)     /* General Purpose Register */
00259 
00260 #define TCCR0A  (*(volatile unsigned char *)0x44)     /* Timer/Counter 0 Control Register */
00261 #define TCCR0B  (*(volatile unsigned char *)0x45)     /* Timer/Counter 0 Control Register */
00262 #define TCNT0   (*(volatile unsigned char *)0x46)     /* Timer/Counter 0 */
00263 #define OCR0A   (*(volatile unsigned char *)0x47)     /* Timer/Counter 0 Output Compare Register */
00264 #define OCR0B   (*(volatile unsigned char *)0x48)     /* Timer/Counter 0 Output Compare Register */
00265 
00266 #define PLLCSR   (*(volatile unsigned char *)0x49)     /* Pll control and status Register */
00267 
00268 #define SPCR    (*(volatile unsigned char *)0x4C)     /* SPI Control Register */
00269 #define SPSR    (*(volatile unsigned char *)0x4D)     /* SPI Status Register */
00270 #define SPDR    (*(volatile unsigned char *)0x4E)     /* SPI I/O Data Register */
00271 
00272 #define ACSR    (*(volatile unsigned char *)0x50)     /* Analog Comparator Control and Status Register */
00273 
00274 #define MONDR    (*(volatile unsigned char *)0x51)     /* On-Chip Debug Register */
00275 #define MSMDR    (*(volatile unsigned char *)0x52)     /* Monitor Stop mode control Register */
00276 
00277 #define SMCR    (*(volatile unsigned char *)0x53)     /* Sleep Mode Control Register */
00278 #define MCUSR   (*(volatile unsigned char *)0x54)     /* MCU Status Register */
00279 #define MCUCR   (*(volatile unsigned char *)0x55)     /* MCU Control Register */
00280 
00281 #define SPMCSR  (*(volatile unsigned char *)0x57)     /* Store Program Memory Control and Status Register */
00282 
00283 #define SP      (*(volatile unsigned int *)0x5D)      /* Stack Pointer */
00284 #define SREG    (*(volatile unsigned char *)0x5F)     /* Status Register */
00285 
00286 #define WDTCSR   (*(volatile unsigned char *)0x60)     /* Watchdog Timer Control Register */
00287 #define CLKPR   (*(volatile unsigned char *)0x61)     /* Clock Prescale Register */
00288 #define PRR   (*(volatile unsigned char *)0x64)     /* Power Reduction Register */
00289 #define OSCCAL  (*(volatile unsigned char *)0x66)     /* Oscillator Calibration Register */
00290 
00291 #define EICRA   (*(volatile unsigned char *)0x69)     /* External Interrupt Control Register A */
00292 
00293 #define TIMSK0  (*(volatile unsigned char *)0x6E)     /* Timer/Counter 0 Interrupt Mask Register */
00294 #define TIMSK1  (*(volatile unsigned char *)0x6F)     /* Timer/Counter 1 Interrupt Mask Register */
00295 
00296 #define AMP0CSR (*(volatile unsigned int *)0x76)      /* Amplifier0 ctrl and status register */
00297 #define AMP1CSR (*(volatile unsigned char *)0x77)     /* Amplifier1 ctrl and status register */
00298 
00299 #define ADC     (*(volatile unsigned int *)0x78)      /* ADC Data register */
00300 #define ADCL     (*(volatile unsigned char *)0x78)      /* ADC Data register */
00301 #define ADCH     (*(volatile unsigned char *)0x79)      /* ADC Data register */
00302 #define ADCSRA  (*(volatile unsigned char *)0x7A)     /* ADC Control and Status Register A */
00303 #define ADCSRB  (*(volatile unsigned char *)0x7B)     /* ADC Control and Status Register B */
00304 #define ADMUX   (*(volatile unsigned char *)0x7C)     /* ADC Multiplexer Selection Register */
00305 
00306 #define DIDR0   (*(volatile unsigned char *)0x7E)     /* Digital Input Disable Register 0 */
00307 #define DIDR1   (*(volatile unsigned char *)0x7F)     /* Digital Input Disable Register 1 */
00308 
00309 #define TCCR1A  (*(volatile unsigned char *)0x80)     /* Timer/Counter 1 Control Register A */
00310 #define TCCR1B  (*(volatile unsigned char *)0x81)     /* Timer/Counter 1 Control Register B */
00311 #define TCCR1C  (*(volatile unsigned char *)0x82)     /* Timer/Counter 1 Control Register C */
00312 #define TCNT1   (*(volatile unsigned int *)0x84)      /* Timer/Counter 1 Register */
00313 #define ICR1    (*(volatile unsigned int *)0x86)      /* Timer/Counter 1 Input Capture Register */
00314 #define OCR1A   (*(volatile unsigned int *)0x88)      /* Timer/Counter 1 Output Compare Register A */
00315 #define OCR1AL   (*(volatile unsigned char *)0x88)      /* Timer/Counter 1 Output Compare Register A */
00316 #define OCR1AH   (*(volatile unsigned char *)0x89)      /* Timer/Counter 1 Output Compare Register A */
00317 
00318 #define OCR1B   (*(volatile unsigned int *)0x8A)      /* Timer/Counter 1 Output Compare Register B */
00319 
00320 #define PIFR0   (*(volatile unsigned char *)0xA0)      /* PSC0 interrupt flag Register */
00321 #define PIM0   (*(volatile unsigned char *)0xA1)      /* PSC 0 interrupt mask Register */
00322 
00323 #define PIFR1   (*(volatile unsigned char *)0xA2)      /* PSC1 interrupt flag Register */
00324 #define PIM1   (*(volatile unsigned char *)0xA3)      /* PSC 1 interrupt mask Register */
00325 
00326 #define PIFR2   (*(volatile unsigned char *)0xA4)      /* PSC2 interrupt flag Register */
00327 #define PIM2   (*(volatile unsigned char *)0xA5)      /* PSC 2 interrupt mask Register */
00328 
00329 #define DACON   (*(volatile unsigned char *)0xAA)      /* DAC Control Register */
00330 #define DAC   (*(volatile unsigned int *)0xAB)      /* DAC data Register */
00331 #define DACL   (*(volatile unsigned char *)0xAB)      /* DAC data Register */
00332 #define DACH   (*(volatile unsigned char *)0xAC)      /* DAC data Register */
00333 
00334 #define AC0CON   (*(volatile unsigned char *)0xAD)      /* Analog Comparator 0 status register */
00335 #define AC1CON   (*(volatile unsigned char *)0xAE)      /* Analog Comparator 1 status register */
00336 #define AC2CON   (*(volatile unsigned char *)0xAF)      /* Analog Comparator 2 status register */
00337 
00338 #define UCSRA  (*(volatile unsigned char *)0xC0)      /* USART Control and Status Register A */
00339 #define UCSRB  (*(volatile unsigned char *)0xC1)      /* USART Control and Status Register B */
00340 #define UCSRC  (*(volatile unsigned char *)0xC2)      /* USART Control and Status Register C */
00341 #define UBRR   (*(volatile unsigned int *)0xC4)       /* USART Baud Rate Register  */
00342 #define UBRRL  (*(volatile unsigned char *)0xC4)      /* USART Baud Rate Register Low */
00343 #define UBRRH  (*(volatile unsigned char *)0xC5)      /* USART Baud Rate Register High */
00344 #define UDR    (*(volatile unsigned char *)0xC6)      /* USART I/O Data Register */
00345 
00346 /*USART0 left for compatibility*/
00347 #define UCSR0A  (*(volatile unsigned char *)0xC0)     /* USART0 Control and Status Register A */
00348 #define UCSR0B  (*(volatile unsigned char *)0xC1)     /* USART0 Control and Status Register B */
00349 #define UCSR0C  (*(volatile unsigned char *)0xC2)     /* USART0 Control and Status Register C */
00350 #define UBRR0   (*(volatile unsigned int *)0xC4)      /* USART0 Baud Rate Register  */
00351 #define UBRR0L  (*(volatile unsigned char *)0xC4)     /* USART0 Baud Rate Register Low */
00352 #define UBRR0H  (*(volatile unsigned char *)0xC5)     /* USART0 Baud Rate Register High */
00353 #define UDR0    (*(volatile unsigned char *)0xC6)     /* USART0 I/O Data Register */
00354 
00355 /*EUSART */
00356 #define EUCSRA  (*(volatile unsigned char *)0xC8)     /* EUSART Control and Status Register A */
00357 #define EUCSRB  (*(volatile unsigned char *)0xC9)     /* EUSART Control and Status Register B */
00358 #define EUCSRC  (*(volatile unsigned char *)0xCA)     /* EUSART Control and Status Register C */
00359 #define MUBRR   (*(volatile unsigned int *)0xCC)     /* EUSART Max manchester receiver counter */
00360 #define MUBRRL  (*(volatile unsigned char *)0xCC)     /* EUSART Max manchester receiver counter */
00361 #define MUBRRH   (*(volatile unsigned char *)0xCD)     /* EUSART Max manchester receiver counter */
00362 #define EUDR    (*(volatile unsigned char *)0xCE)     /* USART0 I/O Data Register */
00363 
00364 #define PSOC0  (*(volatile unsigned char *)0xD0)     /* PSC 0 Synchro & Output Configuration */
00365 #define OCR0SA  (*(volatile unsigned int *)0xD2)     /* PSC 0 Output Compare Register SA */
00366 #define OCR0SAL  (*(volatile unsigned char *)0xD2)     /* PSC 0 Output Compare Register SA */
00367 #define OCR0SAH  (*(volatile unsigned char *)0xD3)     /* PSC 0 Output Compare Register SA */
00368 
00369 #define OCR0RA  (*(volatile unsigned int *)0xD4)     /* PSC 0 Output Compare Register RA*/
00370 #define OCR0RAL  (*(volatile unsigned char *)0xD4)     /* PSC 0 Output Compare Register RA*/
00371 #define OCR0RAH  (*(volatile unsigned char *)0xD5)     /* PSC 0 Output Compare Register RA*/
00372 
00373 #define OCR0SB   (*(volatile unsigned int *)0xD6)     /* PSC 0 Output Compare Register SB */
00374 #define OCR0SBL   (*(volatile unsigned char *)0xD6)     /* PSC 0 Output Compare Register SB */
00375 #define OCR0SBH   (*(volatile unsigned char *)0xD7)     /* PSC 0 Output Compare Register SB */
00376 
00377 #define OCR0RB  (*(volatile unsigned int*)0xD8)     /* PSC 0 Output Compare Register RB */
00378 #define OCR0RBL  (*(volatile unsigned char*)0xD8)     /* PSC 0 Output Compare Register RB */
00379 #define OCR0RBH  (*(volatile unsigned char*)0xD9)     /* PSC 0 Output Compare Register RB */
00380 
00381 #define PCNF0    (*(volatile unsigned char *)0xDA)     /* PSC 0 Configuration Register */
00382 #define PCTL0  (*(volatile unsigned char *)0xDB)     /* PSC 0 Control Register */
00383 #define PFRC0A   (*(volatile unsigned char *)0xDC)     /* PSC 0 Input A Control Register */
00384 #define PFRC0B  (*(volatile unsigned char *)0xDD)     /* PSC 0 Input B Control Register */
00385 #define PICR0    (*(volatile unsigned int *)0xDE)     /* PSC 0 Input Capture Register */
00386 
00387 
00388 #define PSOC1  (*(volatile unsigned char *)0xE0)     /* PSC 1 Synchro & Output Configuration */
00389 #define OCR1SA  (*(volatile unsigned int *)0xE2)     /* PSC 1 Output Compare Register SA */
00390 #define OCR1SAL  (*(volatile unsigned char *)0xE2)     /* PSC 1 Output Compare Register SA */
00391 #define OCR1SAH  (*(volatile unsigned char *)0xE3)     /* PSC 1 Output Compare Register SA */
00392 
00393 #define OCR1RA  (*(volatile unsigned int *)0xE4)     /* PSC 1 Output Compare Register RA*/
00394 #define OCR1RAL  (*(volatile unsigned char *)0xE4)     /* PSC 1 Output Compare Register RA*/
00395 #define OCR1RAH  (*(volatile unsigned char *)0xE5)     /* PSC 1 Output Compare Register RA*/
00396 
00397 #define OCR1SB   (*(volatile unsigned int *)0xE6)     /* PSC 1 Output Compare Register SB */
00398 #define OCR1SBL   (*(volatile unsigned char *)0xE6)     /* PSC 1 Output Compare Register SB */
00399 #define OCR1SBH   (*(volatile unsigned char *)0xE7)     /* PSC 1 Output Compare Register SB */
00400 
00401 #define OCR1RB  (*(volatile unsigned int*)0xE8)     /* PSC 1 Output Compare Register RB */
00402 #define OCR1RBL  (*(volatile unsigned char*)0xE8)     /* PSC 1 Output Compare Register RB */
00403 #define OCR1RBH  (*(volatile unsigned char*)0xE9)     /* PSC 1 Output Compare Register RB */
00404 
00405 #define PCNF1    (*(volatile unsigned char *)0xEA)     /* PSC 1 Configuration Register */
00406 #define PCTL1  (*(volatile unsigned char *)0xEB)     /* PSC 1 Control Register */
00407 #define PFRC1A   (*(volatile unsigned char *)0xEC)     /* PSC 1 Input A Control Register */
00408 #define PFRC1B  (*(volatile unsigned char *)0xED)     /* PSC 1 Input B Control Register */
00409 #define PICR1    (*(volatile unsigned int *)0xEE)     /* PSC 1 Input Capture Register */
00410 
00411 
00412 #define PSOC2  (*(volatile unsigned char *)0xF0)     /* PSC 2 Synchro & Output Configuration */
00413 #define OCR2SA  (*(volatile unsigned int *)0xF2)     /* PSC 2 Output Compare Register SA */
00414 #define OCR2SAL  (*(volatile unsigned char *)0xF2)     /* PSC 2 Output Compare Register SA */
00415 #define OCR2SAH  (*(volatile unsigned char *)0xF3)     /* PSC 2 Output Compare Register SA */
00416 
00417 #define OCR2RA  (*(volatile unsigned int *)0xF4)     /* PSC 2 Output Compare Register RA*/
00418 #define OCR2RAL  (*(volatile unsigned char *)0xF4)     /* PSC 2 Output Compare Register RA*/
00419 #define OCR2RAH  (*(volatile unsigned char *)0xF5)     /* PSC 2 Output Compare Register RA*/
00420 
00421 #define OCR2SB   (*(volatile unsigned int *)0xF6)     /* PSC 2 Output Compare Register SB */
00422 #define OCR2SBL   (*(volatile unsigned char *)0xF6)     /* PSC 2 Output Compare Register SB */
00423 #define OCR2SBH   (*(volatile unsigned char *)0xF7)     /* PSC 2 Output Compare Register SB */
00424 
00425 #define OCR2RB  (*(volatile unsigned int*)0xF8)     /* PSC 2 Output Compare Register RB */
00426 #define OCR2RBL  (*(volatile unsigned char*)0xF8)     /* PSC 2 Output Compare Register RB */
00427 #define OCR2RBH  (*(volatile unsigned char*)0xF9)     /* PSC 2 Output Compare Register RB */
00428 
00429 #define PCNF2    (*(volatile unsigned char *)0xFA)     /* PSC 2 Configuration Register */
00430 #define PCTL2  (*(volatile unsigned char *)0xFB)     /* PSC 2 Control Register */
00431 #define PFRC2A   (*(volatile unsigned char *)0xFC)     /* PSC 2 Input A Control Register */
00432 #define PFRC2B  (*(volatile unsigned char *)0xFD)     /* PSC 2 Input B Control Register */
00433 #define PICR2    (*(volatile unsigned int *)0xFE)     /* PSC 2 Input Capture Register */
00434 
00435 
00436 /*==============================*/
00437 /* Interrupt Vector Definitions */
00438 /*==============================*/
00439 
00440 #define    RESET_vect           0
00441 #define    PSC2_CAPT_vect       1
00442 #define    PSC2EC_vect          2
00443 #define    PSC1_CAPT_vect       3
00444 #define    PSC1EC_vect          4
00445 #define    PSC0_CAPT_vect       5
00446 #define    PSC0EC_vect          6
00447 #define    ANACOMP_0_vect       7
00448 #define    ANACOMP_1_vect       8
00449 #define    ANACOMP_2_vect       9
00450 #define    INT0_vect            10
00451 #define    TIMER1_CAPT_vect     11
00452 #define    TIMER1_COMPA_vect    12
00453 #define    TIMER1_COMPB_vect    13
00454 #define    TIMER1_OVF_vect      15
00455 #define    TIMER0_COMPA_vect    16
00456 #define    TIMER0_OVF_vect      17
00457 #define    ADC_vect             18
00458 #define    INT1_vect            19
00459 #define    SPI_STC_vect         20
00460 #define    USART_RXC_vect       21
00461 #define    USART_UDRE_vect      22
00462 #define    USART_TXC_vect       23
00463 #define    INT2_vect            24
00464 #define    WDT_vect             25
00465 #define    EE_RDY_vect          26
00466 #define    TIMER0_COMPB_vect    27
00467 #define    INT3_vect            28
00468 #define    SPM_READY_vect       31
00469 
00470 #endif /* _ICC_*/
00471 
00472 
00473 
00474 /*==========================*/
00475 /* Bit Position Definitions */
00476 /*==========================*/
00477 
00478 /* PINB : Input Pins, Port B */
00479 #define    PINB7    7
00480 #define    PINB6    6
00481 #define    PINB5    5
00482 #define    PINB4    4
00483 #define    PINB3    3
00484 #define    PINB2    2
00485 #define    PINB1    1
00486 #define    PINB0    0
00487 
00488 /* DDRB : Data Direction Register, Port B */
00489 #define    DDB7     7
00490 #define    DDB6     6
00491 #define    DDB5     5
00492 #define    DDB4     4
00493 #define    DDB3     3
00494 #define    DDB2     2
00495 #define    DDB1     1
00496 #define    DDB0     0
00497 
00498 /* PORTB : Data Register, Port B */
00499 #define    PB7      7
00500 #define    PB6      6
00501 #define    PB5      5
00502 #define    PB4      4
00503 #define    PB3      3
00504 #define    PB2      2
00505 #define    PB1      1
00506 #define    PB0      0
00507 
00508 /* PORTB : Data Register, Port B */
00509 #define    PORTB7   7
00510 #define    PORTB6   6
00511 #define    PORTB5   5
00512 #define    PORTB4   4
00513 #define    PORTB3   3
00514 #define    PORTB2   2
00515 #define    PORTB1   1
00516 #define    PORTB0   0
00517 
00518 /* PINC : Input Pins, Port C */
00519 #define    PINC7    7
00520 #define    PINC6    6
00521 #define    PINC5    5
00522 #define    PINC4    4
00523 #define    PINC3    3
00524 #define    PINC2    2
00525 #define    PINC1    1
00526 #define    PINC0    0
00527 
00528 /* DDRC : Data Direction Register, Port C */
00529 #define    DDC7     7
00530 #define    DDC6     6
00531 #define    DDC5     5
00532 #define    DDC4     4
00533 #define    DDC3     3
00534 #define    DDC2     2
00535 #define    DDC1     1
00536 #define    DDC0     0
00537 
00538 /* PORTC : Data Register, Port C */
00539 #define    PC7      7
00540 #define    PC6      6
00541 #define    PC5      5
00542 #define    PC4      4
00543 #define    PC3      3
00544 #define    PC2      2
00545 #define    PC1      1
00546 #define    PC0      0
00547 
00548 /* PORTC : Data Register, Port C */
00549 #define    PORTC7   7
00550 #define    PORTC6   6
00551 #define    PORTC5   5
00552 #define    PORTC4   4
00553 #define    PORTC3   3
00554 #define    PORTC2   2
00555 #define    PORTC1   1
00556 #define    PORTC0   0
00557 
00558 /* PIND : Input Pins, Port D */
00559 #define    PIND7    7
00560 #define    PIND6    6
00561 #define    PIND5    5
00562 #define    PIND4    4
00563 #define    PIND3    3
00564 #define    PIND2    2
00565 #define    PIND1    1
00566 #define    PIND0    0
00567 
00568 /* DDRD : Data Direction Register, Port D */
00569 #define    DDD7     7
00570 #define    DDD6     6
00571 #define    DDD5     5
00572 #define    DDD4     4
00573 #define    DDD3     3
00574 #define    DDD2     2
00575 #define    DDD1     1
00576 #define    DDD0     0
00577 
00578 /* PORTD : Data Register, Port D */
00579 #define    PD7      7
00580 #define    PD6      6
00581 #define    PD5      5
00582 #define    PD4      4
00583 #define    PD3      3
00584 #define    PD2      2
00585 #define    PD1      1
00586 #define    PD0      0
00587 
00588 /* PORTD : Data Register, Port D */
00589 #define    PORTD7   7
00590 #define    PORTD6   6
00591 #define    PORTD5   5
00592 #define    PORTD4   4
00593 #define    PORTD3   3
00594 #define    PORTD2   2
00595 #define    PORTD1   1
00596 #define    PORTD0   0
00597 
00598 /* PINE : Input Pins, Port E */
00599 #define    PINE7    7
00600 #define    PINE6    6
00601 #define    PINE5    5
00602 #define    PINE4    4
00603 #define    PINE3    3
00604 #define    PINE2    2
00605 #define    PINE1    1
00606 #define    PINE0    0
00607 
00608 /* DDRE : Data Direction Register, Port E */
00609 #define    DDE7     7
00610 #define    DDE6     6
00611 #define    DDE5     5
00612 #define    DDE4     4
00613 #define    DDE3     3
00614 #define    DDE2     2
00615 #define    DDE1     1
00616 #define    DDE0     0
00617 
00618 /* PORTE : Data Register, Port E */
00619 #define    PE7      7
00620 #define    PE6      6
00621 #define    PE5      5
00622 #define    PE4      4
00623 #define    PE3      3
00624 #define    PE2      2
00625 #define    PE1      1
00626 #define    PE0      0
00627 
00628 /* PORTE : Data Register, Port E */
00629 #define    PORTE7   7
00630 #define    PORTE6   6
00631 #define    PORTE5   5
00632 #define    PORTE4   4
00633 #define    PORTE3   3
00634 #define    PORTE2   2
00635 #define    PORTE1   1
00636 #define    PORTE0   0
00637 
00638 /* PINF : Input Pins, Port F */
00639 #define    PINF7    7
00640 #define    PINF6    6
00641 #define    PINF5    5
00642 #define    PINF4    4
00643 #define    PINF3    3
00644 #define    PINF2    2
00645 #define    PINF1    1
00646 #define    PINF0    0
00647 
00648 /* TIFR0 : Timer/Counter Interrupt Flag Register 0 */
00649 #define    OCF0B    2
00650 #define    OCF0A    1
00651 #define    TOV0     0
00652 
00653 /* TIFR1 : Timer/Counter Interrupt Flag Register 1 */
00654 #define    ICF1      5
00655 #define    OCF1B     2
00656 #define    OCF1A     1
00657 #define    TOV1      0
00658 
00659 /* GPIOR1  */
00660 #define    GPIOR17   7
00661 #define    GPIOR16   6
00662 #define    GPIOR15   5
00663 #define    GPIOR14   4
00664 #define    GPIOR13   3
00665 #define    GPIOR12   2
00666 #define    GPIOR11   1
00667 #define    GPIOR10   0
00668 
00669 /* GPIOR2  */
00670 #define    GPIOR27   7
00671 #define    GPIOR26   6
00672 #define    GPIOR25   5
00673 #define    GPIOR24   4
00674 #define    GPIOR23   3
00675 #define    GPIOR22   2
00676 #define    GPIOR21   1
00677 #define    GPIOR20   0
00678 
00679 /* GPIOR3  */
00680 #define    GPIOR37   7
00681 #define    GPIOR36   6
00682 #define    GPIOR35   5
00683 #define    GPIOR34   4
00684 #define    GPIOR33   3
00685 #define    GPIOR32   2
00686 #define    GPIOR31   1
00687 #define    GPIOR30   0
00688 
00689 /* EIFR : External Interrupt Flag Register */
00690 #define    INTF3     3
00691 #define    INTF2     2
00692 #define    INTF1     1
00693 #define    INTF0     0
00694 
00695 /* EIMSK : External Interrupt Mask Register */
00696 #define    INT3      3
00697 #define    INT2      2
00698 #define    INT1      1
00699 #define    INT0      0
00700 
00701 /* GPIOR0  */
00702 #define    GPIOR07   7
00703 #define    GPIOR06   6
00704 #define    GPIOR05   5
00705 #define    GPIOR04   4
00706 #define    GPIOR03   3
00707 #define    GPIOR02   2
00708 #define    GPIOR01   1
00709 #define    GPIOR00   0
00710 
00711 /* EECR : EEPROM Control Register */
00712 #define    EERIE     3
00713 #define    EEMWE     2
00714 #define    EEWE      1
00715 #define    EERE      0
00716 
00717 /* GTCCR : General Timer Control Register */
00718 #define    TSM       7
00719 #define    ICPSEL1   6
00720 #define    PSRSYNC   0
00721 
00722 /* TCCR0A : Timer/Counter 0 Control Register A */
00723 #define    COM0A1    7
00724 #define    COM0A0    6
00725 #define    COM0B1    5
00726 #define    COM0B0    4
00727 
00728 #define    WGM01     1
00729 #define    WGM00     0
00730 
00731 /* TCCR0B : Timer/Counter 0 Control Register B */
00732 #define    FOC0A     7
00733 #define    FOC0B     6
00734 #define    WGM02     3
00735 #define    CS02      2
00736 #define    CS01      1
00737 #define    CS00      0
00738 
00739 /* PLLCSR */
00740 #define    PLLF      2
00741 #define    PLLE      1
00742 #define    PLLOCK    0
00743 #define    PLOCK     0
00744 
00745 /* SPCR : SPI Control Register */
00746 #define    SPIE      7
00747 #define    SPE       6
00748 #define    DORD      5
00749 #define    MSTR      4
00750 #define    CPOL      3
00751 #define    CPHA      2
00752 #define    SPR1      1
00753 #define    SPR0      0
00754 
00755 /* SPSR : SPI Status Register */
00756 #define    SPIF      7
00757 #define    WCOL      6
00758 #define    SPI2X     0
00759 
00760 /* ACSR : Analog Comparator Control and Status Register */
00761 #define    ACCKDIV   7
00762 #define    AC2IF     6
00763 #define    AC1IF     5
00764 #define    AC0IF     4
00765 #define    AC2O      2
00766 #define    AC1O      1
00767 #define    AC0O      0
00768 
00769 /* SMCR : Sleep Mode Control Register */
00770 #define    SM2       3
00771 #define    SM1       2
00772 #define    SM0       1
00773 #define    SE        0
00774 
00775 /* MCUSR : MCU general Status Register */
00776 #define    WDRF      3
00777 #define    BORF      2
00778 #define    EXTRF     1
00779 #define    PORF      0
00780 
00781 /* MCUCR : MCU general Control Register */
00782 #define    SPIPS     7
00783 #define    PUD       4
00784 #define    IVSEL     1
00785 #define    IVCE      0
00786 
00787 /* SPMCR : Store Program Memory Control and Status Register */
00788 #define    SPMIE     7
00789 #define    RWWSB     6
00790 #define    RWWSRE    4
00791 #define    BLBSET    3
00792 #define    PGWRT     2
00793 #define    PGERS     1
00794 #define    SPMEN     0
00795 
00796 /* SPH : Stack Pointer High */
00797 #define    SP15      7
00798 #define    SP14      6
00799 #define    SP13      5
00800 #define    SP12      4
00801 #define    SP11      3
00802 #define    SP10      2
00803 #define    SP9       1
00804 #define    SP8       0
00805 
00806 /* SPL : Stack Pointer Low */
00807 #define    SP7       7
00808 #define    SP6       6
00809 #define    SP5       5
00810 #define    SP4       4
00811 #define    SP3       3
00812 #define    SP2       2
00813 #define    SP1       1
00814 #define    SP0       0
00815 
00816 /* WTDCSR : Watchdog Timer Control Register */
00817 #define    WDIF      7
00818 #define    WDIE      6
00819 #define    WDP3      5
00820 #define    WDCE      4
00821 #define    WDE       3
00822 #define    WDP2      2
00823 #define    WDP1      1
00824 #define    WDP0      0
00825 
00826 /* CLKPR : Source Clock Prescaler Register */
00827 #define    CKLPCE    7
00828 #define    CKLPS3    3
00829 #define    CKLPS2    2
00830 #define    CKLPS1    1
00831 #define    CKLPS0    0
00832 
00833 /* PRR  */
00834 #define    PRPSC2    7
00835 #define    PRPSC1    6
00836 #define    PRPSC0    5
00837 #define    PRTIM1    4
00838 #define    PRTIM0    3
00839 #define    PRSPI     2
00840 #define    PRUSART   1
00841 #define    PRADC     0
00842 
00843 /* OSCAL  */
00844 #define    CAL6      6
00845 #define    CAL5      5
00846 #define    CAL4      4
00847 #define    CAL3      3
00848 #define    CAL2      2
00849 #define    CAL1      1
00850 #define    CAL0      0
00851 
00852 /* EICRA  */
00853 #define    ISC31     7
00854 #define    ISC30     6
00855 #define    ISC21     5
00856 #define    ISC20     4
00857 #define    ISC11     3
00858 #define    ISC10     2
00859 #define    ISC01     1
00860 #define    ISC00     0
00861 
00862 /* TIMSK0 : Timer Interrupt Mask Register0 */
00863 #define    OCIE0B    2
00864 #define    OCIE0A    1
00865 #define    TOIE0     0
00866 
00867 /* TIMSK1 : Timer Interrupt Mask Register1 */
00868 #define    ICIE1     5
00869 #define    OCIE1B    2
00870 #define    OCIE1A    1
00871 #define    TOIE1     0
00872 
00873 /* AMP0CSR  */
00874 #define    AMP0EN    7
00875 #define    AMP0IS    6
00876 #define    AMP0G1    5
00877 #define    AMP0G0    4
00878 #define    AMP0TS2   2
00879 #define    AMP0TS1   1
00880 #define    AMP0TS0   0
00881 
00882 /* AMP1CSR  */
00883 #define    AMP1EN    7
00884 #define    AMP1IS    6
00885 #define    AMP1G1    5
00886 #define    AMP1G0    4
00887 #define    AMP1TS2   2
00888 #define    AMP1TS1   1
00889 #define    AMP1TS0   0
00890 
00891 /* ADCSRA : ADC Control and Status Register A*/
00892 #define    ADEN      7
00893 #define    ADSC      6
00894 #define    ADATE     5
00895 #define    ADIF      4
00896 #define    ADIE      3
00897 #define    ADPS2     2
00898 #define    ADPS1     1
00899 #define    ADPS0     0
00900 
00901 /* ADCSRB : ADC Control and Status Register B*/
00902 #define    ADHSM     7
00903 #define    ADASCR    4
00904 #define    ADST3     3
00905 #define    ADST2     2
00906 #define    ADST1     1
00907 #define    ADST0     0
00908 
00909 /* ADMUX : ADC Multiplexer Selection Register */
00910 #define    REFS1     7
00911 #define    REFS0     6
00912 #define    ADLAR     5
00913 #define    MUX3      3
00914 #define    MUX2      2
00915 #define    MUX1      1
00916 #define    MUX0      0
00917 
00918 /* DIDR0 */
00919 #define    ADC7D     7
00920 #define    ADC6D     6
00921 #define    ADC5D     5
00922 #define    ADC4D     4
00923 #define    ADC3D     3
00924 #define    ADC2D     2
00925 #define    ADC1D     1
00926 #define    ADC0D     0
00927 
00928 /* DIDR1 */
00929 #define    ACMP0D    5
00930 #define    AMP0PD    4
00931 #define    AMP0ND    3
00932 #define    ADC10D    2
00933 #define    ACMP1D    2
00934 #define    ADC9D     1
00935 #define    AMP1PD    1
00936 #define    ADC8D     0
00937 #define    AMP1ND    0
00938 
00939 /* TCCR1A : Timer/Counter 1 Control Register A */
00940 #define    COM1A1    7
00941 #define    COM1A0    6
00942 #define    COM1B1    5
00943 #define    COM1B0    4
00944 #define    WGM11     1
00945 #define    WGM10     0
00946 
00947 /* TCCR1B : Timer/Counter 1 Control Register B */
00948 #define    ICNC1     7
00949 #define    ICES1     6
00950 #define    WGM13     4
00951 #define    WGM12     3
00952 #define    CS12      2
00953 #define    CS11      1
00954 #define    CS10      0
00955 
00956 /* TCCR1C : Timer/Counter 1 Control Register C */
00957 #define    FOC1A     7
00958 #define    FOC1B     6
00959 
00960 /* PIFR0 : PSC 0 Interrupt Flag Register */
00961 #define    PSEI0     5
00962 #define    PEV0B     4
00963 #define    PEV0A     3
00964 #define    PRN01     2
00965 #define    PRN00     1
00966 #define    PEOP0     0
00967 
00968 /* PIM0 : PSC 0 Interrupt Mask Register */
00969 #define    PSEIE0    5
00970 #define    PEVE0B    4
00971 #define    PEVE0A    3
00972 #define    PEOPE0    0
00973 
00974 /* PIFR1 : PSC 1 Interrupt Flag Register */
00975 #define    PSEI1     5
00976 #define    PEV1B     4
00977 #define    PEV1A     3
00978 #define    PRN11     2
00979 #define    PRN10     1
00980 #define    PEOP1     0
00981 
00982 /* PIM1 : PSC 1 Interrupt Mask Register */
00983 #define    PSEIE1    5
00984 #define    PEVE1B    4
00985 #define    PEVE1A    3
00986 #define    PEOPE1    0
00987 
00988 /* PIFR2 : PSC 2 Interrupt Flag Register */
00989 #define    PSEI2     5
00990 #define    PEV2B     4
00991 #define    PEV2A     3
00992 #define    PRN21     2
00993 #define    PRN20     1
00994 #define    PEOP2     0
00995 
00996 /* PIM2 : PSC 2 Interrupt Mask Register */
00997 #define    PSEIE1    5
00998 #define    PEVE2B    4
00999 #define    PEVE2A    3
01000 #define    PEOPE2    0
01001 
01002 /* DACON: DAC Control and Status Register */
01003 #define    DAATE     7
01004 #define    DATS2     6
01005 #define    DATS1     5
01006 #define    DATS0     4
01007 #define    DALA      2
01008 #define    DAOE      1
01009 #define    DAEN      0
01010 
01011 /* AC0CON : Analog comparator 0 Control and Status Register */
01012 #define    AC0EN     7
01013 #define    AC0IE     6
01014 #define    AC0IS1    5
01015 #define    AC0IS0    4
01016 #define    AC0M2     2
01017 #define    AC0M1     1
01018 #define    AC0M0     0
01019 
01020 /* AC1CON : Analog comparator 1 Control and Status Register */
01021 #define    AC1EN     7
01022 #define    AC1IE     6
01023 #define    AC1IS1    5
01024 #define    AC1IS0    4
01025 #define    AC1ICE    3
01026 #define    AC1M2     2
01027 #define    AC1M1     1
01028 #define    AC1M0     0
01029 
01030 /* AC2CON : Analog comparator 2 Control and Status Register */
01031 #define    AC2EN     7
01032 #define    AC2IE     6
01033 #define    AC2IS1    5
01034 #define    AC2IS0    4
01035 #define    AC2SADE   3
01036 #define    AC2M2     2
01037 #define    AC2M1     1
01038 #define    AC2M0     0
01039 
01040 /* UCSRA : USART Control and Status Register A */
01041 #define    RXC       7
01042 #define    TXC       6
01043 #define    UDRE      5
01044 #define    FE        4
01045 #define    DOR       3
01046 #define    UPE       2
01047 #define    U2X       1
01048 #define    MPCM      0
01049 
01050 /* UCSRB : USART Control and Status Register B */
01051 #define    RXCIE     7
01052 #define    TXCIE     6
01053 #define    UDRIE     5
01054 #define    RXEN      4
01055 #define    TXEN      3
01056 #define    UCSZ2     2
01057 #define    RXB8      1
01058 #define    TXB8      0
01059 
01060 /* UCSRC : USART Control and Status Register C */
01061 #define    UMSEL     6
01062 #define    UPM1      5
01063 #define    UPM0      4
01064 #define    USBS      3
01065 #define    UCSZ1     2
01066 #define    UCSZ0     1
01067 #define    UCPOL     0
01068 
01069 /* USART0 left for compatiblity reason */
01070 /* UCSR0A : USART0 Control and Status Register A */
01071 #define    RXC0      7
01072 #define    TXC0      6
01073 #define    UDRE0     5
01074 #define    FE0       4
01075 #define    DOR0      3
01076 #define    UPE0      2
01077 #define    U2X0      1
01078 #define    MPCM0     0
01079 
01080 /* UCSR0B : USART0 Control and Status Register B */
01081 #define    RXCIE0    7
01082 #define    TXCIE0    6
01083 #define    UDRIE0    5
01084 #define    RXEN0     4
01085 #define    TXEN0     3
01086 #define    UCSZ02    2
01087 #define    RXB80     1
01088 #define    TXB80     0
01089 
01090 /* UCSR0C : USART0 Control and Status Register C */
01091 #define    UMSEL0    6
01092 #define    UPM01     5
01093 #define    UPM00     4
01094 #define    USBS0     3
01095 #define    UCSZ01    2
01096 #define    UCSZ00    1
01097 #define    UCPOL0    0
01098 
01099 /* EUSART */
01100 /* EUCSRA : EUSART Control and Status Register A */
01101 #define    UTxS3     7
01102 #define    UTxS2     6
01103 #define    UTxS1     5
01104 #define    UTxS0     4
01105 #define    URxS3     3
01106 #define    URxS2     2
01107 #define    URxS1     1
01108 #define    URxS0     0
01109 
01110 /* EUCSRB : EUSART Control and Status Register B */
01111 #define    EUSART    4
01112 #define    EUSBS     3
01113 #define    EMCH      1
01114 #define    BODR      0
01115 
01116 /* EUCSRC : EUSART Control and Status Register C */
01117 #define    FEM       3
01118 #define    F1617     2
01119 #define    STP1      1
01120 #define    STP0      0
01121 
01122 /* PSOC0 : PSC 0 Synchro and Output Configuration */
01123 #define    PSYNC01   5
01124 #define    PSYNC00   4
01125 #define    POEN0B    2
01126 #define    POEN0A    0
01127 
01128 /* PCNF0 : PSC 0 Configuration */
01129 #define    PFIFTY0   7
01130 #define    PALOCK0   6
01131 #define    PLOCK0    5
01132 #define    PMODE01   4
01133 #define    PMODE00   3
01134 #define    POP0      2
01135 #define    PCLKSEL0  1
01136 
01137 /* PCTL0 : PSC 0 Control */
01138 #define    PPRE01    7
01139 #define    PPRE00    6
01140 #define    PBFM0     5
01141 #define    PAOC0B    4
01142 #define    PAOC0A    3
01143 #define    PARUN0    2
01144 #define    PCCYC0    1
01145 #define    PRUN0     0
01146 
01147 /* PFRC0A : PSC 0 Input A Control Register */
01148 #define    PCAPE0A   7
01149 #define    PISEL0A   6
01150 #define    PELEV0A   5
01151 #define    PFLTE0A   4
01152 #define    PRFM0A3   3
01153 #define    PRFM0A2   2
01154 #define    PRFM0A1   1
01155 #define    PRFM0A0   0
01156 
01157 /* PFRC0B : PSC 0 Input B Control Register */
01158 #define    PCAPE0B   7
01159 #define    PISEL0B   6
01160 #define    PELEV0B   5
01161 #define    PFLTE0B   4
01162 #define    PRFM0B3   3
01163 #define    PRFM0B2   2
01164 #define    PRFM0B1   1
01165 #define    PRFM0B0   0
01166 
01167 /* PSOC1 : PSC 1 Synchro and Output Configuration */
01168 #define    PSYNC11   5
01169 #define    PSYNC10   4
01170 #define    POEN1B    2
01171 #define    POEN1A    0
01172 
01173 /* PCNF1 : PSC 1 Configuration */
01174 #define    PFIFTY1   7
01175 #define    PALOCK1   6
01176 #define    PLOCK1    5
01177 #define    PMODE11   4
01178 #define    PMODE10   3
01179 #define    POP1      2
01180 #define    PCLKSEL1  1
01181 
01182 /* PCTL1 : PSC 1 Control */
01183 #define    PPRE11    7
01184 #define    PPRE10    6
01185 #define    PBFM1     5
01186 #define    PAOC1B    4
01187 #define    PAOC1A    3
01188 #define    PARUN1    2
01189 #define    PCCYC1    1
01190 #define    PRUN1     0
01191 
01192 /* PFRC1A : PSC 1 Input A Control Register */
01193 #define    PCAPE1A   7
01194 #define    PISEL1A   6
01195 #define    PELEV1A   5
01196 #define    PFLTE1A   4
01197 #define    PRFM1A3   3
01198 #define    PRFM1A2   2
01199 #define    PRFM1A1   1
01200 #define    PRFM1A0   0
01201 
01202 /* PFRC1B : PSC 1 Input B Control Register */
01203 #define    PCAPE1B   7
01204 #define    PISEL1B   6
01205 #define    PELEV1B   5
01206 #define    PFLTE1B   4
01207 #define    PRFM1B3   3
01208 #define    PRFM1B2   2
01209 #define    PRFM1B1   1
01210 #define    PRFM1B0   0
01211 
01212 /* PSOC2 : PSC 2 Synchro and Output Configuration */
01213 #define    POS23     7
01214 #define    POS22     6
01215 #define    PSYNC21   5
01216 #define    PSYNC20   4
01217 #define    POEN2D    3
01218 #define    POEN2B    2
01219 #define    POEN2C    1
01220 #define    POEN2A    0
01221 
01222 /* POM2 : PSC 2 Output Matrix */
01223 #define    POMV2B3   7
01224 #define    POMV2B2   6
01225 #define    POMV2B1   5
01226 #define    POMV2B0   4
01227 #define    POMV2A3   3
01228 #define    POMV2A2   2
01229 #define    POMV2A1   1
01230 #define    POMV2A0   0
01231 
01232 /* PCNF2 : PSC 2 Configuration */
01233 #define    PFIFTY2   7
01234 #define    PALOCK2   6
01235 #define    PLOCK2    5
01236 #define    PMODE21   4
01237 #define    PMODE20   3
01238 #define    POP2      2
01239 #define    PCLKSEL2  1
01240 #define    POME2     0
01241 
01242 /* PCTL2 : PSC 2 Control */
01243 #define    PPRE21    7
01244 #define    PPRE20    6
01245 #define    PBFM2     5
01246 #define    PAOC2B    4
01247 #define    PAOC2A    3
01248 #define    PARUN2    2
01249 #define    PCCYC2    1
01250 #define    PRUN2     0
01251 
01252 /* PFRC2A : PSC 2 Input A Control Register */
01253 #define    PCAPE2A   7
01254 #define    PISEL2A   6
01255 #define    PELEV2A   5
01256 #define    PFLTE2A   4
01257 #define    PRFM2A3   3
01258 #define    PRFM2A2   2
01259 #define    PRFM2A1   1
01260 #define    PRFM2A0   0
01261 
01262 /* PFRC2B : PSC 2 Input B Control Register */
01263 #define    PCAPE2B   7
01264 #define    PISEL2B   6
01265 #define    PELEV2B   5
01266 #define    PFLTE2B   4
01267 #define    PRFM2B3   3
01268 #define    PRFM2B2   2
01269 #define    PRFM2B1   1
01270 #define    PRFM2B0   0
01271 
01272 /* Pointer definition */
01273 #define    XL     r26
01274 #define    XH     r27
01275 #define    YL     r28
01276 #define    YH     r29
01277 #define    ZL     r30
01278 #define    ZH     r31
01279 
01280 #endif  /* _MCU_H*/