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Defines |
| #define | Disable_psc0_autolock_mode() (PCNF0 &= ~(1<<PALOCK0) ) |
| | The update will be procced according to PLOCK0 bit.
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| #define | Disable_psc0_fifty_percent_mode() (PCNF0 &= ~(1<<PFIFTY0) ) |
| | OCR0R/SAH/L and OCR0R/SBH/L are fully independant.
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| #define | Enable_psc0_autolock_mode() (PCNF0 |= (1<<PALOCK0) ) |
| | OCR0R/SAH/L and OCR0R/SBH/L can be written without disturbing the PSC cycle. The update of these registers will be proceed at the end of the PSC cycle if the OCR0RB has been last written.
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| #define | Enable_psc0_fifty_percent_mode() (PCNF0 |= (1<<PFIFTY0) ) |
| | PSC0 is in 50% mode: Only OCR0RBH/L and OCR0SBH/L are used. They are duplicated in OCR0R/SAH/L during the update of OCR0BH/L.
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| #define | Lock_psc0_compare_values() (PCNF0 |= (1<<PLOCK0) ) |
| | Take care that the lock is active only if you have disabled the autolock mode.
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| #define | Update_psc0_compare_values() (PCNF0 &= ~(1<<PLOCK0) ) |
| | The compare registers will be updated with the content of OCR0ARH/L and OCR0BRH.
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