PSC0 Clock Selection
[PSC0 Clock Control]

Collaboration diagram for PSC0 Clock Selection:

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Detailed Description

PSC0 Clock Selection.

Defines
#define	Psc0_use_32_mega_pll_clock()
	Start the PLL at 32MHz and connect it to PSC0.
#define	Psc0_use_64_mega_pll_clock()
	Start the PLL at 64MHz and connect it to PSC0.
#define	Psc0_use_io_clock()   (PCNF0 &= ~(1<<PCLKSEL0) )
	Connect the PSC0 input clock to the I/O clock.
#define	Psc0_use_pll_clock()   (PCNF0 |= (1<<PCLKSEL0) )
	Connect the PSC0 input clock to the PLL.

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Define Documentation

 

#define Psc0_use_32_mega_pll_clock

(

)

Value:

(Start_pll_32_mega(),                                               \
           Wait_pll_ready(),                                                  \
           Psc0_use_pll_clock() )

Start the PLL at 32MHz and connect it to PSC0.

Definition at line 79 of file psc_drv.h.

 

#define Psc0_use_64_mega_pll_clock

(

)

Value:

(Start_pll_64_mega(),                                               \
           Wait_pll_ready(),                                                  \
           Psc0_use_pll_clock() )

Start the PLL at 64MHz and connect it to PSC0.

Definition at line 74 of file psc_drv.h.

 

#define Psc0_use_io_clock

(

)

(PCNF0 &= ~(1<<PCLKSEL0) )

Connect the PSC0 input clock to the I/O clock.

Definition at line 72 of file psc_drv.h.

 

#define Psc0_use_pll_clock

(

)

(PCNF0 |= (1<<PCLKSEL0) )

Connect the PSC0 input clock to the PLL.

Definition at line 70 of file psc_drv.h.

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