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# PWM.c

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    00001 /* This file has been prepared for Doxygen automatic documentation generation.*/
    00029 #include <ioavr.h>
    00030
    00031 #include "enums.h"
    00032
    00033 #include "main.h"
    00034 #include "PWM.h"
    00035 #include "time.h"
    00036
    00037
    00038 //******************************************************************************
    00039 // Functions
    00040 //******************************************************************************
    00044 void PWM_Stop(void)
    00045 {
    00046         OCR1B = 0;  // Reset compare level.
    00047         PLLCSR = 0; // Disable PLL, switch to synchronous CLK mode.
    00048         TCCR1A = 0; // Set normal port operation, disable PWM modes.
    00049         TCCR1B = 0; // Stop timer/counter1.
    00050         TCCR1C = 0; // Set normal port operation.
    00051         TCCR1D = 0; // No fault protection, normal waveform.
    00052         OCR1C = 0;  // Reset compare.
    00053         OCR1D = 0;  // Reset compare.
    00054         DT1 = 0;    // No dead time values.
    00055 }
    00056
    00057
    00066 void PWM_Start(void)
    00067 {
    00068         // Clear OC1B on compare match, enable PWM on comparator OCR1B.
    00069         TCCR1A = (1<<COM1B1)|(0<<COM1B0)|(1<<PWM1B);
    00070
    00071         // Non-inverted PWM, T/C stopped.
    00072         TCCR1B = 0;
    00073
    00074         // Copy shadow bits, disconnect OC1D.
    00075         TCCR1C = (TCCR1A & 0xF0);
    00076
    00077         // No fault protection, use phase & frequency correct PWM.
    00078         TCCR1D = (0<<WGM11)|(1<WGM10);
    00079
    00080         // Does not matter -- PWM6 mode not used.
    00081         TCCR1E = 0;
    00082
    00083         // Does not matter -- OC1A is disabled.
    00084         OCR1A = 0;
    00085
    00086         // Set reset compare level. (Offset is used, or JumperCheck() will fail.)
    00087         OCR1B = PWM_OFFSET;
    00088
    00089         // TOP value for PWM, f(PWM) = 64MHz / 255 = 251kHz.
    00090         OCR1C = 0xFF;
    00091
    00092         // Does not matter -- OC1D is disabled.
    00093         OCR1D = 0;
    00094
    00095         // No dead time values.
    00096         DT1 = 0;
    00097
    00098         // Set PWM port pin to output.
    00099         DDRB |= (1<<PB3);
    00100
    00101         // Enable PLL, use full speed mode.
    00102         PLLCSR = (0<<LSM) | (1<<PLLE);
    00103
    00104         // Use general timer and wait 1 ms for PLL lock to settle.
    00105         Time_Set(TIMER_GEN,0,0,1);
    00106         do{
    00107         }while(Time_Left(TIMER_GEN));
    00108
    00109         // Now wait for PLL to lock.
    00110         do{
    00111         }while((PLLCSR & (1<<PLOCK)) == 0);
    00112
    00113         // Use PLL as clock source.
    00114         PLLCSR |= (1<<PCKE);
    00115
    00116         // CLK PCK = 64MHz / 1 = 64MHz.
    00117         TCCR1B |= (0<<CS13)|(0<<CS12)|(0<<CS11)|(1<<CS10);
    00118 }
    00119
    00120
    00126 unsigned char PWM_IncrementDutyCycle(void){
    00127
    00128         if (OCR1B < PWM_MAX) {
    00129                 OCR1B += 1;
    00130                 return(TRUE);
    00131         } else {
    00132                 return(FALSE);
    00133         }
    00134 }
    00135
    00136
    00142 unsigned char PWM_DecrementDutyCycle(void){
    00143
    00144         if (OCR1B > 0)  {
    00145                 OCR1B -= 1;
    00146                 return(TRUE);
    00147         } else {
    00148                 return(FALSE);
    00149         }
    00150 }