GPIO example application for AVR32 using the local bus interface. More...
#include "compiler.h"#include "preprocessor.h"#include "board.h"#include "pm.h"#include "gpio.h"Go to the source code of this file.
Defines | |
| #define | INSERT_GPIO_LOCAL_TGL_GPIO_PIN(idx, pin) gpio_local_tgl_gpio_pin(pin); |
Pin Configuration | |
| #define | GPIO_PIN_EXAMPLE AVR32_PIN_PA10 |
Functions | |
| static void | fcpu_fpba_configure () |
| int | main (void) |
| This is an example showing how to toggle a GPIO pin at high speed. | |
GPIO example application for AVR32 using the local bus interface.
Definition in file gpio_local_bus_example.c.
| #define GPIO_PIN_EXAMPLE AVR32_PIN_PA10 |
Definition at line 127 of file gpio_local_bus_example.c.
Referenced by main().
| #define INSERT_GPIO_LOCAL_TGL_GPIO_PIN | ( | idx, | ||
| pin | ||||
| ) | gpio_local_tgl_gpio_pin(pin); |
Referenced by main().
| static void fcpu_fpba_configure | ( | ) | [static] |
Definition at line 144 of file gpio_local_bus_example.c.
Referenced by main().
{
#if UC3L
static scif_gclk_opt_t gc_dfllif_ref_opt = { SCIF_GCCTRL_SLOWCLOCK, 0, OFF };
static pcl_freq_param_t pcl_dfll_freq_param =
{
.main_clk_src = PCL_MC_DFLL0,
.cpu_f = EXAMPLE_MCUCLK_HZ,
.pba_f = EXAMPLE_MCUCLK_HZ,
.pbb_f = EXAMPLE_MCUCLK_HZ,
.dfll_f = EXAMPLE_FDFLL_HZ,
.pextra_params = &gc_dfllif_ref_opt
};
// Implementation for UC3L
// Note: on the AT32UC3L-EK board, there is no crystal/external clock connected
// to the OSC0 pinout XIN0/XOUT0. We shall then program the DFLL and switch the
// main clock source to the DFLL.
pcl_configure_clocks(&pcl_dfll_freq_param);
// Note: since it is dynamically computing the appropriate field values of the
// configuration registers from the parameters structure, this function is not
// optimal in terms of code size. For a code size optimal solution, it is better
// to create a new function from pcl_configure_clocks_dfll0() and modify it
// to use preprocessor computation from pre-defined target frequencies.
#elif UC3C
// Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
// Enable the OSC0
scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
// Set the main clock source as being OSC0.
pm_set_mclk_source(PM_CLK_SRC_OSC0);
scif_pll_opt_t opt;
// Setup PLL0 on Osc0, mul=10 ,no divisor, lockcount=16: (16Mhzx8)/2 = 64MHz output
opt.osc = SCIF_OSC0; // Sel Osc0 or Osc1
opt.lockcount = 16; // lockcount in main clock for the PLL wait lock
opt.div = 1; // DIV=1 in the formula
opt.mul = 7; // MUL=7 in the formula
opt.pll_div2 = 1; // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
opt.pll_wbwdisable = 0; //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
opt.pll_freq = 1; // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock
/* Enable PLL0 */
scif_pll_enable(SCIF_PLL0);
/* Wait for PLL0 locked */
scif_wait_for_pll_locked(SCIF_PLL0) ;
// Divide PLL0 output by 2 for CPU, HSB and PBx clocks = 32MHz
pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) 0); // CPU
pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) 0); // HSB
pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) 0); // PBB
pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) 0); // PBA
pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) 0); // PBC
/* Set the main clock source as being PLL0. */
pm_set_mclk_source(PM_CLK_SRC_PLL0);
#else
// Switch the main clock source to Osc0.
pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
// Setup PLL0 on Osc0, mul=10 ,no divisor, lockcount=16: 12Mhzx11 = 132MHz output
pm_pll_setup(&AVR32_PM, 0, // pll.
10, // mul.
1, // div.
0, // osc.
16); // lockcount.
// PLL output VCO frequency is 132MHz.
// We divide it by 2 with the pll_div2=1 to get a main clock at 66MHz.
pm_pll_set_option(&AVR32_PM, 0, // pll.
1, // pll_freq.
1, // pll_div2.
0); // pll_wbwdisable.
// Enable the PLL.
pm_pll_enable(&AVR32_PM, 0);
// Wait until the PLL output is stable.
pm_wait_for_pll0_locked(&AVR32_PM);
// Configure each clock domain to use the main clock divided by 2
// => fCPU = fPBA = fPBB = 33MHz.
pm_cksel(&AVR32_PM,
1, // pbadiv.
0, // pbasel.
1, // pbbdiv.
0, // pbbsel.
1, // hsbdiv=cpudiv
0); // hsbsel=cpusel
// Switch the main clock source to PLL0.
pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
#endif
}
| int main | ( | void | ) |
This is an example showing how to toggle a GPIO pin at high speed.
Definition at line 242 of file gpio_local_bus_example.c.
References fcpu_fpba_configure(), GPIO_PIN_EXAMPLE, and INSERT_GPIO_LOCAL_TGL_GPIO_PIN.
{
// Initialize domain clocks (CPU, HSB, PBA and PBB) to the max frequency available
// without flash wait states.
// Some of the registers in the GPIO module are mapped onto the CPU local bus.
// To ensure maximum transfer speed and cycle determinism, any slaves being
// addressed by the CPU on the local bus must be able to receive and transmit
// data on the bus at CPU clock speeds. The consequences of this is that the
// GPIO module has to run at the CPU clock frequency when local bus transfers
// are being performed => we want fPBA = fCPU.
fcpu_fpba_configure();
// Enable the local bus interface for GPIO.
gpio_local_init();
// Enable the output driver of the example pin.
// Note that the GPIO mode of pins is enabled by default after reset.
gpio_local_enable_pin_output_driver(GPIO_PIN_EXAMPLE);
// Toggle the example GPIO pin at high speed in a loop.
while (1)
{
// Explicit loop unrolling allowing consecutive ST.W instructions without
// loop overhead if compiler optimization is activated, except every 128
// ST.W for the while loop.
#define INSERT_GPIO_LOCAL_TGL_GPIO_PIN(idx, pin) \
gpio_local_tgl_gpio_pin(pin);
MREPEAT(128, INSERT_GPIO_LOCAL_TGL_GPIO_PIN, GPIO_PIN_EXAMPLE)
#undef INSERT_GPIO_LOCAL_TGL_GPIO_PIN
}
}
1.7.1