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# gpio_local_bus_example.c

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    00001 /* This source file is part of the AVR Software Framework 2.0.0 release */
    00002
    00003 /*This file has been prepared for Doxygen automatic documentation generation.*/
    00104 #include "compiler.h"
    00105 #include "preprocessor.h"
    00106 #include "board.h"
    00107 #if UC3L
    00108 // Note: for UC3L devices, the clock configurations are handled by the SCIF module
    00109 // and the synchronous clocks used to clock the main digital logic are handled
    00110 // by the PM module.
    00111 #include "power_clocks_lib.h"
    00112 #elif UC3C
    00113 #include "scif_uc3c.h"
    00114 #include "pm_uc3c.h"
    00115 #else
    00116 #include "pm.h"
    00117 #endif
    00118 #include "gpio.h"
    00119
    00120
    00121
    00122
    00123
    00126
    00127 #define GPIO_PIN_EXAMPLE  AVR32_PIN_PA10
    00128
    00129
    00130
    00133
    00134 #if UC3L
    00135 #define EXAMPLE_FDFLL_HZ              (100000000ULL)  // 100MHz
    00136 #define EXAMPLE_FDFLL_KHZ             (100000UL)
    00137 #define EXAMPLE_MCUCLK_HZ             (25000000UL)    // 25MHz
    00138 #endif
    00139
    00140
    00142
    00143
    00144 static void fcpu_fpba_configure()
    00145 {
    00146 #if UC3L
    00147     static scif_gclk_opt_t gc_dfllif_ref_opt = { SCIF_GCCTRL_SLOWCLOCK, 0, OFF };
    00148     static pcl_freq_param_t pcl_dfll_freq_param =
    00149     {
    00150       .main_clk_src = PCL_MC_DFLL0,
    00151       .cpu_f        = EXAMPLE_MCUCLK_HZ,
    00152       .pba_f        = EXAMPLE_MCUCLK_HZ,
    00153       .pbb_f        = EXAMPLE_MCUCLK_HZ,
    00154       .dfll_f       = EXAMPLE_FDFLL_HZ,
    00155       .pextra_params = &gc_dfllif_ref_opt
    00156     };
    00157 // Implementation for UC3L
    00158     // Note: on the AT32UC3L-EK board, there is no crystal/external clock connected
    00159     // to the OSC0 pinout XIN0/XOUT0. We shall then program the DFLL and switch the
    00160     // main clock source to the DFLL.
    00161     pcl_configure_clocks(&pcl_dfll_freq_param);
    00162     // Note: since it is dynamically computing the appropriate field values of the
    00163     // configuration registers from the parameters structure, this function is not
    00164     // optimal in terms of code size. For a code size optimal solution, it is better
    00165     // to create a new function from pcl_configure_clocks_dfll0() and modify it
    00166     // to use preprocessor computation from pre-defined target frequencies.
    00167 #elif UC3C
    00168     // Configure OSC0 in crystal mode, external crystal with a FOSC0 Hz frequency.
    00169     scif_configure_osc_crystalmode(SCIF_OSC0, FOSC0);
    00170     // Enable the OSC0
    00171     scif_enable_osc(SCIF_OSC0, OSC0_STARTUP, true);
    00172     // Set the main clock source as being OSC0.
    00173     pm_set_mclk_source(PM_CLK_SRC_OSC0);
    00174
    00175     scif_pll_opt_t opt;
    00176
    00177     // Setup PLL0 on Osc0, mul=10 ,no divisor, lockcount=16: (16Mhzx8)/2 = 64MHz output
    00178     opt.osc = SCIF_OSC0;     // Sel Osc0 or Osc1
    00179     opt.lockcount = 16;      // lockcount in main clock for the PLL wait lock
    00180     opt.div = 1;             // DIV=1 in the formula
    00181     opt.mul = 7;             // MUL=7 in the formula
    00182     opt.pll_div2 = 1;        // pll_div2 Divide the PLL output frequency by 2 (this settings does not change the FVCO value)
    00183     opt.pll_wbwdisable = 0;  //pll_wbwdisable 1 Disable the Wide-Bandith Mode (Wide-Bandwith mode allow a faster startup time and out-of-lock time). 0 to enable the Wide-Bandith Mode.
    00184     opt.pll_freq = 1;        // Set to 1 for VCO frequency range 80-180MHz, set to 0 for VCO frequency range 160-240Mhz.
    00185
    00186
    00187     scif_pll_setup(SCIF_PLL0, opt); // lockcount in main clock for the PLL wait lock
    00188
    00189     /* Enable PLL0 */
    00190     scif_pll_enable(SCIF_PLL0);
    00191
    00192     /* Wait for PLL0 locked */
    00193     scif_wait_for_pll_locked(SCIF_PLL0) ;
    00194
    00195     // Divide PLL0 output by 2 for CPU, HSB and PBx clocks = 32MHz
    00196     pm_set_clk_domain_div(PM_CLK_DOMAIN_0, (pm_divratio_t) 0); // CPU
    00197     pm_set_clk_domain_div(PM_CLK_DOMAIN_1, (pm_divratio_t) 0); // HSB
    00198     pm_set_clk_domain_div(PM_CLK_DOMAIN_3, (pm_divratio_t) 0); // PBB
    00199     pm_set_clk_domain_div(PM_CLK_DOMAIN_2, (pm_divratio_t) 0); // PBA
    00200     pm_set_clk_domain_div(PM_CLK_DOMAIN_4, (pm_divratio_t) 0); // PBC
    00201
    00202     /* Set the main clock source as being PLL0. */
    00203     pm_set_mclk_source(PM_CLK_SRC_PLL0);
    00204
    00205 #else
    00206   // Switch the main clock source to Osc0.
    00207   pm_switch_to_osc0(&AVR32_PM, FOSC0, OSC0_STARTUP);
    00208
    00209   // Setup PLL0 on Osc0, mul=10 ,no divisor, lockcount=16: 12Mhzx11 = 132MHz output
    00210   pm_pll_setup(&AVR32_PM, 0,  // pll.
    00211                10,  // mul.
    00212                1,   // div.
    00213                0,   // osc.
    00214                16); // lockcount.
    00215   // PLL output VCO frequency is 132MHz.
    00216   // We divide it by 2 with the pll_div2=1 to get a main clock at 66MHz.
    00217   pm_pll_set_option(&AVR32_PM, 0, // pll.
    00218                     1,  // pll_freq.
    00219                     1,  // pll_div2.
    00220                     0); // pll_wbwdisable.
    00221   // Enable the PLL.
    00222   pm_pll_enable(&AVR32_PM, 0);
    00223   // Wait until the PLL output is stable.
    00224   pm_wait_for_pll0_locked(&AVR32_PM);
    00225   // Configure each clock domain to use the main clock divided by 2
    00226   // => fCPU = fPBA = fPBB = 33MHz.
    00227   pm_cksel(&AVR32_PM,
    00228            1,   // pbadiv.
    00229            0,   // pbasel.
    00230            1,   // pbbdiv.
    00231            0,   // pbbsel.
    00232            1,   // hsbdiv=cpudiv
    00233            0);  // hsbsel=cpusel
    00234   // Switch the main clock source to PLL0.
    00235   pm_switch_to_clock(&AVR32_PM, AVR32_PM_MCCTRL_MCSEL_PLL0);
    00236 #endif
    00237 }
    00238
    00239
    00242 int main(void)
    00243 {
    00244   // Initialize domain clocks (CPU, HSB, PBA and PBB) to the max frequency available
    00245   // without flash wait states.
    00246   // Some of the registers in the GPIO module are mapped onto the CPU local bus.
    00247   // To ensure maximum transfer speed and cycle determinism, any slaves being
    00248   // addressed by the CPU on the local bus must be able to receive and transmit
    00249   // data on the bus at CPU clock speeds. The consequences of this is that the
    00250   // GPIO module has to run at the CPU clock frequency when local bus transfers
    00251   // are being performed => we want fPBA = fCPU.
    00252   fcpu_fpba_configure();
    00253
    00254   // Enable the local bus interface for GPIO.
    00255   gpio_local_init();
    00256
    00257   // Enable the output driver of the example pin.
    00258   // Note that the GPIO mode of pins is enabled by default after reset.
    00259   gpio_local_enable_pin_output_driver(GPIO_PIN_EXAMPLE);
    00260
    00261   // Toggle the example GPIO pin at high speed in a loop.
    00262   while (1)
    00263   {
    00264     // Explicit loop unrolling allowing consecutive ST.W instructions without
    00265     // loop overhead if compiler optimization is activated, except every 128
    00266     // ST.W for the while loop.
    00267 #define INSERT_GPIO_LOCAL_TGL_GPIO_PIN(idx, pin) \
    00268     gpio_local_tgl_gpio_pin(pin);
    00269     MREPEAT(128, INSERT_GPIO_LOCAL_TGL_GPIO_PIN, GPIO_PIN_EXAMPLE)
    00270 #undef INSERT_GPIO_LOCAL_TGL_GPIO_PIN
    00271   }
    00272 }