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# chip/at32uc3a3/include/chip/memory-map.h

Go to the documentation of this file.

    00001
    00041 #ifndef CHIP_MEMORY_MAP_H_INCLUDED
    00042 #define CHIP_MEMORY_MAP_H_INCLUDED
    00043
    00044 /* Internal memories */
    00045 #define CPU_SRAM_BASE                   0x00000000
    00046 #define CPU_SRAM_SIZE                   0x00010000
    00047 #define FLASH_BASE                      0x80000000
    00048 #define FLASH_SIZE                      0x00040000
    00049 #define FLASH_USER_PAGE_BASE            0x80800000
    00050 #define FLASH_USER_PAGE_SIZE            0x00000200
    00051 #define HSB_SRAM_BASE                   0xff000000
    00052 #define HSB_SRAM_SIZE                   0x00010000
    00053
    00054 #define CHIP_ENTRY_VMA                  FLASH_BASE
    00055 #define CHIP_ENTRY_LMA                  FLASH_BASE
    00056
    00057 /* Used by the linker script to place the writeable data sections */
    00058 #define DATA_SRAM_BASE                  CPU_SRAM_BASE
    00059
    00060 /* Devices on the High Speed Bus (HSB) */
    00061 #define USBB_FIFO_BASE                  0xe0000000
    00062 #define DMACA_BASE                      0xff100000
    00063 #define AES_BASE                        0xfffd0000
    00064
    00065 /* Devices on Peripheral Bus A (PBA) */
    00066 #define USBB_REGS_BASE                  0xfffe0000
    00067 #define HMATRIX_BASE                    0xfffe1000
    00068 #define FLASHC_BASE                     0xfffe1400
    00069 #define SMC_BASE                        0xfffe1c00
    00070 #define SDRAMC_BASE                     0xfffe2000
    00071 #define ECCHRS_BASE                     0xfffe2400
    00072 #define BUSMON_BASE                     0xfffe2800
    00073 #define MCI_BASE                        0xfffe4000
    00074 #define MSI_BASE                        0xfffe8000
    00075
    00076 /* Devices on Peripheral Bus B (PBB) */
    00077 #define PDCA_BASE                       0xffff0000
    00078 #define INTC_BASE                       0xffff0800
    00079 #define PM_BASE                         0xffff0c00
    00080 #define RTC_BASE                        0xffff0d00
    00081 #define WDT_BASE                        0xffff0d30
    00082 #define FREQM_BASE                      0xffff0d50
    00083 #define EIC_BASE                        0xffff0d80
    00084 #define GPIO_BASE                       0xffff1000
    00085 #define USART0_BASE                     0xffff1400
    00086 #define USART1_BASE                     0xffff1800
    00087 #define USART2_BASE                     0xffff1c00
    00088 #define USART3_BASE                     0xffff2000
    00089 #define SPI0_BASE                       0xffff2400
    00090 #define SPI1_BASE                       0xffff2800
    00091 #define TWIM0_BASE                      0xffff2c00
    00092 #define TWIM1_BASE                      0xffff3000
    00093 #define SSC_BASE                        0xffff3400
    00094 #define TC0_BASE                        0xffff3800
    00095 #define ADC_BASE                        0xffff3c00
    00096 #define DAC_BASE                        0xffff4000
    00097 #define TC1_BASE                        0xffff4400
    00098 #define TWIS0_BASE                      0xffff5000
    00099 #define TWIS1_BASE                      0xffff5400
    00100
    00101 #ifndef __ASSEMBLER__
    00102 extern struct physmem_pool      cpu_sram_pool;
    00103 extern struct physmem_pool      hsb_sram_pool;
    00104 #endif
    00105
    00106 #endif /* CHIP_MEMORY_MAP_H_INCLUDED */