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# arch/avr32/include/arch/ocd.h

Go to the documentation of this file.

    00001
    00043 #ifndef ARCH_OCD_H_INCLUDED
    00044 #define ARCH_OCD_H_INCLUDED
    00045
    00046 /* OCD Register offsets. Abbreviations used below:
    00047  *
    00048  *      BP      Breakpoint
    00049  *      Comm    Communication
    00050  *      DT      Data Trace
    00051  *      PC      Program Counter
    00052  *      PID     Process ID
    00053  *      R/W     Read/Write
    00054  *      WP      Watchpoint
    00055  */
    00056 #define OCD_DID                         0x0000  /* Device ID */
    00057 #define OCD_DC                          0x0008  /* Development Control */
    00058 #define OCD_DS                          0x0010  /* Development Status */
    00059 #define OCD_RWCS                        0x001c  /* R/W Access Control */
    00060 #define OCD_RWA                         0x0024  /* R/W Access Address */
    00061 #define OCD_RWD                         0x0028  /* R/W Access Data */
    00062 #define OCD_WT                          0x002c  /* Watchpoint Trigger */
    00063 #define OCD_DTC                         0x0034  /* Data Trace Control */
    00064 #define OCD_DTSA0                       0x0038  /* DT Start Addr Channel 0 */
    00065 #define OCD_DTSA1                       0x003c  /* DT Start Addr Channel 1 */
    00066 #define OCD_DTEA0                       0x0048  /* DT End Addr Channel 0 */
    00067 #define OCD_DTEA1                       0x004c  /* DT End Addr Channel 1 */
    00068 #define OCD_BWC0A                       0x0058  /* PC BP/WP Control 0A */
    00069 #define OCD_BWC0B                       0x005c  /* PC BP/WP Control 0B */
    00070 #define OCD_BWC1A                       0x0060  /* PC BP/WP Control 1A */
    00071 #define OCD_BWC1B                       0x0064  /* PC BP/WP Control 1B */
    00072 #define OCD_BWC2A                       0x0068  /* PC BP/WP Control 2A */
    00073 #define OCD_BWC2B                       0x006c  /* PC BP/WP Control 2B */
    00074 #define OCD_BWC3A                       0x0070  /* Data BP/WP Control 3A */
    00075 #define OCD_BWC3B                       0x0074  /* Data BP/WP Control 3B */
    00076 #define OCD_BWA0A                       0x0078  /* PC BP/WP Address 0A */
    00077 #define OCD_BWA0B                       0x007c  /* PC BP/WP Address 0B */
    00078 #define OCD_BWA1A                       0x0080  /* PC BP/WP Address 1A */
    00079 #define OCD_BWA1B                       0x0084  /* PC BP/WP Address 1B */
    00080 #define OCD_BWA2A                       0x0088  /* PC BP/WP Address 2A */
    00081 #define OCD_BWA2B                       0x008c  /* PC BP/WP Address 2B */
    00082 #define OCD_BWA3A                       0x0090  /* Data BP/WP Address 3A */
    00083 #define OCD_BWA3B                       0x0094  /* Data BP/WP Address 3B */
    00084 #define OCD_NXCFG                       0x0100  /* Nexus Configuration */
    00085 #define OCD_DINST                       0x0104  /* Debug Instruction */
    00086 #define OCD_DPC                         0x0108  /* Debug Program Counter */
    00087 #define OCD_CPUCM                       0x010c  /* CPU Control Mask */
    00088 #define OCD_DCCPU                       0x0110  /* Debug Comm CPU */
    00089 #define OCD_DCEMU                       0x0114  /* Debug Comm Emulator */
    00090 #define OCD_DCSR                        0x0118  /* Debug Comm Status */
    00091 #define OCD_PID                         0x011c  /* Ownership Trace PID */
    00092 #define OCD_EPC0                        0x0120  /* Event Pair Control 0 */
    00093 #define OCD_EPC1                        0x0124  /* Event Pair Control 1 */
    00094 #define OCD_EPC2                        0x0128  /* Event Pair Control 2 */
    00095 #define OCD_EPC3                        0x012c  /* Event Pair Control 3 */
    00096 #define OCD_AXC                         0x0130  /* AUX port Control */
    00097
    00098 /* Bits in DID */
    00099 #define OCD_DID_MID_START               1
    00100 #define OCD_DID_MID_SIZE                11
    00101 #define OCD_DID_PN_START                12
    00102 #define OCD_DID_PN_SIZE                 16
    00103 #define OCD_DID_RN_START                28
    00104 #define OCD_DID_RN_SIZE                 4
    00105
    00106 /* Bits in DC */
    00107 #define OCD_DC_TM_START                 0
    00108 #define OCD_DC_TM_SIZE                  2
    00109 #define OCD_DC_EIC_START                3
    00110 #define OCD_DC_EIC_SIZE                 2
    00111 #define OCD_DC_OVC_START                5
    00112 #define OCD_DC_OVC_SIZE                 3
    00113 #define OCD_DC_SS_BIT                   8
    00114 #define OCD_DC_DBR_BIT                  12
    00115 #define OCD_DC_DBE_BIT                  13
    00116 #define OCD_DC_EOS_START                20
    00117 #define OCD_DC_EOS_SIZE                 2
    00118 #define OCD_DC_SQA_BIT                  22
    00119 #define OCD_DC_IRP_BIT                  23
    00120 #define OCD_DC_IFM_BIT                  24
    00121 #define OCD_DC_TOZ_BIT                  25
    00122 #define OCD_DC_TSR_BIT                  26
    00123 #define OCD_DC_RID_BIT                  27
    00124 #define OCD_DC_ORP_BIT                  28
    00125 #define OCD_DC_MM_BIT                   29
    00126 #define OCD_DC_RES_BIT                  30
    00127 #define OCD_DC_ABORT_BIT                31
    00128
    00129 /* Bits in DS */
    00130 #define OCD_DS_SSS_BIT                  0
    00131 #define OCD_DS_SWB_BIT                  1
    00132 #define OCD_DS_HWB_BIT                  2
    00133 #define OCD_DS_HWE_BIT                  3
    00134 #define OCD_DS_STP_BIT                  4
    00135 #define OCD_DS_DBS_BIT                  5
    00136 #define OCD_DS_BP_START                 8
    00137 #define OCD_DS_BP_SIZE                  8
    00138 #define OCD_DS_INC_BIT                  24
    00139 #define OCD_DS_BOZ_BIT                  25
    00140 #define OCD_DS_DBA_BIT                  26
    00141 #define OCD_DS_EXB_BIT                  27
    00142 #define OCD_DS_NTBF_BIT                 28
    00143
    00144 /* Bits in RWCS */
    00145 #define OCD_RWCS_DV_BIT                 0
    00146 #define OCD_RWCS_ERR_BIT                1
    00147 #define OCD_RWCS_CNT_START              2
    00148 #define OCD_RWCS_CNT_SIZE               14
    00149 #define OCD_RWCS_CRC_BIT                19
    00150 #define OCD_RWCS_NTBC_START             20
    00151 #define OCD_RWCS_NTBC_SIZE              2
    00152 #define OCD_RWCS_NTE_BIT                22
    00153 #define OCD_RWCS_NTAP_BIT               23
    00154 #define OCD_RWCS_WRAPPED_BIT            24
    00155 #define OCD_RWCS_CCTRL_START            25
    00156 #define OCD_RWCS_CCTRL_SIZE             2
    00157 #define OCD_RWCS_SZ_START               27
    00158 #define OCD_RWCS_SZ_SIZE                3
    00159 #define OCD_RWCS_RW_BIT                 30
    00160 #define OCD_RWCS_AC_BIT                 31
    00161
    00162 /* Bits in RWA */
    00163 #define OCD_RWA_RWA_START               0
    00164 #define OCD_RWA_RWA_SIZE                32
    00165
    00166 /* Bits in RWD */
    00167 #define OCD_RWD_RWD_START               0
    00168 #define OCD_RWD_RWD_SIZE                32
    00169
    00170 /* Bits in WT */
    00171 #define OCD_WT_DTE_START                20
    00172 #define OCD_WT_DTE_SIZE                 3
    00173 #define OCD_WT_DTS_START                23
    00174 #define OCD_WT_DTS_SIZE                 3
    00175 #define OCD_WT_PTE_START                26
    00176 #define OCD_WT_PTE_SIZE                 3
    00177 #define OCD_WT_PTS_START                29
    00178 #define OCD_WT_PTS_SIZE                 3
    00179
    00180 /* Bits in DTC */
    00181 #define OCD_DTC_T0WP_BIT                0
    00182 #define OCD_DTC_T1WP_BIT                1
    00183 #define OCD_DTC_ASID0EN_BIT             2
    00184 #define OCD_DTC_ASID0_START             3
    00185 #define OCD_DTC_ASID0_SIZE              8
    00186 #define OCD_DTC_ASID1EN_BIT             11
    00187 #define OCD_DTC_ASID1_START             12
    00188 #define OCD_DTC_ASID1_SIZE              8
    00189 #define OCD_DTC_RWT1_START              28
    00190 #define OCD_DTC_RWT1_SIZE               2
    00191 #define OCD_DTC_RWT0_START              30
    00192 #define OCD_DTC_RWT0_SIZE               2
    00193
    00194 /* Bits in DTSA0 */
    00195 #define OCD_DTSA0_DTSA_START            0
    00196 #define OCD_DTSA0_DTSA_SIZE             32
    00197
    00198 /* Bits in DTSA1 */
    00199 #define OCD_DTSA1_DTSA_START            0
    00200 #define OCD_DTSA1_DTSA_SIZE             32
    00201
    00202 /* Bits in DTEA0 */
    00203 #define OCD_DTEA0_DTEA_START            0
    00204 #define OCD_DTEA0_DTEA_SIZE             32
    00205
    00206 /* Bits in DTEA1 */
    00207 #define OCD_DTEA1_DTEA_START            0
    00208 #define OCD_DTEA1_DTEA_SIZE             32
    00209
    00210 /* Bits in BWC0A */
    00211 #define OCD_BWC0A_ASIDEN_BIT            0
    00212 #define OCD_BWC0A_ASID_START            1
    00213 #define OCD_BWC0A_ASID_SIZE             8
    00214 #define OCD_BWC0A_EOC_BIT               14
    00215 #define OCD_BWC0A_AME_BIT               25
    00216 #define OCD_BWC0A_BWE_START             30
    00217 #define OCD_BWC0A_BWE_SIZE              2
    00218
    00219 /* Bits in BWC0B */
    00220 #define OCD_BWC0B_ASIDEN_BIT            0
    00221 #define OCD_BWC0B_ASID_START            1
    00222 #define OCD_BWC0B_ASID_SIZE             8
    00223 #define OCD_BWC0B_EOC_BIT               14
    00224 #define OCD_BWC0B_AME_BIT               25
    00225 #define OCD_BWC0B_BWE_START             30
    00226 #define OCD_BWC0B_BWE_SIZE              2
    00227
    00228 /* Bits in BWC1A */
    00229 #define OCD_BWC1A_ASIDEN_BIT            0
    00230 #define OCD_BWC1A_ASID_START            1
    00231 #define OCD_BWC1A_ASID_SIZE             8
    00232 #define OCD_BWC1A_EOC_BIT               14
    00233 #define OCD_BWC1A_AME_BIT               25
    00234 #define OCD_BWC1A_BWE_START             30
    00235 #define OCD_BWC1A_BWE_SIZE              2
    00236
    00237 /* Bits in BWC1B */
    00238 #define OCD_BWC1B_ASIDEN_BIT            0
    00239 #define OCD_BWC1B_ASID_START            1
    00240 #define OCD_BWC1B_ASID_SIZE             8
    00241 #define OCD_BWC1B_EOC_BIT               14
    00242 #define OCD_BWC1B_AME_BIT               25
    00243 #define OCD_BWC1B_BWE_START             30
    00244 #define OCD_BWC1B_BWE_SIZE              2
    00245
    00246 /* Bits in BWC2A */
    00247 #define OCD_BWC2A_ASIDEN_BIT            0
    00248 #define OCD_BWC2A_ASID_START            1
    00249 #define OCD_BWC2A_ASID_SIZE             8
    00250 #define OCD_BWC2A_EOC_BIT               14
    00251 #define OCD_BWC2A_AMB_START             20
    00252 #define OCD_BWC2A_AMB_SIZE              5
    00253 #define OCD_BWC2A_AME_BIT               25
    00254 #define OCD_BWC2A_BWE_START             30
    00255 #define OCD_BWC2A_BWE_SIZE              2
    00256
    00257 /* Bits in BWC2B */
    00258 #define OCD_BWC2B_ASIDEN_BIT            0
    00259 #define OCD_BWC2B_ASID_START            1
    00260 #define OCD_BWC2B_ASID_SIZE             8
    00261 #define OCD_BWC2B_EOC_BIT               14
    00262 #define OCD_BWC2B_AME_BIT               25
    00263 #define OCD_BWC2B_BWE_START             30
    00264 #define OCD_BWC2B_BWE_SIZE              2
    00265
    00266 /* Bits in BWC3A */
    00267 #define OCD_BWC3A_ASIDEN_BIT            0
    00268 #define OCD_BWC3A_ASID_START            1
    00269 #define OCD_BWC3A_ASID_SIZE             8
    00270 #define OCD_BWC3A_SIZE_START            9
    00271 #define OCD_BWC3A_SIZE_SIZE             3
    00272 #define OCD_BWC3A_EOC_BIT               14
    00273 #define OCD_BWC3A_BWO_START             16
    00274 #define OCD_BWC3A_BWO_SIZE              2
    00275 #define OCD_BWC3A_BME_START             20
    00276 #define OCD_BWC3A_BME_SIZE              4
    00277 #define OCD_BWC3A_BRW_START             28
    00278 #define OCD_BWC3A_BRW_SIZE              2
    00279 #define OCD_BWC3A_BWE_START             30
    00280 #define OCD_BWC3A_BWE_SIZE              2
    00281
    00282 /* Bits in BWC3B */
    00283 #define OCD_BWC3B_ASIDEN_BIT            0
    00284 #define OCD_BWC3B_ASID_START            1
    00285 #define OCD_BWC3B_ASID_SIZE             8
    00286 #define OCD_BWC3B_SIZE_START            9
    00287 #define OCD_BWC3B_SIZE_SIZE             3
    00288 #define OCD_BWC3B_EOC_BIT               14
    00289 #define OCD_BWC3B_BWO_START             16
    00290 #define OCD_BWC3B_BWO_SIZE              2
    00291 #define OCD_BWC3B_BME_START             20
    00292 #define OCD_BWC3B_BME_SIZE              4
    00293 #define OCD_BWC3B_BRW_START             28
    00294 #define OCD_BWC3B_BRW_SIZE              2
    00295 #define OCD_BWC3B_BWE_START             30
    00296 #define OCD_BWC3B_BWE_SIZE              2
    00297
    00298 /* Bits in BWA0A */
    00299 #define OCD_BWA0A_BWA_START             0
    00300 #define OCD_BWA0A_BWA_SIZE              32
    00301
    00302 /* Bits in BWA0B */
    00303 #define OCD_BWA0B_BWA_START             0
    00304 #define OCD_BWA0B_BWA_SIZE              32
    00305
    00306 /* Bits in BWA1A */
    00307 #define OCD_BWA1A_BWA_START             0
    00308 #define OCD_BWA1A_BWA_SIZE              32
    00309
    00310 /* Bits in BWA1B */
    00311 #define OCD_BWA1B_BWA_START             0
    00312 #define OCD_BWA1B_BWA_SIZE              32
    00313
    00314 /* Bits in BWA2A */
    00315 #define OCD_BWA2A_BWA_START             0
    00316 #define OCD_BWA2A_BWA_SIZE              32
    00317
    00318 /* Bits in BWA2B */
    00319 #define OCD_BWA2B_BWA_START             0
    00320 #define OCD_BWA2B_BWA_SIZE              32
    00321
    00322 /* Bits in BWA3A */
    00323 #define OCD_BWA3A_BWA_START             0
    00324 #define OCD_BWA3A_BWA_SIZE              32
    00325
    00326 /* Bits in BWA3B */
    00327 #define OCD_BWA3B_BWA_START             0
    00328 #define OCD_BWA3B_BWA_SIZE              32
    00329
    00330 /* Bits in NXCFG */
    00331 #define OCD_NXCFG_NXARCH_START          0
    00332 #define OCD_NXCFG_NXARCH_SIZE           4
    00333 #define OCD_NXCFG_NXOCD_START           4
    00334 #define OCD_NXCFG_NXOCD_SIZE            4
    00335 #define OCD_NXCFG_NXPCB_START           8
    00336 #define OCD_NXCFG_NXPCB_SIZE            4
    00337 #define OCD_NXCFG_NXDB_START            12
    00338 #define OCD_NXCFG_NXDB_SIZE             4
    00339 #define OCD_NXCFG_MXMSEO_BIT            16
    00340 #define OCD_NXCFG_NXMDO_START           17
    00341 #define OCD_NXCFG_NXMDO_SIZE            4
    00342 #define OCD_NXCFG_NXPT_BIT              21
    00343 #define OCD_NXCFG_NXOT_BIT              22
    00344 #define OCD_NXCFG_NXDWT_BIT             23
    00345 #define OCD_NXCFG_NXDRT_BIT             24
    00346 #define OCD_NXCFG_NXDTC_START           25
    00347 #define OCD_NXCFG_NXDTC_SIZE            3
    00348 #define OCD_NXCFG_NXDMA_BIT             28
    00349
    00350 /* Bits in DINST */
    00351 #define OCD_DINST_DINST_START           0
    00352 #define OCD_DINST_DINST_SIZE            32
    00353
    00354 /* Bits in CPUCM */
    00355 #define OCD_CPUCM_BEM_BIT               1
    00356 #define OCD_CPUCM_FEM_BIT               2
    00357 #define OCD_CPUCM_REM_BIT               3
    00358 #define OCD_CPUCM_IBEM_BIT              4
    00359 #define OCD_CPUCM_IEEM_BIT              5
    00360
    00361 /* Bits in DCCPU */
    00362 #define OCD_DCCPU_DATA_START            0
    00363 #define OCD_DCCPU_DATA_SIZE             32
    00364
    00365 /* Bits in DCEMU */
    00366 #define OCD_DCEMU_DATA_START            0
    00367 #define OCD_DCEMU_DATA_SIZE             32
    00368
    00369 /* Bits in DCSR */
    00370 #define OCD_DCSR_CPUD_BIT               0
    00371 #define OCD_DCSR_EMUD_BIT               1
    00372
    00373 /* Bits in PID */
    00374 #define OCD_PID_PROCESS_START           0
    00375 #define OCD_PID_PROCESS_SIZE            32
    00376
    00377 /* Bits in EPC0 */
    00378 #define OCD_EPC0_RNG_START              0
    00379 #define OCD_EPC0_RNG_SIZE               2
    00380 #define OCD_EPC0_CE_BIT                 4
    00381 #define OCD_EPC0_ECNT_START             16
    00382 #define OCD_EPC0_ECNT_SIZE              16
    00383
    00384 /* Bits in EPC1 */
    00385 #define OCD_EPC1_RNG_START              0
    00386 #define OCD_EPC1_RNG_SIZE               2
    00387 #define OCD_EPC1_ATB_BIT                5
    00388 #define OCD_EPC1_AM_BIT                 6
    00389
    00390 /* Bits in EPC2 */
    00391 #define OCD_EPC2_RNG_START              0
    00392 #define OCD_EPC2_RNG_SIZE               2
    00393 #define OCD_EPC2_DB_START               2
    00394 #define OCD_EPC2_DB_SIZE                2
    00395
    00396 /* Bits in EPC3 */
    00397 #define OCD_EPC3_RNG_START              0
    00398 #define OCD_EPC3_RNG_SIZE               2
    00399 #define OCD_EPC3_DWE_BIT                2
    00400
    00401 /* Bits in AXC */
    00402 #define OCD_AXC_DIV_START               0
    00403 #define OCD_AXC_DIV_SIZE                4
    00404 #define OCD_AXC_AXE_BIT                 8
    00405 #define OCD_AXC_AXS_BIT                 9
    00406 #define OCD_AXC_DDR_BIT                 10
    00407 #define OCD_AXC_LS_BIT                  11
    00408 #define OCD_AXC_REX_BIT                 12
    00409 #define OCD_AXC_REXTEN_BIT              13
    00410
    00411 /* Constants for DC:EIC */
    00412 #define OCD_EIC_PROGRAM_AND_DATA_TRACE  0
    00413 #define OCD_EIC_BREAKPOINT              1
    00414 #define OCD_EIC_NOP                     2
    00415
    00416 /* Constants for DC:OVC */
    00417 #define OCD_OVC_OVERRUN                 0
    00418 #define OCD_OVC_DELAY_CPU_BTM           1
    00419 #define OCD_OVC_DELAY_CPU_DTM           2
    00420 #define OCD_OVC_DELAY_CPU_BTM_DTM       3
    00421
    00422 /* Constants for DC:EOS */
    00423 #define OCD_EOS_NOP                     0
    00424 #define OCD_EOS_DEBUG_MODE              1
    00425 #define OCD_EOS_BREAKPOINT_WATCHPOINT   2
    00426 #define OCD_EOS_THQ                     3
    00427
    00428 /* Constants for RWCS:NTBC */
    00429 #define OCD_NTBC_OVERWRITE              0
    00430 #define OCD_NTBC_DISABLE                1
    00431 #define OCD_NTBC_BREAKPOINT             2
    00432
    00433 /* Constants for RWCS:CCTRL */
    00434 #define OCD_CCTRL_AUTO                  0
    00435 #define OCD_CCTRL_CACHED                1
    00436 #define OCD_CCTRL_UNCACHED              2
    00437
    00438 /* Constants for RWCS:SZ */
    00439 #define OCD_SZ_BYTE                     0
    00440 #define OCD_SZ_HALFWORD                 1
    00441 #define OCD_SZ_WORD                     2
    00442
    00443 /* Constants for WT:PTS */
    00444 #define OCD_PTS_DISABLED                0
    00445 #define OCD_PTS_PROGRAM_0B              1
    00446 #define OCD_PTS_PROGRAM_1A              2
    00447 #define OCD_PTS_PROGRAM_1B              3
    00448 #define OCD_PTS_PROGRAM_2A              4
    00449 #define OCD_PTS_PROGRAM_2B              5
    00450 #define OCD_PTS_DATA_3A                 6
    00451 #define OCD_PTS_DATA_3B                 7
    00452
    00453 /* Constants for DTC:RWT1 */
    00454 #define OCD_RWT1_NO_TRACE               0
    00455 #define OCD_RWT1_DATA_READ              1
    00456 #define OCD_RWT1_DATA_WRITE             2
    00457 #define OCD_RWT1_DATA_READ_WRITE        3
    00458
    00459 /* Constants for DTC:RWT0 */
    00460 #define OCD_RWT0_NO_TRACE               0
    00461 #define OCD_RWT0_DATA_READ              1
    00462 #define OCD_RWT0_DATA_WRITE             2
    00463 #define OCD_RWT0_DATA_READ_WRITE        3
    00464
    00465 /* Constants for BWC0A:BWE */
    00466 #define OCD_BWE_DISABLED                0
    00467 #define OCD_BWE_BREAKPOINT_ENABLED      1
    00468 #define OCD_BWE_WATCHPOINT_ENABLED      3
    00469
    00470 /* Constants for BWC0B:BWE */
    00471 #define OCD_BWE_DISABLED                0
    00472 #define OCD_BWE_BREAKPOINT_ENABLED      1
    00473 #define OCD_BWE_WATCHPOINT_ENABLED      3
    00474
    00475 /* Constants for BWC1A:BWE */
    00476 #define OCD_BWE_DISABLED                0
    00477 #define OCD_BWE_BREAKPOINT_ENABLED      1
    00478 #define OCD_BWE_WATCHPOINT_ENABLED      3
    00479
    00480 /* Constants for BWC1B:BWE */
    00481 #define OCD_BWE_DISABLED                0
    00482 #define OCD_BWE_BREAKPOINT_ENABLED      1
    00483 #define OCD_BWE_WATCHPOINT_ENABLED      3
    00484
    00485 /* Constants for BWC2A:BWE */
    00486 #define OCD_BWE_DISABLED                0
    00487 #define OCD_BWE_BREAKPOINT_ENABLED      1
    00488 #define OCD_BWE_WATCHPOINT_ENABLED      3
    00489
    00490 /* Constants for BWC2B:BWE */
    00491 #define OCD_BWE_DISABLED                0
    00492 #define OCD_BWE_BREAKPOINT_ENABLED      1
    00493 #define OCD_BWE_WATCHPOINT_ENABLED      3
    00494
    00495 /* Constants for BWC3A:SIZE */
    00496 #define OCD_SIZE_BYTE_ACCESS            4
    00497 #define OCD_SIZE_HALFWORD_ACCESS        5
    00498 #define OCD_SIZE_WORD_ACCESS            6
    00499 #define OCD_SIZE_DOUBLE_WORD_ACCESS     7
    00500
    00501 /* Constants for BWC3A:BRW */
    00502 #define OCD_BRW_READ_BREAK              0
    00503 #define OCD_BRW_WRITE_BREAK             1
    00504 #define OCD_BRW_ANY_ACCES_BREAK         2
    00505
    00506 /* Constants for BWC3A:BWE */
    00507 #define OCD_BWE_DISABLED                0
    00508 #define OCD_BWE_BREAKPOINT_ENABLED      1
    00509 #define OCD_BWE_WATCHPOINT_ENABLED      3
    00510
    00511 /* Constants for BWC3B:SIZE */
    00512 #define OCD_SIZE_BYTE_ACCESS            4
    00513 #define OCD_SIZE_HALFWORD_ACCESS        5
    00514 #define OCD_SIZE_WORD_ACCESS            6
    00515 #define OCD_SIZE_DOUBLE_WORD_ACCESS     7
    00516
    00517 /* Constants for BWC3B:BRW */
    00518 #define OCD_BRW_READ_BREAK              0
    00519 #define OCD_BRW_WRITE_BREAK             1
    00520 #define OCD_BRW_ANY_ACCES_BREAK         2
    00521
    00522 /* Constants for BWC3B:BWE */
    00523 #define OCD_BWE_DISABLED                0
    00524 #define OCD_BWE_BREAKPOINT_ENABLED      1
    00525 #define OCD_BWE_WATCHPOINT_ENABLED      3
    00526
    00527 /* Constants for EPC0:RNG */
    00528 #define OCD_RNG_DISABLED                0
    00529 #define OCD_RNG_EXCLUSIVE               1
    00530 #define OCD_RNG_INCLUSIVE               2
    00531
    00532 /* Constants for EPC1:RNG */
    00533 #define OCD_RNG_DISABLED                0
    00534 #define OCD_RNG_EXCLUSIVE               1
    00535 #define OCD_RNG_INCLUSIVE               2
    00536
    00537 /* Constants for EPC2:RNG */
    00538 #define OCD_RNG_DISABLED                0
    00539 #define OCD_RNG_EXCLUSIVE               1
    00540 #define OCD_RNG_INCLUSIVE               2
    00541
    00542 /* Constants for EPC2:DB */
    00543 #define OCD_DB_DISABLED                 0
    00544 #define OCD_DB_CHAINED_B                1
    00545 #define OCD_DB_CHAINED_A                2
    00546 #define OCD_DB_AHAINED_A_AND_B          3
    00547
    00548 /* Constants for EPC3:RNG */
    00549 #define OCD_RNG_DISABLED                0
    00550 #define OCD_RNG_EXCLUSIVE               1
    00551 #define OCD_RNG_INCLUSIVE               2
    00552
    00553 #ifndef __ASSEMBLER__
    00554
    00555 /* Register access macros */
    00556 static inline unsigned long __ocd_read(unsigned int reg)
    00557 {
    00558         return __builtin_mfdr(reg);
    00559 }
    00560
    00561 static inline void __ocd_write(unsigned int reg, unsigned long value)
    00562 {
    00563         __builtin_mtdr(reg, value);
    00564 }
    00565
    00566 #define ocd_read(reg)                   __ocd_read(OCD_##reg)
    00567 #define ocd_write(reg, value)           __ocd_write(OCD_##reg, value)
    00568
    00569 #endif /* !__ASSEMBLER__ */
    00570
    00571 #endif /* ARCH_OCD_H_INCLUDED */