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# drivers/dmac/dmaca_regs.h

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    00001
    00041 #ifndef DMACA_REGS_H_INCLUDED
    00042 #define DMACA_REGS_H_INCLUDED
    00043
    00046 #define DMACA_CHAN_SAR          0x0000
    00047 #define DMACA_CHAN_DAR          0x0008
    00048 #define DMACA_CHAN_LLP          0x0010
    00049 # define DMACA_LLP_LMS(x)               ((x) <<  0)
    00050 #define DMACA_CHAN_CTLL         0x0018
    00051 # define DMACA_CTLL_INT_EN              (  1 <<  0)
    00052 # define DMACA_CTLL_DST_TR_WIDTH(x)     ((x) <<  1)
    00053 # define DMACA_CTLL_SRC_TR_WIDTH(x)     ((x) <<  4)
    00054 # define DMACA_CTLL_DINC_INCREMENT      (  0 <<  7)
    00055 # define DMACA_CTLL_DINC_DECREMENT      (  1 <<  7)
    00056 # define DMACA_CTLL_DINC_NO_CHANGE      (  2 <<  7)
    00057 # define DMACA_CTLL_SINC_INCREMENT      (  0 <<  9)
    00058 # define DMACA_CTLL_SINC_DECREMENT      (  1 <<  9)
    00059 # define DMACA_CTLL_SINC_NO_CHANGE      (  2 <<  9)
    00060 # define DMACA_CTLL_DST_MSIZE(x)        ((x) << 11)
    00061 # define DMACA_CTLL_SRC_MSIZE(x)        ((x) << 14)
    00062 # define DMACA_CTLL_TT_M2M              (  0 << 20)
    00063 # define DMACA_CTLL_TT_M2P              (  1 << 20)
    00064 # define DMACA_CTLL_TT_P2M              (  2 << 20)
    00065 # define DMACA_CTLL_TT_P2P              (  3 << 20)
    00066 # define DMACA_CTLL_DMS(x)              ((x) << 23)
    00067 # define DMACA_CTLL_SMS(x)              ((x) << 25)
    00068 # define DMACA_CTLL_LLP_D_EN            (  1 << 27)
    00069 # define DMACA_CTLL_LLP_S_EN            (  1 << 28)
    00070 #define DMACA_CHAN_CTLH         0x001c
    00071 # define DMACA_CTLH_BLOCK_TS(x)         ((x) <<  0)
    00072 #define DMACA_CHAN_CFGL         0x0040
    00073 # define DMACA_CFGL_CH_PRIOR(x)         ((x) <<  5)
    00074 # define DMACA_CH_SUSP                  (  1 <<  8)
    00075 # define DMACA_FIFO_EMPTY               (  1 <<  9)
    00076 #define DMACA_CHAN_CFGH         0x0044
    00077 # define DMACA_CFGH_FCMODE              (  1 <<  0)
    00078 # define DMACA_CFGH_FIFO_MODE           (  1 <<  1)
    00079 # define DMACA_CFGH_SRC_PER(x)          ((x) <<  7)
    00080 # define DMACA_CFGH_DST_PER(x)          ((x) << 11)
    00081
    00082
    00083
    00084 #define DMACA_CHAN_REGS_SIZE    0x0058
    00085
    00088 #define DMACA_RAW_TFR           0x02c0
    00089 #define DMACA_RAW_BLOCK         0x02c8
    00090 #define DMACA_RAW_SRC_TRAN      0x02d0
    00091 #define DMACA_RAW_DST_TRAN      0x02d8
    00092 #define DMACA_RAW_ERR           0x02e0
    00093 #define DMACA_STATUS_TFR        0x02e8
    00094 #define DMACA_STATUS_BLOCK      0x02f0
    00095 #define DMACA_STATUS_SRC_TRAN   0x02f8
    00096 #define DMACA_STATUS_DST_TRAN   0x0300
    00097 #define DMACA_STATUS_ERR        0x0308
    00098 #define DMACA_MASK_TFR          0x0310
    00099 #define DMACA_MASK_BLOCK        0x0318
    00100 #define DMACA_MASK_SRC_TRAN     0x0320
    00101 #define DMACA_MASK_DST_TRAN     0x0328
    00102 #define DMACA_MASK_ERR          0x0330
    00103 #define DMACA_CLEAR_TFR         0x0338
    00104 #define DMACA_CLEAR_BLOCK       0x0340
    00105 #define DMACA_CLEAR_SRC_TRAN    0x0348
    00106 #define DMACA_CLEAR_DST_TRAN    0x0350
    00107 #define DMACA_CLEAR_ERR         0x0358
    00108 #define DMACA_STATUS_INT        0x0360
    00109 #define DMACA_DMACFG            0x0398
    00110 # define DMACA_DMACFG_DMA_EN            (  1 <<  0)
    00111 #define DMACA_CH_EN             0x03a0
    00112
    00113
    00114
    00115 struct dmaca_hw_desc {
    00116         uint32_t        sar;
    00117         uint32_t        dar;
    00118         uint32_t        llp;
    00119         uint32_t        ctll;
    00120         uint32_t        ctlh;
    00121 };
    00122
    00126 #define dmaca_read_reg(reg)                                     \
    00127         mmio_read32((void *)(DMACA_BASE + DMACA_##reg))
    00128
    00131 #define dmaca_write_reg(reg, value)                             \
    00132         mmio_write32((void *)(DMACA_BASE + DMACA_##reg), value)
    00133
    00137 #define dmaca_chan_read_reg(chan, reg)                          \
    00138         mmio_read32(chan->regs + DMACA_CHAN_##reg)
    00139
    00142 #define dmaca_chan_write_reg(chan, reg, value)                  \
    00143         mmio_write32(chan->regs + DMACA_CHAN_##reg, value)
    00144
    00149 #define dmaca_set_chan_bit(chan, reg)                           \
    00150         dmaca_write_reg(reg, (chan->mask << 8) | chan->mask)
    00151
    00155 #define dmaca_clear_chan_bit(chan, reg)                         \
    00156         dmaca_write_reg(reg, chan->mask << 8)
    00157
    00161 #define dmaca_test_chan_bit(chan, reg)                          \
    00162         (dmaca_read_reg(reg) & chan->mask)
    00163
    00164 #endif /* DMACA_REGS_H_INCLUDED */