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# drivers/aes/aes_regs.h

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    00001
    00042 #ifndef AES_REGS_H_INCLUDED
    00043 #define AES_REGS_H_INCLUDED
    00044
    00045 #include <io.h>
    00046
    00047 #define AES_CR                          0x0000
    00048 #define AES_CR_SWRST                    0x0010
    00049 #define AES_MR                          0x0004
    00050 #define AES_MR_CIPHER_MASK                      (1 << 0)
    00051 #define AES_MR_CIPHER_OFFSET    0
    00052 #define AES_MR_START_MODE_MANUAL        (0)
    00053 #define AES_MR_START_MODE_AUTO          (1 << 8)
    00054 #define AES_MR_START_MODE_DMA           (1 << 9)
    00055 #define AES_MR_LOD                      0x0080
    00056 #define AES_IER                         0x0010
    00057 #define AES_IDR                         0x0014
    00058 #define AES_IMR                         0x0018
    00059 #define AES_ISR                 0x001c
    00060 #define AES_KEY1                0x0020
    00061 #define AES_KEY2                0x0024
    00062 #define AES_KEY3                0x0028
    00063 #define AES_KEY4                0x002c
    00064 #define AES_KEY5                0x0030
    00065 #define AES_KEY6                0x0034
    00066 #define AES_KEY7                0x0038
    00067 #define AES_KEY8                0x003c
    00068 #define AES_INPUT1              0x0040
    00069 #define AES_INPUT2              0x0044
    00070 #define AES_INPUT3              0x0048
    00071 #define AES_INPUT4              0x004c
    00072 #define AES_OUTPUT1             0x0050
    00073 #define AES_OUTPUT2             0x0054
    00074 #define AES_OUTPUT3             0x0058
    00075 #define AES_OUTPUT4             0x005c
    00076 #define AES_INIT1               0x0060
    00077 #define AES_INIT2               0x0064
    00078 #define AES_INIT3               0x0068
    00079 #define AES_INIT4               0x006c
    00080
    00081 //#define SPI_MR_PCS(x)         (x << 16)
    00082 //#define SPI_MR_PCS_MASK               ((0xf) << 16)
    00083
    00084 /* Register access macros */
    00085 #define aes_read_reg(port, reg)                                 \
    00086         mmio_read32((port) + AES_##reg)
    00087 #define aes_write_reg(port, reg, value)                         \
    00088         mmio_write32((port) + AES_##reg, value)
    00089
    00090 #define aes_write_key_reg(port, index, value)                   \
    00091         mmio_write32((port) + AES_KEY1 + (4 * index), value)
    00092 #define aes_write_init_reg(port, index, value)                  \
    00093         mmio_write32((port) + AES_INIT1 + (4 * index), value)
    00094 #define aes_write_input_reg(port, index, value)                 \
    00095         mmio_write32((port) + AES_INPUT1 + (4 * index), value)
    00096 #define aes_read_output_reg(port, index)                        \
    00097         mmio_read32((port) + AES_OUTPUT1 + (4 * index))
    00098
    00099 #endif /* AES_REGS_H_INCLUDED */
    00100