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# drivers/flash/flashc.c

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    00001
    00044 #include <bitops.h>
    00045 #include <interrupt.h>
    00046 #include <io.h>
    00047 #include <chip/memory-map.h>
    00048 #include <flash/flashc.h>
    00049
    00050 void flashc_adjust_wait_state(unsigned long new_hclk_rate)
    00051 {
    00052         unsigned long   iflags;
    00053         uint32_t        fcr;
    00054
    00055         iflags = cpu_irq_save();
    00056
    00057         fcr = mmio_read32((void *)FLASHC_BASE);
    00058
    00059         /* FIXME: Max rate taken from UC3A0 data sheet */
    00060         if (new_hclk_rate > 33000000) {
    00061                 /* Set one wait state for flash access */
    00062                 fcr |= 1 << 6;
    00063         } else {
    00064                 /* No wait state necessary */
    00065                 fcr &= ~(1 << 6);
    00066         }
    00067
    00068         mmio_write32((void *)FLASHC_BASE, fcr);
    00069         mmio_read32((void *)FLASHC_BASE);
    00070
    00071         cpu_irq_restore(iflags);
    00072 }
    00073
    00074 void flashc_write_gp_fuse(unsigned int bit_nr)
    00075 {
    00076         uint32_t        fcmd;
    00077
    00078         assert(bit_nr < 64);
    00079
    00080         fcmd = 0xa5 << 24 | bit_nr << 8 | 7;
    00081         mmio_write32((void *)(FLASHC_BASE + 4), fcmd);
    00082 }
    00083
    00084 void flashc_erase_gp_fuse(unsigned int bit_nr)
    00085 {
    00086         uint32_t        fcmd;
    00087
    00088         assert(bit_nr < 64);
    00089
    00090         fcmd = 0xa5 << 24 | bit_nr << 8 | 8;
    00091         mmio_write32((void *)(FLASHC_BASE + 4), fcmd);
    00092 }