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# include/pm/pm_v3_regs.h

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    00001
    00041 #ifndef HARDWARE_PM_V3_REGS_H_INCLUDED
    00042 #define HARDWARE_PM_V3_REGS_H_INCLUDED
    00043
    00044 /* PM v3 registers and bitfield definitions */
    00045 #define PM_MCCTRL                       0x0000  /* Main Clock Control */
    00046 # define PM_MCCTRL_MCSEL_MASK           (3   <<  0)     /* Main clock select */
    00047 # define PM_MCCTRL_MCSEL(x)             ((x) <<  0)
    00048 # define PM_MCCTRL_MCSEL_SLOW           (0   <<  0)     /* Slow clock */
    00049 # define PM_MCCTRL_MCSEL_OSC0           (1   <<  0)     /* OSC0 */
    00050 # define PM_MCCTRL_MCSEL_PLL0           (2   <<  0)     /* PLL0 */
    00051 # define PM_MCCTRL_OSCEN(x)             (1 << ((x) + 2)) /* OSCx enable */
    00052 # define PM_MCCTRL_OSCEN_BIT(x)         ((x) + 2)       /* OSCx enable */
    00053 # define PM_MCCTRL_CRIPEL_BIT           24              /* CRIPEL enable */
    00054 #define PM_CKSEL                        0x0004  /* Clock Select */
    00055 # define PM_CKSEL_CPUSEL(x)             ((x) <<  0)     /* CPU clock divider */
    00056 # define PM_CKSEL_CPUDIV                (1   <<  7)     /* CPU div enable */
    00057 # define PM_CKSEL_HSBSEL(x)             ((x) <<  8)     /* HSB clock divider */
    00058 # define PM_CKSEL_HSBDIV                (1   << 15)     /* HSB div enable */
    00059 # define PM_CKSEL_PBASEL(x)             ((x) << 16)     /* PBA clock divider */
    00060 # define PM_CKSEL_PBADIV                (1   << 23)     /* PBA div enable */
    00061 # define PM_CKSEL_PBBSEL(x)             ((x) << 24)     /* PBB clock divider */
    00062 # define PM_CKSEL_PBBDIV                (1   << 31)     /* PBB div enable */
    00063 #define PM_CPUMASK                      0x0008  /* CPU clock mask */
    00064 #define PM_HSBMASK                      0x000c  /* HSB clock mask */
    00065 #define PM_PBAMASK                      0x0010  /* PBA clock mask */
    00066 #define PM_PBBMASK                      0x0014  /* PBB clock mask */
    00067 #define PM_PBADIVMASK                   0x0018  /* PBA div clock mask */
    00068 #define PM_PBBDIVMASK                   0x001c  /* PBB div clock mask */
    00069 #define PM_PLL(x)       (0x0040 + 4 * (x))      /* PLL control */
    00070 # define PM_PLL_PLLEN                   (1   <<  0)     /* PLL enable */
    00071 # define PM_PLL_PLLOSC(x)               ((x) <<  1)     /* Osc select */
    00072 # define PM_PLL_GET_PLLOSC(reg)         (((reg) >> 1) & 3)
    00073 # define PM_PLL_VCO_MHZ_MASK            (3   <<  3)     /* VCO frequency */
    00074 # define PM_PLL_VCO_MHZ_25_50           (0   <<  3)     /* 25-50 MHz */
    00075 # define PM_PLL_VCO_MHZ_50_100          (1   <<  3)     /* 50-100 MHz */
    00076 # define PM_PLL_VCO_MHZ_100_200         (2   <<  3)     /* 100-200 MHz */
    00077 # define PM_PLL_VCO_MHZ_200_400         (3   <<  3)     /* 200-400 MHz */
    00078 # define PM_PLL_OUTPUT_DIV_BY_2         (1   <<  5)     /* Divide by 2 */
    00079 # define PM_PLL_PLLDIV(x)               ((x) <<  8)     /* PLL divider */
    00080 # define PM_PLL_GET_PLLDIV(reg)         (((reg) >> 8) & 0x3f)
    00081 # define PM_PLL_PLLMUL(x)               ((x) << 16)     /* PLL multiplier */
    00082 # define PM_PLL_GET_PLLMUL(reg)         (((reg) >> 16) & 0x3f)
    00083 # define PM_PLL_PLLCOUNT(x)             ((x) << 24)     /* PLL startup count */
    00084 #define PM_OSCCTRL(x)   (0x0080 + 4 * (x))      /* Oscillator control */
    00085 # define PM_OSC_MODE_MASK               (7   <<  0)     /* Oscillator Mode */
    00086 # define PM_OSC_MODE_EXT                (0   <<  0)     /* External clock */
    00087 # define PM_OSC_MODE_XTAL_1_12          (1   <<  0)     /* 1-12 MHz crystal */
    00088 # define PM_OSC_MODE_XTAL_12_24         (2   <<  0)     /* 12-24 MHz crystal */
    00089 # define PM_OSC_MODE_XTAL_24_42         (3   <<  0)     /* 24-42 MHz crystal */
    00090 # define PM_OSC_MODE_XTAL_42_66         (4   <<  0)     /* 42-66 MHz crystal */
    00091 # define PM_OSC_MODE_FEEDBACK           (1   <<  3)     /* Feedback resistor */
    00092 # define PM_OSC_STARTUP_MASK            (7   <<  8)     /* Startup cycles */
    00093 # define PM_OSC_STARTUP_0               (0   <<  8)     /* 0 cycles */
    00094 # define PM_OSC_STARTUP_32              (1   <<  8)     /* 32 cycles */
    00095 # define PM_OSC_STARTUP_64              (2   <<  8)     /* 64 cycles */
    00096 # define PM_OSC_STARTUP_512             (3   <<  8)     /* 512 cycles */
    00097 # define PM_OSC_STARTUP_1024            (4   <<  8)     /* 1024 cycles */
    00098 # define PM_OSC_STARTUP_4096            (5   <<  8)     /* 4096 cycles */
    00099 # define PM_OSC_STARTUP_8192            (6   <<  8)     /* 8192 cycles */
    00100 # define PM_OSC_STARTUP_16384           (7   <<  8)     /* 16384 cycles */
    00101 #define PM_IER                          0x00c0  /* Interrupt Enable */
    00102 #define PM_IDR                          0x00c4  /* Interrupt Disable */
    00103 #define PM_IMR                          0x00c8  /* Interrupt Mask */
    00104 #define PM_ISR                          0x00cc  /* Interrupt Status */
    00105 #define PM_ICR                          0x00d0  /* Interrupt Clear */
    00106 #define PM_POSCSR                       0x00d4  /* Power/Osc Status */
    00107 # define PM_OSCRDY(x)                   (1  << (x))     /* OSCx ready */
    00108 # define PM_OSCRDY_BIT(x)               (x)
    00109 # define PM_OSC32RDY                    (1   <<  7)     /* OSC32 ready */
    00110 # define PM_LOCK(x)                     (1 << ((x) + 8)) /* PLLx locked */
    00111 # define PM_LOCKLOST(x)                 (1 << ((x) + 16)) /* PLLx lock lost */
    00112 # define PM_CKRDY                       (1   << 24)     /* Clock ready */
    00113 # define PM_MSKRDY                      (1   << 25)     /* Mask ready */
    00114 # define PM_WAKE                        (1   << 26)     /* ??? */
    00115 # define PM_PERRDY                      (1   << 28)     /* Periph ready */
    00116 #define PM_GCCTRL(x)    (0x0100 + 4 * (x))      /* Generic Clock Control */
    00117 # define PM_GCCTRL_CEN                  (1   <<  0)     /* Clock enable */
    00118 # define PM_GCCTRL_DIVEN                (1   <<  1)     /* Divider enable */
    00119 # define PM_GCCTRL_OSCSEL(x)            ((x) <<  8)     /* Clock source */
    00120 # define PM_GCCTRL_OSCSEL_MASK          (3   << 15)
    00121 # define PM_GCCTRL_DIV(x)               ((x) << 16)     /* Divider */
    00122 #define PM_PPCR                         0x0150  /* Periph Power Control */
    00123 #define PM_RC_RCAUSE                    0x0180  /* Reset Cause */
    00124 #define PM_WCAUSE                       0x0184  /* Wake Cause */
    00125 #define PM_AWEN                         0x0188  /* Async Wake Enable */
    00126
    00127 /* Register access macros */
    00128 #define pm_read_reg(reg)                                        \
    00129         mmio_read32((void *)PM_BASE + PM_##reg)
    00130 #define pm_write_reg(reg, value)                                \
    00131         mmio_write32((void *)PM_BASE + PM_##reg, value)
    00132
    00133 #endif /* HARDWARE_PM_V3_REGS_H_INCLUDED */