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# chip/at32uc3a3/include/chip/dma_controller.h

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    00001
    00041 #ifndef CHIP_DMA_CONTROLLER_H_INCLUDED
    00042 #define CHIP_DMA_CONTROLLER_H_INCLUDED
    00043
    00044 #include <chip/memory-map.h>
    00045 #include <dmac/dmaca.h>
    00046 #include <dmac/pdca.h>
    00047
    00051 enum dmac_periph_id {
    00052         /* DMACA Peripheral IDs */
    00053         DMAC_PERIPH_AES_RX      = 0x00,
    00054         DMAC_PERIPH_AES_TX,
    00055         DMAC_PERIPH_MCI_RX,
    00056         DMAC_PERIPH_MCI_TX,
    00057         DMAC_PERIPH_MSI_RX,
    00058         DMAC_PERIPH_MSI_TX,
    00059         DMAC_PERIPH_EXT0,
    00060         DMAC_PERPIH_EXT1,
    00061
    00062         /* PDCA Peripheral IDs */
    00063         DMAC_PERIPH_ADC_RX      = 0x20,
    00064         DMAC_PERIPH_SSC_RX,
    00065         DMAC_PERIPH_USART0_RX,
    00066         DMAC_PERIPH_USART1_RX,
    00067         DMAC_PERIPH_USART2_RX,
    00068         DMAC_PERIPH_USART3_RX,
    00069         DMAC_PERIPH_TWIM0_RX,
    00070         DMAC_PERIPH_TWIM1_RX,
    00071         DMAC_PERIPH_TWIS0_RX,
    00072         DMAC_PERIPH_TWIS1_RX,
    00073         DMAC_PERIPH_SPI0_RX,
    00074         DMAC_PERIPH_SPI1_RX,
    00075         DMAC_PERIPH_SSC_TX,
    00076         DMAC_PERIPH_USART0_TX,
    00077         DMAC_PERIPH_USART1_TX,
    00078         DMAC_PERIPH_USART2_TX,
    00079         DMAC_PERIPH_USART3_TX,
    00080         DMAC_PERIPH_TWIM0_TX,
    00081         DMAC_PERIPH_TWIM1_TX,
    00082         DMAC_PERIPH_TWIS0_TX,
    00083         DMAC_PERIPH_TWIS1_TX,
    00084         DMAC_PERIPH_SPI0_TX,
    00085         DMAC_PERIPH_SPI1_TX,
    00086         DMAC_PERIPH_DAC_TX,
    00087
    00088         /* Dummy ID indicating "no peripheral" */
    00089         DMAC_PERIPH_NONE        = 0xff,
    00090 };
    00091
    00092 static inline unsigned int dmaca_get_periph_id(enum dmac_periph_id dmac_id)
    00093 {
    00094         return dmac_id;
    00095 }
    00096
    00097 static inline unsigned int pdca_get_periph_id(enum dmac_periph_id dmac_id)
    00098 {
    00099         return dmac_id - 0x20;
    00100 }
    00101
    00102 /* FIXME: Missing from the documentation */
    00103 #define CHIP_DMACA_NR_CHANNELS          4
    00104 #define CHIP_PDCA_NR_CHANNELS           8
    00105
    00106 #define PDCA_NR_PERIPH_IDS              24
    00107
    00108 static inline struct dmac_channel *dmac_aes_alloc_tx_channel(void)
    00109 {
    00110         return dmaca_alloc_channel(&dmaca_controller, DMAC_PERIPH_NONE,
    00111                         DMAC_PERIPH_AES_TX, 0, AES_BASE + 0x40);
    00112 }
    00113
    00114 static inline struct dmac_channel *dmac_aes_alloc_rx_channel(void)
    00115 {
    00116         return dmaca_alloc_channel(&dmaca_controller, DMAC_PERIPH_AES_RX,
    00117                         DMAC_PERIPH_NONE, AES_BASE + 0x50, 0);
    00118 }
    00119
    00120 static inline void dmac_aes_free_channel(struct dmac_channel *chan)
    00121 {
    00122         dmaca_free_channel(&dmaca_controller, chan);
    00123 }
    00124
    00125 static inline struct dmac_channel *dmac_mci_alloc_channel(void)
    00126 {
    00127         return dmaca_alloc_channel(&dmaca_controller, DMAC_PERIPH_MCI_RX,
    00128                         DMAC_PERIPH_MCI_TX, MCI_BASE + 0x30, MCI_BASE + 0x34);
    00129 }
    00130
    00131 static inline void dmac_mci_free_channel(struct dmac_channel *chan)
    00132 {
    00133         dmaca_free_channel(&dmaca_controller, chan);
    00134 }
    00135
    00136 extern struct dma_controller pdca_controller;
    00137
    00138 static inline struct dmac_channel *dmac_spi_alloc_tx_channel(
    00139                 unsigned int id)
    00140 {
    00141         assert(id <= 1);
    00142
    00143         switch (id) {
    00144         case 0:
    00145                 return pdca_alloc_channel(&pdca_controller, DMAC_PERIPH_NONE,
    00146                                 DMAC_PERIPH_SPI0_TX, 0, SPI0_BASE + 0x0C);
    00147         case 1:
    00148                 return pdca_alloc_channel(&pdca_controller, DMAC_PERIPH_NONE,
    00149                                 DMAC_PERIPH_SPI1_TX, 0, SPI1_BASE + 0x0C);
    00150         default:
    00151                 return NULL;
    00152         }
    00153 }
    00154
    00155 static inline struct dmac_channel *dmac_spi_alloc_rx_channel(
    00156                 unsigned int id)
    00157 {
    00158         assert(id <= 1);
    00159
    00160         switch (id) {
    00161         case 0:
    00162                 return pdca_alloc_channel(&pdca_controller,
    00163                                 DMAC_PERIPH_SPI0_RX, DMAC_PERIPH_NONE,
    00164                                 SPI0_BASE + 0x08, 0);
    00165         case 1:
    00166                 return pdca_alloc_channel(&pdca_controller,
    00167                                 DMAC_PERIPH_SPI1_RX, DMAC_PERIPH_NONE,
    00168                                 SPI1_BASE + 0x08, 0);
    00169         default:
    00170                 return NULL;
    00171         }
    00172 }
    00173
    00174 static inline void dmac_spi_free_channel(struct dmac_channel *chan)
    00175 {
    00176         pdca_free_channel(&pdca_controller, chan);
    00177 }
    00178
    00179 #endif /* CHIP_DMA_CONTROLLER_H_INCLUDED */