port.c File Reference

---

Detailed Description

FreeRTOS port source for AVR32 UC3.

• Compiler: IAR EWAVR32
• Supported devices: All AVR32 devices can be used.
• AppNote:

Author:

Atmel Corporation: http://www.atmel.com
Support and FAQ: http://support.atmel.no/

Definition in file IAR/AVR32_UC3/port.c.

#include "gpio.h"
#include "FreeRTOS.h"
#include "task.h"
#include <avr32/io.h>
#include <intrinsics.h>

Go to the source code of this file.

Defines
#define	portINITIAL_SR   ( ( portSTACK_TYPE ) 0x00400000 )
#define	portINSTRUCTION_SIZE   ( ( portSTACK_TYPE ) 0 )
#define	portNO_CRITICAL_NESTING   ( ( unsigned portLONG ) 0 )
Functions
int	__low_level_init (void)
void	local_start_pll (void)
static void	prvClearCcInt (void)
static void	prvScheduleFirstTick (void)
static void	prvSetupTimerInterrupt (void)
void *	pvPortRealloc (void *pv, size_t xWantedSize)
portSTACK_TYPE *	pxPortInitialiseStack (portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters)
void	SCALLYield (void)
void	vPortEndScheduler (void)
void	vPortEnterCritical (void)
void	vPortExitCritical (void)
static void	vTick (void)
portBASE_TYPE	xPortStartScheduler (void)
Variables
volatile unsigned portLONG	ulCriticalNesting = 9999UL

---

Define Documentation

#define portINITIAL_SR   ( ( portSTACK_TYPE ) 0x00400000 )

Definition at line 78 of file IAR/AVR32_UC3/port.c.

#define portINSTRUCTION_SIZE   ( ( portSTACK_TYPE ) 0 )

Definition at line 79 of file IAR/AVR32_UC3/port.c.

#define portNO_CRITICAL_NESTING   ( ( unsigned portLONG ) 0 )

Definition at line 82 of file IAR/AVR32_UC3/port.c.

---

Function Documentation

int __low_level_init

(

void

)

Definition at line 100 of file IAR/AVR32_UC3/port.c.

References configCPU_CLOCK_HZ, and local_start_pll().

{
    #if configHEAP_INIT
        #pragma segment = "HEAP"
        portBASE_TYPE *pxMem;
    #endif

    /* Enable exceptions. */
    ENABLE_ALL_EXCEPTIONS();

    /* Initialize interrupt handling. */
    INTC_init_interrupts();

    #if configHEAP_INIT
    {
        /* Initialize the heap used by malloc. */
        for( pxMem = __segment_begin( "HEAP" ); pxMem < ( portBASE_TYPE * ) __segment_end( "HEAP" ); )
        {
            *pxMem++ = 0xA5A5A5A5;
        }
    }
    #endif

    /* Code section present if and only if the debug trace is activated. */
    #if configDBG
    {
        static const gpio_map_t DBG_USART_GPIO_MAP =
        {
            { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
            { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
        };

        static const usart_options_t DBG_USART_OPTIONS =
        {
            .baudrate = configDBG_USART_BAUDRATE,
            .charlength = 8,
            .paritytype = USART_NO_PARITY,
            .stopbits = USART_1_STOPBIT,
            .channelmode = USART_NORMAL_CHMODE
        };

        /* Initialize the USART used for the debug trace with the configured parameters. */
        extern volatile avr32_usart_t *volatile stdio_usart_base;
        stdio_usart_base = configDBG_USART;
        gpio_enable_module( DBG_USART_GPIO_MAP,
                            sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
        usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ);
    }
    #endif

    local_start_pll();

    /* Request initialization of data segments. */
    return 1;
}

void local_start_pll

(

void

)

Definition at line 106 of file main.c.

Referenced by __low_level_init(), and _init_startup().

                           {

    volatile avr32_pm_t *pm = &AVR32_PM;

    // Switch the main clock to OSC0
    pm_switch_to_osc0(pm, FOSC0, OSC0_STARTUP);
    // Setup PLL0 on OSC0, mul=15 ,no divisor, lockcount=16, ie. 12Mhz x 11 = 132MHz output
    pm_pll_setup(pm,    // volatile avr32_pm_t *pm
            0,  // unsigned int pll
            10, // unsigned int mul
            1,  // unsigned int div, Sel Osc0/PLL0 or Osc1/Pll1
            0,  // unsigned int osc
            16);// unsigned int lockcount


    // set PLL options to run @ 96 Mhz
    pm_pll_set_option(pm, // volatile avr32_pm_t *pm
            0, // unsigned int pll
            1, // unsigned int  pll_freq
            1, // unsigned int  pll_div2
            0); // unsigned int  pll_wbwdisable
    // Enable PLL0
    pm_pll_enable(pm, 0);
    // Wait for PLL0 locked
    pm_wait_for_pll0_locked(pm) ;
    // Setup generic clock number 0 on PLL, with OSC0/PLL0, no divisor
    pm_gc_setup(pm, 0, 1, // Use Osc (=0) or PLL (=1)
            0,    // Sel Osc0/PLL0 or Osc1/Pll1
            0, 0);

    // Enable Generic clock 0*/
    pm_gc_enable(pm, 0);

    // set divider to 8 for PBA bus and 2 for PBB 0 for CPU
    pm_cksel(pm, 1, 1, 1, 0, 0, 0);

    // one wait state at 66 Mhz
    flashc_set_wait_state(1);
    /* Output the clock to a gpio(PA7) */
    gpio_enable_module_pin(AVR32_PM_GCLK_0_0_PIN, AVR32_PM_GCLK_0_0_FUNCTION);

    // switch to clock
    pm_switch_to_clock(pm, AVR32_PM_MCCTRL_MCSEL_PLL0);
    
    /* Initialize the SDRAM Controller and the external SDRAM chip. */
    sdramc_init(66000000);
    
}

static void prvClearCcInt

(

void

)

[static]

Definition at line 309 of file IAR/AVR32_UC3/port.c.

    {
        Set_system_register(AVR32_COMPARE, Get_system_register(AVR32_COMPARE));
    }

static void prvScheduleFirstTick

(

void

)

[static]

Definition at line 302 of file IAR/AVR32_UC3/port.c.

References configCPU_CLOCK_HZ, and configTICK_RATE_HZ.

    {
        Set_system_register(AVR32_COMPARE, configCPU_CLOCK_HZ/configTICK_RATE_HZ);
        Set_system_register(AVR32_COUNT, 0);
    }

static void prvSetupTimerInterrupt

(

void

)

[static]

Definition at line 323 of file IAR/AVR32_UC3/port.c.

References configPBA_CLOCK_HZ, configTICK_RATE_HZ, configTICK_TC_CHANNEL, prvScheduleFirstTick(), and vTick().

{
    #if( configTICK_USE_TC==1 )

        volatile avr32_tc_t *tc = &AVR32_TC;

        // Options for waveform genration.
        tc_waveform_opt_t waveform_opt =
        {
        .channel  = configTICK_TC_CHANNEL,             /* Channel selection. */

        .bswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOB. */
        .beevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOB. */
        .bcpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOB. */
        .bcpb     = TC_EVT_EFFECT_NOOP,                /* RB compare effect on TIOB. */

        .aswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOA. */
        .aeevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOA. */
        .acpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOA: toggle. */
        .acpa     = TC_EVT_EFFECT_NOOP,                /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */

        .wavsel   = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
        .enetrg   = FALSE,                             /* External event trigger enable. */
        .eevt     = 0,                                 /* External event selection. */
        .eevtedg  = TC_SEL_NO_EDGE,                    /* External event edge selection. */
        .cpcdis   = FALSE,                             /* Counter disable when RC compare. */
        .cpcstop  = FALSE,                             /* Counter clock stopped with RC compare. */

        .burst    = FALSE,                             /* Burst signal selection. */
        .clki     = FALSE,                             /* Clock inversion. */
        .tcclks   = TC_CLOCK_SOURCE_TC3                /* Internal source clock 3. */
        };

        tc_interrupt_t tc_interrupt =
        {
            .etrgs=0,
            .ldrbs=0,
            .ldras=0,
            .cpcs =1,
            .cpbs =0,
            .cpas =0,
            .lovrs=0,
            .covfs=0,
        };

    #endif

    /* Disable all interrupt/exception. */
    portDISABLE_INTERRUPTS();

    /* Register the compare interrupt handler to the interrupt controller and
    enable the compare interrupt. */

    #if( configTICK_USE_TC==1 )
    {
        INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, AVR32_INTC_INT0);

        /* Initialize the timer/counter. */
        tc_init_waveform(tc, &waveform_opt);

        /* Set the compare triggers.
        Remember TC counter is 16-bits, so counting second is not possible!
        That's why we configure it to count ms. Set Rc to the right value with
        rounding. */
        tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ + 4 * configTICK_RATE_HZ ) /
                                                ( 8 * configTICK_RATE_HZ ) );

        tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );

        /* Start the timer/counter. */
        tc_start(tc, configTICK_TC_CHANNEL);
    }
    #else
    {
        INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, AVR32_INTC_INT0);
        prvScheduleFirstTick();
    }
    #endif
}

void* pvPortRealloc	(	void *	pv,
		size_t	xWantedSize
	)

Definition at line 158 of file IAR/AVR32_UC3/port.c.

{
void *pvReturn;

    vTaskSuspendAll();
    {
        pvReturn = realloc( pv, xWantedSize );
    }
    xTaskResumeAll();

    return pvReturn;
}

portSTACK_TYPE* pxPortInitialiseStack	(	portSTACK_TYPE *	pxTopOfStack,
		pdTASK_CODE	pxCode,
		void *	pvParameters
	)

Definition at line 249 of file IAR/AVR32_UC3/port.c.

References portINITIAL_SR, portINSTRUCTION_SIZE, and portNO_CRITICAL_NESTING.

{
    /* Setup the initial stack of the task.  The stack is set exactly as
    expected by the portRESTORE_CONTEXT() macro. */

    /* When the task starts, it will expect to find the function parameter in R12. */
    pxTopOfStack--;
    *pxTopOfStack-- = ( portSTACK_TYPE ) 0x08080808;                    /* R8 */
    *pxTopOfStack-- = ( portSTACK_TYPE ) 0x09090909;                    /* R9 */
    *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0A0A0A0A;                    /* R10 */
    *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0B0B0B0B;                    /* R11 */
    *pxTopOfStack-- = ( portSTACK_TYPE ) pvParameters;                  /* R12 */
    *pxTopOfStack-- = ( portSTACK_TYPE ) 0xDEADBEEF;                    /* R14/LR */
    *pxTopOfStack-- = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
    *pxTopOfStack-- = ( portSTACK_TYPE ) portINITIAL_SR;                /* SR */
    *pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF0000FF;                    /* R0 */
    *pxTopOfStack-- = ( portSTACK_TYPE ) 0x01010101;                    /* R1 */
    *pxTopOfStack-- = ( portSTACK_TYPE ) 0x02020202;                    /* R2 */
    *pxTopOfStack-- = ( portSTACK_TYPE ) 0x03030303;                    /* R3 */
    *pxTopOfStack-- = ( portSTACK_TYPE ) 0x04040404;                    /* R4 */
    *pxTopOfStack-- = ( portSTACK_TYPE ) 0x05050505;                    /* R5 */
    *pxTopOfStack-- = ( portSTACK_TYPE ) 0x06060606;                    /* R6 */
    *pxTopOfStack-- = ( portSTACK_TYPE ) 0x07070707;                    /* R7 */
    *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_NESTING;         /* ulCriticalNesting */

    return pxTopOfStack;
}

void SCALLYield

(

void

)

Definition at line 202 of file IAR/AVR32_UC3/port.c.

{
    /* Save the context of the interrupted task. */
    portSAVE_CONTEXT_SCALL();
    vTaskSwitchContext();
    portRESTORE_CONTEXT_SCALL();
}

void vPortEndScheduler

(

void

)

Definition at line 292 of file IAR/AVR32_UC3/port.c.

{
    /* It is unlikely that the AVR32 port will require this function as there
    is nothing to return to.  */
}

void vPortEnterCritical

(

void

)

Definition at line 216 of file IAR/AVR32_UC3/port.c.

References ulCriticalNesting.

{
    /* Disable interrupts */
    portDISABLE_INTERRUPTS();

    /* Now interrupts are disabled ulCriticalNesting can be accessed
     directly.  Increment ulCriticalNesting to keep a count of how many times
     portENTER_CRITICAL() has been called. */
    ulCriticalNesting++;
}

void vPortExitCritical

(

void

)

Definition at line 229 of file IAR/AVR32_UC3/port.c.

References portNO_CRITICAL_NESTING, and ulCriticalNesting.

{
    if(ulCriticalNesting > portNO_CRITICAL_NESTING)
    {
        ulCriticalNesting--;
        if( ulCriticalNesting == portNO_CRITICAL_NESTING )
        {
            /* Enable all interrupt/exception. */
            portENABLE_INTERRUPTS();
        }
    }
}

static void vTick

(

void

)

[static]

Definition at line 177 of file IAR/AVR32_UC3/port.c.

References prvClearCcInt().

{
    /* Save the context of the interrupted task. */
    portSAVE_CONTEXT_OS_INT();

    #if( configTICK_USE_TC==1 )
        /* Clear the interrupt flag. */
        prvClearTcInt();
    #else
        /* Clear the interrupt flag. */
        prvClearCcInt();
    #endif

    /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
    calls in a critical section . */
    portENTER_CRITICAL();
        vTaskIncrementTick();
    portEXIT_CRITICAL();

    /* Restore the context of the "elected task". */
    portRESTORE_CONTEXT_OS_INT();
}

portBASE_TYPE xPortStartScheduler

(

void

)

Definition at line 278 of file IAR/AVR32_UC3/port.c.

References prvSetupTimerInterrupt().

{
    /* Start the timer that generates the tick ISR.  Interrupts are disabled
    here already. */
    prvSetupTimerInterrupt();

    /* Start the first task. */
    portRESTORE_CONTEXT();

    /* Should not get here! */
    return 0;
}

---

Variable Documentation

volatile unsigned portLONG ulCriticalNesting = 9999UL

Definition at line 83 of file IAR/AVR32_UC3/port.c.