# port.c File Reference

## Detailed Description

FreeRTOS port source for AVR32 UC3.

- Compiler: IAR EWAVR32
- Supported devices: All AVR32 devices can be used.
- AppNote:

Author:
  Atmel Corporation: http://www.atmel.com
  Support and FAQ: http://support.atmel.no/

Definition in file IAR/AVR32_UC3/port.c.

`#include "gpio.h"`
`#include "FreeRTOS.h"`
`#include "task.h"`
`#include <avr32/io.h>`
`#include <intrinsics.h>`

Go to the source code of this file.

## Defines
#define | portINITIAL_SR ( ( portSTACK_TYPE ) 0x00400000 )
#define | portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 0 )
#define | portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )
## Functions
int | __low_level_init (void)
void | local_start_pll (void)
static void | prvClearCcInt (void)
static void | prvScheduleFirstTick (void)
static void | prvSetupTimerInterrupt (void)
void * | pvPortRealloc (void *pv, size_t xWantedSize)
portSTACK_TYPE * | pxPortInitialiseStack (portSTACK_TYPE *pxTopOfStack, pdTASK_CODE pxCode, void *pvParameters)
void | SCALLYield (void)
void | vPortEndScheduler (void)
void | vPortEnterCritical (void)
void | vPortExitCritical (void)
static void | vTick (void)
portBASE_TYPE | xPortStartScheduler (void)
## Variables
volatile unsigned portLONG | ulCriticalNesting = 9999UL

## Define Documentation

#define portINITIAL_SR ( ( portSTACK_TYPE ) 0x00400000 )

Definition at line 78 of file IAR/AVR32_UC3/port.c.

#define portINSTRUCTION_SIZE ( ( portSTACK_TYPE ) 0 )

Definition at line 79 of file IAR/AVR32_UC3/port.c.

#define portNO_CRITICAL_NESTING ( ( unsigned portLONG ) 0 )

Definition at line 82 of file IAR/AVR32_UC3/port.c.

## Function Documentation

int __low_level_init | ( | void |  | ) |

Definition at line 100 of file IAR/AVR32_UC3/port.c.

References configCPU_CLOCK_HZ, and local_start_pll().

    00101 {
    00102     #if configHEAP_INIT
    00103         #pragma segment = "HEAP"
    00104         portBASE_TYPE *pxMem;
    00105     #endif
    00106
    00107     /* Enable exceptions. */
    00108     ENABLE_ALL_EXCEPTIONS();
    00109
    00110     /* Initialize interrupt handling. */
    00111     INTC_init_interrupts();
    00112
    00113     #if configHEAP_INIT
    00114     {
    00115         /* Initialize the heap used by malloc. */
    00116         for( pxMem = __segment_begin( "HEAP" ); pxMem < ( portBASE_TYPE * ) __segment_end( "HEAP" ); )
    00117         {
    00118             *pxMem++ = 0xA5A5A5A5;
    00119         }
    00120     }
    00121     #endif
    00122
    00123     /* Code section present if and only if the debug trace is activated. */
    00124     #if configDBG
    00125     {
    00126         static const gpio_map_t DBG_USART_GPIO_MAP =
    00127         {
    00128             { configDBG_USART_RX_PIN, configDBG_USART_RX_FUNCTION },
    00129             { configDBG_USART_TX_PIN, configDBG_USART_TX_FUNCTION }
    00130         };
    00131
    00132         static const usart_options_t DBG_USART_OPTIONS =
    00133         {
    00134             .baudrate = configDBG_USART_BAUDRATE,
    00135             .charlength = 8,
    00136             .paritytype = USART_NO_PARITY,
    00137             .stopbits = USART_1_STOPBIT,
    00138             .channelmode = USART_NORMAL_CHMODE
    00139         };
    00140
    00141         /* Initialize the USART used for the debug trace with the configured parameters. */
    00142         extern volatile avr32_usart_t *volatile stdio_usart_base;
    00143         stdio_usart_base = configDBG_USART;
    00144         gpio_enable_module( DBG_USART_GPIO_MAP,
    00145                             sizeof( DBG_USART_GPIO_MAP ) / sizeof( DBG_USART_GPIO_MAP[0] ) );
    00146         usart_init_rs232(configDBG_USART, &DBG_USART_OPTIONS, configCPU_CLOCK_HZ);
    00147     }
    00148     #endif
    00149
    00150     local_start_pll();
    00151
    00152     /* Request initialization of data segments. */
    00153     return 1;
    00154 }

void local_start_pll | ( | void |  | ) |

Definition at line 133 of file main.c.

Referenced by __low_level_init(), and _init_startup().

    00133                            {
    00134
    00135     volatile avr32_pm_t *pm = &AVR32_PM;
    00136
    00137     // Switch the main clock to OSC0
    00138     pm_switch_to_osc0(pm, FOSC0, OSC0_STARTUP);
    00139     // Setup PLL0 on OSC0, mul=15 ,no divisor, lockcount=16, ie. 12Mhz x 11 = 132MHz output
    00140     pm_pll_setup(pm,    // volatile avr32_pm_t *pm
    00141             0,  // unsigned int pll
    00142             10, // unsigned int mul
    00143             1,  // unsigned int div, Sel Osc0/PLL0 or Osc1/Pll1
    00144             0,  // unsigned int osc
    00145             16);// unsigned int lockcount
    00146
    00147
    00148     // set PLL options to run @ 96 Mhz
    00149     pm_pll_set_option(pm, // volatile avr32_pm_t *pm
    00150             0, // unsigned int pll
    00151             1, // unsigned int  pll_freq
    00152             1, // unsigned int  pll_div2
    00153             0); // unsigned int  pll_wbwdisable
    00154     // Enable PLL0
    00155     pm_pll_enable(pm, 0);
    00156     // Wait for PLL0 locked
    00157     pm_wait_for_pll0_locked(pm) ;
    00158     // Setup generic clock number 0 on PLL, with OSC0/PLL0, no divisor
    00159     pm_gc_setup(pm, 0, 1, // Use Osc (=0) or PLL (=1)
    00160             0,    // Sel Osc0/PLL0 or Osc1/Pll1
    00161             0, 0);
    00162
    00163     // Enable Generic clock 0*/
    00164     pm_gc_enable(pm, 0);
    00165
    00166     // set divider to 8 for PBA bus and 2 for PBB 0 for CPU
    00167     pm_cksel(pm, 1, 1, 1, 0, 0, 0);
    00168
    00169     // one wait state at 66 Mhz
    00170     flashc_set_wait_state(1);
    00171     /* Output the clock to a gpio(PA7) */
    00172     gpio_enable_module_pin(AVR32_PM_GCLK_0_0_PIN, AVR32_PM_GCLK_0_0_FUNCTION);
    00173
    00174     // switch to clock
    00175     pm_switch_to_clock(pm, AVR32_PM_MCCTRL_MCSEL_PLL0);
    00176
    00177     /* Initialize the SDRAM Controller and the external SDRAM chip. */
    00178     sdramc_init(66000000);
    00179
    00180 }

static void prvClearCcInt | ( | void |  | ) | `[static]`

Definition at line 309 of file IAR/AVR32_UC3/port.c.

    00310     {
    00311         Set_system_register(AVR32_COMPARE, Get_system_register(AVR32_COMPARE));
    00312     }

static void prvScheduleFirstTick | ( | void |  | ) | `[static]`

Definition at line 302 of file IAR/AVR32_UC3/port.c.

References configCPU_CLOCK_HZ, and configTICK_RATE_HZ.

    00303     {
    00304         Set_system_register(AVR32_COMPARE, configCPU_CLOCK_HZ/configTICK_RATE_HZ);
    00305         Set_system_register(AVR32_COUNT, 0);
    00306     }

static void prvSetupTimerInterrupt | ( | void |  | ) | `[static]`

Definition at line 323 of file IAR/AVR32_UC3/port.c.

References configPBA_CLOCK_HZ, configTICK_RATE_HZ, configTICK_TC_CHANNEL, prvScheduleFirstTick(), and vTick().

    00324 {
    00325     #if( configTICK_USE_TC==1 )
    00326
    00327         volatile avr32_tc_t *tc = &AVR32_TC;
    00328
    00329         // Options for waveform genration.
    00330         tc_waveform_opt_t waveform_opt =
    00331         {
    00332         .channel  = configTICK_TC_CHANNEL,             /* Channel selection. */
    00333
    00334         .bswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOB. */
    00335         .beevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOB. */
    00336         .bcpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOB. */
    00337         .bcpb     = TC_EVT_EFFECT_NOOP,                /* RB compare effect on TIOB. */
    00338
    00339         .aswtrg   = TC_EVT_EFFECT_NOOP,                /* Software trigger effect on TIOA. */
    00340         .aeevt    = TC_EVT_EFFECT_NOOP,                /* External event effect on TIOA. */
    00341         .acpc     = TC_EVT_EFFECT_NOOP,                /* RC compare effect on TIOA: toggle. */
    00342         .acpa     = TC_EVT_EFFECT_NOOP,                /* RA compare effect on TIOA: toggle (other possibilities are none, set and clear). */
    00343
    00344         .wavsel   = TC_WAVEFORM_SEL_UP_MODE_RC_TRIGGER,/* Waveform selection: Up mode without automatic trigger on RC compare. */
    00345         .enetrg   = FALSE,                             /* External event trigger enable. */
    00346         .eevt     = 0,                                 /* External event selection. */
    00347         .eevtedg  = TC_SEL_NO_EDGE,                    /* External event edge selection. */
    00348         .cpcdis   = FALSE,                             /* Counter disable when RC compare. */
    00349         .cpcstop  = FALSE,                             /* Counter clock stopped with RC compare. */
    00350
    00351         .burst    = FALSE,                             /* Burst signal selection. */
    00352         .clki     = FALSE,                             /* Clock inversion. */
    00353         .tcclks   = TC_CLOCK_SOURCE_TC3                /* Internal source clock 3. */
    00354         };
    00355
    00356         tc_interrupt_t tc_interrupt =
    00357         {
    00358             .etrgs=0,
    00359             .ldrbs=0,
    00360             .ldras=0,
    00361             .cpcs =1,
    00362             .cpbs =0,
    00363             .cpas =0,
    00364             .lovrs=0,
    00365             .covfs=0,
    00366         };
    00367
    00368     #endif
    00369
    00370     /* Disable all interrupt/exception. */
    00371     portDISABLE_INTERRUPTS();
    00372
    00373     /* Register the compare interrupt handler to the interrupt controller and
    00374     enable the compare interrupt. */
    00375
    00376     #if( configTICK_USE_TC==1 )
    00377     {
    00378         INTC_register_interrupt((__int_handler)&vTick, configTICK_TC_IRQ, AVR32_INTC_INT0);
    00379
    00380         /* Initialize the timer/counter. */
    00381         tc_init_waveform(tc, &waveform_opt);
    00382
    00383         /* Set the compare triggers.
    00384         Remember TC counter is 16-bits, so counting second is not possible!
    00385         That's why we configure it to count ms. Set Rc to the right value with
    00386         rounding. */
    00387         tc_write_rc( tc, configTICK_TC_CHANNEL, ( configPBA_CLOCK_HZ + 4 * configTICK_RATE_HZ ) /
    00388                                                 ( 8 * configTICK_RATE_HZ ) );
    00389
    00390         tc_configure_interrupts( tc, configTICK_TC_CHANNEL, &tc_interrupt );
    00391
    00392         /* Start the timer/counter. */
    00393         tc_start(tc, configTICK_TC_CHANNEL);
    00394     }
    00395     #else
    00396     {
    00397         INTC_register_interrupt((__int_handler)&vTick, AVR32_CORE_COMPARE_IRQ, AVR32_INTC_INT0);
    00398         prvScheduleFirstTick();
    00399     }
    00400     #endif
    00401 }

void* pvPortRealloc | ( | void * | pv,
|  | size_t | xWantedSize |
| ) |  |  |

Definition at line 158 of file IAR/AVR32_UC3/port.c.

    00159 {
    00160 void *pvReturn;
    00161
    00162     vTaskSuspendAll();
    00163     {
    00164         pvReturn = realloc( pv, xWantedSize );
    00165     }
    00166     xTaskResumeAll();
    00167
    00168     return pvReturn;
    00169 }

portSTACK_TYPE* pxPortInitialiseStack | ( | portSTACK_TYPE * | pxTopOfStack,
|  | pdTASK_CODE | pxCode,
|  | void * | pvParameters |
| ) |  |  |

Definition at line 249 of file IAR/AVR32_UC3/port.c.

References portINITIAL_SR, portINSTRUCTION_SIZE, and portNO_CRITICAL_NESTING.

    00250 {
    00251     /* Setup the initial stack of the task.  The stack is set exactly as
    00252     expected by the portRESTORE_CONTEXT() macro. */
    00253
    00254     /* When the task starts, it will expect to find the function parameter in R12. */
    00255     pxTopOfStack--;
    00256     *pxTopOfStack-- = ( portSTACK_TYPE ) 0x08080808;                    /* R8 */
    00257     *pxTopOfStack-- = ( portSTACK_TYPE ) 0x09090909;                    /* R9 */
    00258     *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0A0A0A0A;                    /* R10 */
    00259     *pxTopOfStack-- = ( portSTACK_TYPE ) 0x0B0B0B0B;                    /* R11 */
    00260     *pxTopOfStack-- = ( portSTACK_TYPE ) pvParameters;                  /* R12 */
    00261     *pxTopOfStack-- = ( portSTACK_TYPE ) 0xDEADBEEF;                    /* R14/LR */
    00262     *pxTopOfStack-- = ( portSTACK_TYPE ) pxCode + portINSTRUCTION_SIZE; /* R15/PC */
    00263     *pxTopOfStack-- = ( portSTACK_TYPE ) portINITIAL_SR;                /* SR */
    00264     *pxTopOfStack-- = ( portSTACK_TYPE ) 0xFF0000FF;                    /* R0 */
    00265     *pxTopOfStack-- = ( portSTACK_TYPE ) 0x01010101;                    /* R1 */
    00266     *pxTopOfStack-- = ( portSTACK_TYPE ) 0x02020202;                    /* R2 */
    00267     *pxTopOfStack-- = ( portSTACK_TYPE ) 0x03030303;                    /* R3 */
    00268     *pxTopOfStack-- = ( portSTACK_TYPE ) 0x04040404;                    /* R4 */
    00269     *pxTopOfStack-- = ( portSTACK_TYPE ) 0x05050505;                    /* R5 */
    00270     *pxTopOfStack-- = ( portSTACK_TYPE ) 0x06060606;                    /* R6 */
    00271     *pxTopOfStack-- = ( portSTACK_TYPE ) 0x07070707;                    /* R7 */
    00272     *pxTopOfStack = ( portSTACK_TYPE ) portNO_CRITICAL_NESTING;         /* ulCriticalNesting */
    00273
    00274     return pxTopOfStack;
    00275 }

void SCALLYield | ( | void |  | ) |

Definition at line 202 of file IAR/AVR32_UC3/port.c.

    00203 {
    00204     /* Save the context of the interrupted task. */
    00205     portSAVE_CONTEXT_SCALL();
    00206     vTaskSwitchContext();
    00207     portRESTORE_CONTEXT_SCALL();
    00208 }

void vPortEndScheduler | ( | void |  | ) |

Definition at line 292 of file IAR/AVR32_UC3/port.c.

    00293 {
    00294     /* It is unlikely that the AVR32 port will require this function as there
    00295     is nothing to return to.  */
    00296 }

void vPortEnterCritical | ( | void |  | ) |

Definition at line 216 of file IAR/AVR32_UC3/port.c.

References ulCriticalNesting.

    00217 {
    00218     /* Disable interrupts */
    00219     portDISABLE_INTERRUPTS();
    00220
    00221     /* Now interrupts are disabled ulCriticalNesting can be accessed
    00222      directly.  Increment ulCriticalNesting to keep a count of how many times
    00223      portENTER_CRITICAL() has been called. */
    00224     ulCriticalNesting++;
    00225 }

void vPortExitCritical | ( | void |  | ) |

Definition at line 229 of file IAR/AVR32_UC3/port.c.

References portNO_CRITICAL_NESTING, and ulCriticalNesting.

    00230 {
    00231     if(ulCriticalNesting > portNO_CRITICAL_NESTING)
    00232     {
    00233         ulCriticalNesting--;
    00234         if( ulCriticalNesting == portNO_CRITICAL_NESTING )
    00235         {
    00236             /* Enable all interrupt/exception. */
    00237             portENABLE_INTERRUPTS();
    00238         }
    00239     }
    00240 }

static void vTick | ( | void |  | ) | `[static]`

Definition at line 177 of file IAR/AVR32_UC3/port.c.

References prvClearCcInt().

    00178 {
    00179     /* Save the context of the interrupted task. */
    00180     portSAVE_CONTEXT_OS_INT();
    00181
    00182     #if( configTICK_USE_TC==1 )
    00183         /* Clear the interrupt flag. */
    00184         prvClearTcInt();
    00185     #else
    00186         /* Clear the interrupt flag. */
    00187         prvClearCcInt();
    00188     #endif
    00189
    00190     /* Because FreeRTOS is not supposed to run with nested interrupts, put all OS
    00191     calls in a critical section . */
    00192     portENTER_CRITICAL();
    00193         vTaskIncrementTick();
    00194     portEXIT_CRITICAL();
    00195
    00196     /* Restore the context of the "elected task". */
    00197     portRESTORE_CONTEXT_OS_INT();
    00198 }

portBASE_TYPE xPortStartScheduler | ( | void |  | ) |

Definition at line 278 of file IAR/AVR32_UC3/port.c.

References prvSetupTimerInterrupt().

    00279 {
    00280     /* Start the timer that generates the tick ISR.  Interrupts are disabled
    00281     here already. */
    00282     prvSetupTimerInterrupt();
    00283
    00284     /* Start the first task. */
    00285     portRESTORE_CONTEXT();
    00286
    00287     /* Should not get here! */
    00288     return 0;
    00289 }

## Variable Documentation

volatile unsigned portLONG ulCriticalNesting = 9999UL

Definition at line 83 of file IAR/AVR32_UC3/port.c.