dac.c

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/* Copyright (c) 2007, Atmel Corporation All rights reserved.
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#include "dac.h"

void abdac_enable(volatile avr32_abdac_t *abdac)
{
    volatile avr32_pm_t *pm = &AVR32_PM;
    pm->gcctrl[ABDAC_GCLK] |= GCLK_BIT(CEN);
    abdac->cr |= ABDAC_BIT(CR_EN);
}

void abdac_disable(volatile avr32_abdac_t *abdac)
{
    volatile avr32_pm_t *pm = &AVR32_PM;
    abdac->cr &= ~ABDAC_BIT(CR_EN);
    pm->gcctrl[ABDAC_GCLK] &= ~GCLK_BIT(CEN);
}

unsigned long abdac_set_dac_hz(volatile avr32_abdac_t *abdac,
        const unsigned long bus_hz, const unsigned long dac_hz)
{
    volatile avr32_pm_t *pm = &AVR32_PM;
    unsigned short div;

    if (bus_hz < (256 * dac_hz)) {
        return -EINVAL;
    }

    div = bus_hz / (256 * dac_hz);

    /* div must be a power of 2. */
    div = (div + 1) & ~1UL;

    if (div > 2) {
        pm->gcctrl[ABDAC_GCLK] = GCLK_BIT(DIVEN) | GCLK_BF(DIV, ((div / 2) - 1));
    } else {
        pm->gcctrl[ABDAC_GCLK] = GCLK_BIT(DIVEN);
    }

    return (bus_hz / (256 * div));
}

unsigned long abdac_get_dac_hz(volatile avr32_abdac_t *abdac,
        const unsigned long bus_hz)
{
    volatile avr32_pm_t *pm = &AVR32_PM;
    unsigned short div = 0;

    if (pm->gcctrl[ABDAC_GCLK] & GCLK_BIT(DIVEN)) {
        div = 2 * (GCLK_BFEXT(DIV, pm->gcctrl[ABDAC_GCLK]) + 1);
    }

    return (bus_hz / div);
}

int abdac_sink(volatile avr32_abdac_t *abdac,
        const unsigned short ch0, const unsigned short ch1)
{
    volatile unsigned long timeout = ABDAC_TIMEOUT;

    do {
    } while (!(abdac->isr & ABDAC_BIT(ISR_TX_READY)) && timeout--);

    if (0 == timeout) {
        return -ETIMEOUT;
    }

    abdac->sdr = ABDAC_BF(SDR_CHANNEL0, ch0) | ABDAC_BF(SDR_CHANNEL1, ch1);

    return 0;
}

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