#include <lcdc.h>
Definition at line 62 of file lcdc.h.
Data Fields | |
| unsigned char | burst_length |
| Burst length of DMA controller. | |
| unsigned char | clkmod |
| Pixel clock mode. | |
| unsigned char | ctrst_ena |
| Contrast PWM generator enable. | |
| unsigned char | ctrst_pol |
| Contrast PWM polarity This value defines the polarity of the contrast PWM output. If NORMAL, the output pulses are high level (the output will be high whenever the value in the counter is less than the value in the compare register CONTRAST_VAL ctrstval ). If INVERTED, the output pulses are low level. | |
| unsigned char | ctrst_ps |
| Contrast PWM prescaler This Prescaler divides the LCD controller clock for the contrast PWM generator. | |
| unsigned char | ctrstval |
| Contrast value PWM compare value used to adjust the analog value obtained after an external filter to control the contrast of the display. | |
| unsigned char | distype |
| Display type. | |
| unsigned int | dmabaddr1 |
| Base address for the upper panel (in dual scan mode) or complete frame. | |
| unsigned int | dmabaddr2 |
| Base address of lower panel (dual scan mode only. | |
| unsigned short | frame_rate |
| Frame rate of the display. | |
| unsigned short | guard_time |
| Delay in frame periods between applying control signals to the LCD module and setting PWR high, and between setting PWR low and removing control signals from LCD module. | |
| unsigned char | hbp |
| Horizontal back porch Number of idle pixel clock cycles at the beginning of the line. Idle period is (HBP+1) pixel clock cycles. | |
| unsigned char | hfp |
| Horizontal front porch Number of idle pixel clock cycles at the end of the line. Idle period is (HFP+1) pixel clock cycles. | |
| unsigned short | hpw |
| Horizontal sync pulse width Width of the HSYNC pulse, given in pixel clock cycles. Width is (HPW+1) PCLK cycles. | |
| unsigned char | ifwidth |
| Interface width (only valid for STN mode). | |
| unsigned char | invclk |
| Pixel clock polarity. | |
| unsigned char | invdval |
| Data valid polarity. | |
| unsigned char | invframe |
| Vertical sync polarity. | |
| unsigned char | invline |
| Horizontal sync polarity. | |
| unsigned char | invvd |
| Data polarity. | |
| unsigned int | lcdcclock |
| LCD controller clock Frequency in MHz at which the LCD module runs. This can be set in the generic clock setup. | |
| unsigned char | memor |
| Memory organization. | |
| unsigned char | mmode |
| Toggle rate Toggle the polarity after each frame (EACH_FRAME) or by a specified value (MVAL_DEFINED). | |
| unsigned char | mval |
| Toggle rate value. If Toggle rate is set to MVAL_DEFINED this value sets toggle rate to mval + 1 line periods. | |
| unsigned char | pixelsize |
| Bits per pixel. | |
| unsigned char | scanmod |
| Scan mode. | |
| unsigned char | set2dmode |
| Enables or disables the 2D addressing mode If 2D addressing is activated the values in virtual_xres and virtual_yres must be set according to the virtual frame size. | |
| unsigned char | vbp |
| Vertical back porch In TFT mode, these bits equal the number of idle lines at the beginning of the frame. In STN mode, these bits should be set to 0. | |
| unsigned char | vfp |
| Vertical front porch In TFT mode, these bits equal the number of idle lines at the end of the frame. In STN mode, these bits should be set to 0. | |
| unsigned char | vhdly |
| Vertical to horizontal delay In TFT mode, this is the delay between VSYNC rising or falling edge and HSYNC rising edge. Delay is (VHDLY+1) pixel clock cycles. In STN mode, these bits should be set to 0. | |
| unsigned int | virtual_xres |
| Virtual horizontal size of the display (in pixels) Use this in 2D addressing mode to set the size of the frame buffer. | |
| unsigned int | virtual_yres |
| Virtual vertical size of the display (in pixels) Use this value in 2D addressing mode to set the size of the frame buffer. | |
| unsigned char | vpw |
| Vertical sync pulse width In TFT mode, these bits equal the vertical synchronization pulse width, given in number of lines. VSYNC width is equal to (VPW+1) lines. In STN mode, these bits should be set to 0. | |
| unsigned short | xres |
| Number of columns on the display (in pixels). | |
| unsigned short | yres |
| Number of rows on the display (in pixels). | |
| unsigned char lcdc_conf_t::burst_length |
| unsigned char lcdc_conf_t::clkmod |
Pixel clock mode.
Definition at line 162 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::ctrst_ena |
Contrast PWM generator enable.
Definition at line 203 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::ctrst_pol |
Contrast PWM polarity This value defines the polarity of the contrast PWM output. If NORMAL, the output pulses are high level (the output will be high whenever the value in the counter is less than the value in the compare register CONTRAST_VAL ctrstval ). If INVERTED, the output pulses are low level.
Definition at line 197 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::ctrst_ps |
Contrast PWM prescaler This Prescaler divides the LCD controller clock for the contrast PWM generator.
Definition at line 188 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::ctrstval |
Contrast value PWM compare value used to adjust the analog value obtained after an external filter to control the contrast of the display.
Definition at line 179 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::distype |
Display type.
Definition at line 128 of file lcdc.h.
Referenced by lcdc_init().
| unsigned int lcdc_conf_t::dmabaddr1 |
Base address for the upper panel (in dual scan mode) or complete frame.
Definition at line 64 of file lcdc.h.
Referenced by fill_frame_buffer(), fill_frame_buffer_bm(), fill_virtual_frame_buffer_bm(), increment_frame_base(), lcdc_init(), and main().
| unsigned int lcdc_conf_t::dmabaddr2 |
Base address of lower panel (dual scan mode only.
Definition at line 66 of file lcdc.h.
Referenced by lcdc_init().
| unsigned short lcdc_conf_t::frame_rate |
| unsigned short lcdc_conf_t::guard_time |
Delay in frame periods between applying control signals to the LCD module and setting PWR high, and between setting PWR low and removing control signals from LCD module.
Definition at line 102 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::hbp |
Horizontal back porch Number of idle pixel clock cycles at the beginning of the line. Idle period is (HBP+1) pixel clock cycles.
Definition at line 227 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::hfp |
Horizontal front porch Number of idle pixel clock cycles at the end of the line. Idle period is (HFP+1) pixel clock cycles.
Definition at line 232 of file lcdc.h.
Referenced by lcdc_init().
| unsigned short lcdc_conf_t::hpw |
Horizontal sync pulse width Width of the HSYNC pulse, given in pixel clock cycles. Width is (HPW+1) PCLK cycles.
Definition at line 222 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::ifwidth |
Interface width (only valid for STN mode).
Definition at line 117 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::invclk |
Pixel clock polarity.
Definition at line 150 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::invdval |
Data valid polarity.
Definition at line 156 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::invframe |
Vertical sync polarity.
Definition at line 139 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::invline |
Horizontal sync polarity.
Definition at line 145 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::invvd |
| unsigned int lcdc_conf_t::lcdcclock |
LCD controller clock Frequency in MHz at which the LCD module runs. This can be set in the generic clock setup.
Definition at line 99 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::memor |
Memory organization.
Definition at line 110 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::mmode |
Toggle rate Toggle the polarity after each frame (EACH_FRAME) or by a specified value (MVAL_DEFINED).
Definition at line 210 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::mval |
Toggle rate value. If Toggle rate is set to MVAL_DEFINED this value sets toggle rate to mval + 1 line periods.
Definition at line 217 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::pixelsize |
Bits per pixel.
Definition at line 173 of file lcdc.h.
Referenced by fill_frame_buffer(), fill_frame_buffer_bm(), increment_frame_base(), lcdc_init(), and main().
| unsigned char lcdc_conf_t::scanmod |
| unsigned char lcdc_conf_t::set2dmode |
Enables or disables the 2D addressing mode If 2D addressing is activated the values in virtual_xres and virtual_yres must be set according to the virtual frame size.
Definition at line 80 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::vbp |
Vertical back porch In TFT mode, these bits equal the number of idle lines at the beginning of the frame. In STN mode, these bits should be set to 0.
Definition at line 243 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::vfp |
Vertical front porch In TFT mode, these bits equal the number of idle lines at the end of the frame. In STN mode, these bits should be set to 0.
Definition at line 248 of file lcdc.h.
Referenced by lcdc_init().
| unsigned char lcdc_conf_t::vhdly |
Vertical to horizontal delay In TFT mode, this is the delay between VSYNC rising or falling edge and HSYNC rising edge. Delay is (VHDLY+1) pixel clock cycles. In STN mode, these bits should be set to 0.
Definition at line 254 of file lcdc.h.
Referenced by lcdc_init().
| unsigned int lcdc_conf_t::virtual_xres |
Virtual horizontal size of the display (in pixels) Use this in 2D addressing mode to set the size of the frame buffer.
Definition at line 85 of file lcdc.h.
Referenced by increment_frame_base(), lcdc_init(), and main().
| unsigned int lcdc_conf_t::virtual_yres |
Virtual vertical size of the display (in pixels) Use this value in 2D addressing mode to set the size of the frame buffer.
Definition at line 90 of file lcdc.h.
Referenced by increment_frame_base(), and main().
| unsigned char lcdc_conf_t::vpw |
Vertical sync pulse width In TFT mode, these bits equal the vertical synchronization pulse width, given in number of lines. VSYNC width is equal to (VPW+1) lines. In STN mode, these bits should be set to 0.
Definition at line 238 of file lcdc.h.
Referenced by lcdc_init().
| unsigned short lcdc_conf_t::xres |
Number of columns on the display (in pixels).
Definition at line 70 of file lcdc.h.
Referenced by fill_frame_buffer(), fill_frame_buffer_bm(), lcdc_init(), and main().
| unsigned short lcdc_conf_t::yres |
Number of rows on the display (in pixels).
Definition at line 72 of file lcdc.h.
Referenced by fill_frame_buffer(), increment_frame_base(), lcdc_init(), and main().
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