sdram.h File Reference

#include <avr32/io.h>
#include "errno.h"

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Data Structures
struct	sdram_info
Defines
#define	MODE_AUTOREFRESH   4
#define	MODE_EXT_LOAD_MR   5
#define	MODE_LOAD_MR   3
#define	MODE_NOP   1
#define	MODE_NORMAL   0
#define	MODE_POWER_DOWN   6
#define	MODE_PRECHARGE   2
Functions
int	sdram_init (const sdram_info *info)

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Define Documentation

#define MODE_AUTOREFRESH   4

SDRAMC operation mode: Auto refresh

Definition at line 65 of file sdram.h.

#define MODE_EXT_LOAD_MR   5

SDRAMC operation mode: Extended Load

Definition at line 70 of file sdram.h.

#define MODE_LOAD_MR   3

SDRAMC operation mode: Load Mode Register

Definition at line 60 of file sdram.h.

#define MODE_NOP   1

SDRAMC operation mode: NO OP

Definition at line 50 of file sdram.h.

#define MODE_NORMAL   0

SDRAMC operation mode: Normal operation

Definition at line 45 of file sdram.h.

#define MODE_POWER_DOWN   6

SDRAMC operation mode: Power Down

Definition at line 75 of file sdram.h.

#define MODE_PRECHARGE   2

SDRAMC operation mode: Precharge

Definition at line 55 of file sdram.h.

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Function Documentation

int sdram_init

(

const sdram_info *

info

)

This function will initialize the AVR32 SDRAM Controller

Parameters:

*info

The setup and timing variables for the controller

Returns:

Nothing

Definition at line 56 of file sdram.c.

References sdram_info::banks, sdram_info::bus_width, sdram_info::cas, sdram_info::cols, sdram_info::rows, sdram, sdram_delay(), SUCCESS, sdram_info::tras, sdram_info::trc, sdram_info::trcd, sdram_info::trp, sdram_info::twr, and sdram_info::txsr.

Referenced by mt481c2m32b2tg_init().

{
        volatile avr32_sdramc_t *sdram = &AVR32_SDRAMC;
        volatile avr32_hmatrix_t *hmatrix = &AVR32_HMATRIX;
        volatile avr32_pio_t *pio = &AVR32_PIOE;

        /* Enable SDRAM mode for CS1 in the BAMBI mux */
        hmatrix->sfr[AVR32_SDRAMC_HMATRIX_NR] |= 0x0002;
        hmatrix->sfr[AVR32_SDRAMC_HMATRIX_NR] |= 0x0100;

        /* Setup SDRAM info */
        sdram->cr = ( (info->cols-8) << AVR32_SDRAMC_CR_NC ) |
                ( (info->rows-11) << AVR32_SDRAMC_CR_NR ) |
                ( (info->banks-1) << AVR32_SDRAMC_CR_NB ) |
                ( info->cas << AVR32_SDRAMC_CR_CAS ) |
                ( info->twr << AVR32_SDRAMC_CR_TWR ) |
                ( info->trc << AVR32_SDRAMC_CR_TRC ) |
                ( info->trp << AVR32_SDRAMC_CR_TRP ) |
                ( info->trcd << AVR32_SDRAMC_CR_TRCD ) |
                ( info->tras << AVR32_SDRAMC_CR_TRAS ) |
                ( info->txsr << AVR32_SDRAMC_CR_TXSR );

        if(info->bus_width == 16 ){
                sdram->cr = 1<<AVR32_SDRAMC_CR_DBW_OFFSET;
        } else if ( info->bus_width == 32 ) {
                // Initialize data bus bits 31-16 (muxed with the LCDC).
                pio->asr |= 0x0000FFFF;
                pio->pdr |= 0x0000FFFF;
        }

        sdram_delay(400);

        return SUCCESS;
}

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