#include "sdram.h"
Go to the source code of this file.
Defines | |
| #define | MODE_AUTOREFRESH 4 |
| #define | MODE_EXT_LOAD_MR 5 |
| #define | MODE_LOAD_MR 3 |
| #define | MODE_NOP 1 |
| #define | MODE_NORMAL 0 |
| #define | MODE_POWER_DOWN 6 |
| #define | MODE_PRECHARGE 2 |
Functions | |
| static void | sdram_delay (int us) |
| int | sdram_init (const sdram_info *info) |
| #define MODE_AUTOREFRESH 4 |
| #define MODE_LOAD_MR 3 |
| #define MODE_NORMAL 0 |
| #define MODE_PRECHARGE 2 |
| static void sdram_delay | ( | int | us | ) | [static] |
Definition at line 46 of file sdram.c.
Referenced by sdram_init().
00047 { 00048 volatile int i, loop_limit; 00049 00050 loop_limit = us * 100; 00051 for (i=0; i<loop_limit;i++) 00052 asm volatile("nop"); 00053 00054 }
| int sdram_init | ( | const sdram_info * | info | ) |
This function will initialize the AVR32 SDRAM Controller
| *info | The setup and timing variables for the controller |
Definition at line 56 of file sdram.c.
References sdram_info::banks, sdram_info::bus_width, sdram_info::cas, sdram_info::cols, sdram_info::rows, sdram, sdram_delay(), SUCCESS, sdram_info::tras, sdram_info::trc, sdram_info::trcd, sdram_info::trp, sdram_info::twr, and sdram_info::txsr.
Referenced by mt481c2m32b2tg_init().
00057 { 00058 volatile avr32_sdramc_t *sdram = &AVR32_SDRAMC; 00059 volatile avr32_hmatrix_t *hmatrix = &AVR32_HMATRIX; 00060 volatile avr32_pio_t *pio = &AVR32_PIOE; 00061 00062 /* Enable SDRAM mode for CS1 in the BAMBI mux */ 00063 hmatrix->sfr[AVR32_SDRAMC_HMATRIX_NR] |= 0x0002; 00064 hmatrix->sfr[AVR32_SDRAMC_HMATRIX_NR] |= 0x0100; 00065 00066 /* Setup SDRAM info */ 00067 sdram->cr = ( (info->cols-8) << AVR32_SDRAMC_CR_NC ) | 00068 ( (info->rows-11) << AVR32_SDRAMC_CR_NR ) | 00069 ( (info->banks-1) << AVR32_SDRAMC_CR_NB ) | 00070 ( info->cas << AVR32_SDRAMC_CR_CAS ) | 00071 ( info->twr << AVR32_SDRAMC_CR_TWR ) | 00072 ( info->trc << AVR32_SDRAMC_CR_TRC ) | 00073 ( info->trp << AVR32_SDRAMC_CR_TRP ) | 00074 ( info->trcd << AVR32_SDRAMC_CR_TRCD ) | 00075 ( info->tras << AVR32_SDRAMC_CR_TRAS ) | 00076 ( info->txsr << AVR32_SDRAMC_CR_TXSR ); 00077 00078 if(info->bus_width == 16 ){ 00079 sdram->cr = 1<<AVR32_SDRAMC_CR_DBW_OFFSET; 00080 } else if ( info->bus_width == 32 ) { 00081 // Initialize data bus bits 31-16 (muxed with the LCDC). 00082 pio->asr |= 0x0000FFFF; 00083 pio->pdr |= 0x0000FFFF; 00084 } 00085 00086 sdram_delay(400); 00087 00088 return SUCCESS; 00089 }
1.5.3-20071008