lcdc_vga_example.c

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/* Copyright (c) 2007, Atmel Corporation All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are met:
 *
 * 1. Redistributions of source code must retain the above copyright notice,
 * this list of conditions and the following disclaimer.
 *
 * 2. Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
 * 3. The name of ATMEL may not be used to endorse or promote products derived
 * from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
 * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 */
#include "usart.h"
#include "pio.h"
#include "lcdc.h"
#include <string.h>
#include <avr32/io.h>
#include "sdram.h"
#include "errno.h"


/* Enable disable the display configurations here */
/* #define CONF_640_480_60 */
#define CONF_800_600_60
/* #define CONF_1024_768_60 */

#define BITMAP_FILE_ADDRESS 0xA0400000

#define CPU_FAMILY      "AVR32_AP"
#define CPU_TYPE        "AT32AP7000"
#define MAX_FREQ        150000000

#define DEFAULT_FREQ    OSC0_FREQ
#define DEFAULT_UART    UART_A

/* Define the on-board oscillators in Hz */
#define OSC0_FREQ       20000000
#define OSC1_FREQ       12000000

/* Timeout for PLL */
#define PLL_TIMEOUT 500000 
/* Define the on-board memory sizes */
#define SDRAM_SIZE      8

/* Define the peripheral names */
#define UART_A  AVR32_USART1
#define UART_C  AVR32_USART3
#define IRDA    AVR32_USART2

/* Refresh rate of SDRAM in number of bus clocks */ 
#define REFRESH_RATE 1170

static const struct sdram_info sdram = {
        .phys_addr      = AVR32_EBI1_ADDRESS,
        .bus_width      = 32,
        .rows           = 11,
        .cols           = 8,
        .banks          = 2,
        .cas            = 3,
        .twr            = 2,
        .trc            = 7,
        .trp            = 2,
        .trcd           = 2,
        .tras           = 5,
        .txsr           = 5,
};

volatile avr32_usart_t *usart = &AVR32_USART1;
int display_bm(lcdc_conf_t *lcdc_conf, void * file_start);

void usart_print(volatile struct avr32_usart_t * usart, char *str)
{
        while (*str != '\0')
                usart_putchar(usart, *str++);
}

void usart_printHex(volatile avr32_usart_t * usart, const unsigned long n)
{
        char tmp[9];
        int i;

        for (i = 0; i < 8; i++) {
                unsigned long nibble;

                nibble = (n >> (28 - 4 * i)) & 0x0F;

                if (nibble < 10) {
                        tmp[i] = nibble + '0';
                } else {
                        tmp[i] = nibble - 10 + 'a';
                }
        }

        tmp[8] = 0;
        usart_print(usart, tmp);
}

static int mt481c2m32b2tg_init(const sdram_info *info)
{
        volatile unsigned long *sdram = (unsigned long *) info->phys_addr;
        volatile avr32_sdramc_t *sdramc = &AVR32_SDRAMC;
        unsigned long dummy_read;
        unsigned int i;

        if ( sdram_init(info) )
                return INVALID_ARGUMENT;

        /* Precharge All command is issued to the SDRAM */
        sdramc->mr = MODE_PRECHARGE;
        dummy_read = sdramc->mr;
        sdram[0] = 0;

        /* Provide eight auto-refresh (CBR) cycles */
        sdramc->mr = MODE_AUTOREFRESH;
        dummy_read = sdramc->mr;
        for (i = 0; i < 8; i++)
        {
                sdram[0] = 0;
        }
        
        /* CAS from info struct, burst length 1, serial burst type */
        sdramc->mr = MODE_LOAD_MR;
        dummy_read = sdramc->mr;
        sdram[0x020] = 0;

        /* A Normal Mode command is provided, 3 clocks after tMRD is met. */
        dummy_read = sdramc->mr;
        sdramc->mr = MODE_NORMAL;
        dummy_read = sdramc->mr;
        sdram[0] = 0;
        
        /* Write refresh rate into SDRAMC refresh timer count register */
        sdramc->tr = REFRESH_RATE;

        return SUCCESS;
}

static int init_uart_a(int module_frequ)
{ 
        struct usart_options_t opt;
        volatile struct avr32_usart_t *usart = &AVR32_USART1;

        avr32_piomap_t usart_piomap = {                            \
                {AVR32_USART1_RXD_0_PIN, AVR32_USART1_RXD_0_FUNCTION}, \
                {AVR32_USART1_TXD_0_PIN, AVR32_USART1_TXD_0_FUNCTION}   \
        };

        /* Set options for the USART */
        opt.baudrate = 115200;
        opt.charlength = 8;
        opt.paritytype = USART_NO_PARITY;
        opt.stopbits = USART_1_STOPBIT;
        opt.channelmode = USART_NORMAL_CHMODE;

        /* Initialize it in RS232 mode */
        if(usart_init_rs232(usart, &opt, module_frequ ) )
                return INVALID_ARGUMENT;

        /* Setup pio for USART */
        pio_enable_module(usart_piomap, 2);

        return SUCCESS;
}

int board_init( void )
{
        volatile struct avr32_usart_t *usart = &AVR32_USART1;
        volatile struct avr32_pm_t *pm = &AVR32_PM;
        volatile struct avr32_smc_t * smc = &AVR32_SMC;
        volatile struct avr32_hmatrix_t * phm = &AVR32_HMATRIX;
        unsigned int timeout = PLL_TIMEOUT;

        /* Initialize USART */
        if(init_uart_a(20000000))
                return INVALID_ARGUMENT;
        usart_print(usart, "STK1000 initialization:\n");
        usart_print(usart, " -> USART ... OK\n");
        /* reset usart before clock change */
        usart_reset(usart);

        
        /* SLOT_CYCLE -> max burst cycles (slow bursts can be broken)
        * DEFMSTR_TYPE -> 0 No default master, 1 last default master, 
        * 2 fixed master
        * FIXED_DEFMSTR -> master number (5 = LCD Controller)
        * ARBT -> 0 round robin, 1 fixed priority
        */
        
        phm->scfg[4] = ((16 << AVR32_HMATRIX_SCFG4_SLOT_CYCLE_OFFSET) 
                & AVR32_HMATRIX_SCFG4_SLOT_CYCLE_MASK) 
                | ((2 << AVR32_HMATRIX_SCFG4_DEFMSTR_TYPE_OFFSET) 
                & AVR32_HMATRIX_SCFG4_DEFMSTR_TYPE_OFFSET) 
                | ((5 << AVR32_HMATRIX_SCFG4_FIXED_DEFMSTR_OFFSET 
                & AVR32_HMATRIX_SCFG4_FIXED_DEFMSTR_OFFSET)) 
                | ((1 << AVR32_HMATRIX_SCFG4_ARBT_OFFSET));
        
        /* Set maximum priority to LCD Controller */
        phm->prs[4].pras = 0x00F00000;
                
        /* set up SMC for higher frequencies */
        smc->cs[0].mode = 0x00031103;
        smc->cs[0].cycle = 0x000c000d;
        smc->cs[0].pulse = 0x0b0a0906;
        smc->cs[0].setup = 0x00010002;
        
        pm->pll0 = (0 << AVR32_PM_PLL0_PLLOSC_OFFSET) 
                | ( (15 - 1) << AVR32_PM_PLL0_PLLMUL_OFFSET)
                | ( (2 - 1) << AVR32_PM_PLL0_PLLDIV_OFFSET) 
                | ( 16 << AVR32_PM_PLL0_PLLCOUNT_OFFSET) 
                | ( 0x4 << AVR32_PM_PLL0_PLLOPT_OFFSET) 
                | ( 1 << AVR32_PM_PLL0_PLLEN_OFFSET);
        
        /* Wait until pll has locked or a timeout elapsed*/
        while(!(pm->isr & (1 << AVR32_PM_ISR_LOCK0_OFFSET))
                && (timeout != 0)){
                timeout--;
        }
        
        if(timeout == 0){
                usart_print(usart, "ERROR: PLL did not lock");
                return -1;
        }

        pm->cksel = (1 << AVR32_PM_CKSEL_HSBDIV_OFFSET) 
                | ( 0 << AVR32_PM_CKSEL_HSBSEL_OFFSET) 
                | ( 1 << AVR32_PM_CKSEL_PBADIV_OFFSET) 
                | ( 1 << AVR32_PM_CKSEL_PBASEL_OFFSET) 
                | ( 1 << AVR32_PM_CKSEL_PBBDIV_OFFSET) 
                | ( 1 << AVR32_PM_CKSEL_PBBSEL_OFFSET);

        pm->mcctrl = 0x2;
        
        if(init_uart_a(37500000)) /* reinitialize due to clock change */
                return INVALID_ARGUMENT;
        usart_print(usart, "OK\n");
        
        /* Initialize SDRAMC */
        usart_print(usart, " -> SDRAM ... ");
        if (mt481c2m32b2tg_init(&sdram) )
                return ERROR;
        usart_print(usart, "OK\n");

        /* Done. Print frequency and return */
        usart_print(usart, "STK1000 is successfully initialized");

        return 0;
}
lcdc_conf_t lcdc_vga_std_conf = {
                
        dmabaddr1: 0x10000000,
        dmabaddr2: 0,
        burst_length: 4,
        xres: 640,
        yres: 480,
        set2dmode: MODE_2D_OFF,
        virtual_xres: 0,
        virtual_yres: 0,
        frame_rate: 60,
        lcdcclock: 25000000,
        guard_time: 2,
        memor: BIG_ENDIAN,
        ifwidth: 0,
        scanmod: SINGLE_SCAN,
        distype: TFT,
        invvd: NORMAL,
        invframe: NORMAL,
        invline: NORMAL,
        invclk: INVERTED,
        invdval: NORMAL,
        clkmod: ALWAYS_ACTIVE,
        pixelsize: BPP_24,
        ctrstval: 0x0f,
        ctrst_ena: DISABLED,
        ctrst_pol: NORMAL,
        ctrst_ps: PRE_HALF,
        mval: 0,
        mmode: EACH_FRAME,
        hpw: 64,/* Should be 96 but LCD Controller supports only up to 64 */
        hbp: 48,
        hfp: 16,
        vpw: 2, 
        vbp: 33,
        vfp: 10,
        vhdly: 0,
};
lcdc_conf_t lcdc_800_600_60_conf = {
                
        dmabaddr1: 0x10000000,
        dmabaddr2: 0,
        burst_length: 4,
        xres: 800,
        yres: 600,
        set2dmode: MODE_2D_OFF,
        virtual_xres: 0,
        virtual_yres: 0,
        frame_rate: 60,
        lcdcclock: 40000000,
        guard_time: 2,
        memor: BIG_ENDIAN,
        ifwidth: 0,
        scanmod: SINGLE_SCAN,
        distype: TFT,
        invvd: NORMAL,
        invframe: INVERTED,
        invline: NORMAL,
        invclk: INVERTED,
        invdval: NORMAL,
        clkmod: ALWAYS_ACTIVE,
        pixelsize: BPP_24,
        ctrstval: 0x0f,
        ctrst_ena: DISABLED,
        ctrst_pol: NORMAL,
        ctrst_ps: PRE_HALF,
        mval: 0,
        mmode: EACH_FRAME,
        hpw: 64, /* should be 80 but LCD Controller supports only up to 64 */
        hbp: 126,
        hfp: 46,
        vpw: 4, 
        vbp: 17,
        vfp: 3,
        vhdly: 0,
};
lcdc_conf_t lcdc_1024_768_60_conf = {
                
        dmabaddr1: 0x10000000,
        dmabaddr2: 0,
        burst_length: 4,
        xres: 1024,
        yres: 768,
        set2dmode: MODE_2D_OFF,
        virtual_xres: 0,
        virtual_yres: 0,
        frame_rate: 60,
        lcdcclock: 64000000,
        guard_time: 2,
        memor: BIG_ENDIAN,
        ifwidth: 0,
        scanmod: SINGLE_SCAN,
        distype: TFT,
        invvd: NORMAL,
        invframe: INVERTED,
        invline: NORMAL,
        invclk: INVERTED,
        invdval: NORMAL,
        clkmod: ALWAYS_ACTIVE,
        pixelsize: BPP_16,
        ctrstval: 0x0f,
        ctrst_ena: DISABLED,
        ctrst_pol: NORMAL,
        ctrst_ps: PRE_HALF,
        mval: 0,
        mmode: EACH_FRAME,
        hpw: 64, /* Should be 104 but LCD controller supports only up to 64 */
        hbp: 152,
        hfp: 48,
        vpw: 4, 
        vbp: 23,
        vfp: 3,
        vhdly: 0,
};

void lcdc_pio_config(void){
        /* CC and MOD signals are not used for the video DAC and are not connected to 
        * the monitor interface
        */
                avr32_piomap_t piomap = {
                        { AVR32_LCDC_DVAL_0_0_PIN, AVR32_LCDC_DVAL_0_0_FUNCTION },
                        { AVR32_LCDC_HSYNC_0_PIN, AVR32_LCDC_HSYNC_0_FUNCTION },
                        { AVR32_LCDC_PCLK_0_PIN, AVR32_LCDC_PCLK_0_FUNCTION },
                        { AVR32_LCDC_PWR_0_PIN, AVR32_LCDC_PWR_0_FUNCTION },
                        { AVR32_LCDC_VSYNC_0_PIN, AVR32_LCDC_VSYNC_0_FUNCTION },
                        { AVR32_LCDC_DATA_0_0_PIN, AVR32_LCDC_DATA_0_0_FUNCTION },
                        { AVR32_LCDC_DATA_1_0_PIN, AVR32_LCDC_DATA_1_0_FUNCTION },
                        { AVR32_LCDC_DATA_2_0_PIN, AVR32_LCDC_DATA_1_0_FUNCTION },
                        { AVR32_LCDC_DATA_3_0_PIN, AVR32_LCDC_DATA_1_0_FUNCTION },
                        { AVR32_LCDC_DATA_4_0_PIN, AVR32_LCDC_DATA_1_0_FUNCTION },
                        { AVR32_LCDC_DATA_5_PIN, AVR32_LCDC_DATA_5_FUNCTION },
                        { AVR32_LCDC_DATA_6_PIN, AVR32_LCDC_DATA_6_FUNCTION },
                        { AVR32_LCDC_DATA_7_PIN, AVR32_LCDC_DATA_7_FUNCTION },
                        { AVR32_LCDC_DATA_8_0_PIN, AVR32_LCDC_DATA_8_0_FUNCTION },
                        { AVR32_LCDC_DATA_9_0_PIN, AVR32_LCDC_DATA_9_0_FUNCTION },
                        { AVR32_LCDC_DATA_10_0_PIN, AVR32_LCDC_DATA_10_0_FUNCTION },
                        { AVR32_LCDC_DATA_11_0_PIN, AVR32_LCDC_DATA_11_0_FUNCTION },
                        { AVR32_LCDC_DATA_12_0_PIN, AVR32_LCDC_DATA_12_0_FUNCTION },
                        { AVR32_LCDC_DATA_13_PIN, AVR32_LCDC_DATA_13_FUNCTION },
                        { AVR32_LCDC_DATA_14_PIN, AVR32_LCDC_DATA_14_FUNCTION },
                        { AVR32_LCDC_DATA_15_PIN, AVR32_LCDC_DATA_15_FUNCTION },
                        { AVR32_LCDC_DATA_16_0_PIN, AVR32_LCDC_DATA_16_0_FUNCTION },
                        { AVR32_LCDC_DATA_17_0_PIN, AVR32_LCDC_DATA_17_0_FUNCTION },
                        { AVR32_LCDC_DATA_18_0_PIN, AVR32_LCDC_DATA_18_0_FUNCTION },
                        { AVR32_LCDC_DATA_19_0_PIN, AVR32_LCDC_DATA_19_0_FUNCTION },
                        { AVR32_LCDC_DATA_20_0_PIN, AVR32_LCDC_DATA_20_0_FUNCTION },
                        { AVR32_LCDC_DATA_21_0_PIN, AVR32_LCDC_DATA_21_0_FUNCTION },
                        { AVR32_LCDC_DATA_22_PIN, AVR32_LCDC_DATA_22_FUNCTION },
                        { AVR32_LCDC_DATA_23_PIN, AVR32_LCDC_DATA_23_FUNCTION }
                        
        };
        pio_enable_module(piomap, 31);
        
}
void fill_frame_buffer (lcdc_conf_t *lcdc_conf)
{
        
        unsigned int k,l,x,y;
        unsigned char * framePtr;
        unsigned short tmp;
        
        framePtr = (unsigned char *) (lcdc_conf->dmabaddr1 | 0xA0000000);
        
        if(lcdc_conf->pixelsize == BPP_24){
        for (l=0; l < lcdc_conf->yres; l++){
                for (k=0; k < lcdc_conf->xres; k++) 
                {
                        x = (255 * l) / lcdc_conf->yres;
                        y = (255 * k) / lcdc_conf->xres;
                        *framePtr++ = x;
                        *framePtr++ = y;
                        *framePtr++ = 255 - (x + y) / 2;
                }
        }
        }
        if(lcdc_conf->pixelsize == BPP_16){
                for (l=0; l < lcdc_conf->yres; l++){
                        for (k=0; k < lcdc_conf->xres; k++)
                        {
                                x = (32 * l) / lcdc_conf->yres;
                                y = (32 * k) / lcdc_conf->xres;
                                /* 1-5-5-5 format */
                                tmp =  (((32 - (x + y) / 2) << 10)& 0x0007C00) | ((y << 5) & 0x000003E0) | (x & 0x0000001F);
                                *framePtr = tmp;
                                framePtr += 2;
                        }
                }
        }
}
int main (void)
{
        volatile avr32_pm_t *pm = &AVR32_PM;
        lcdc_conf_t * lcdc_conf;
        unsigned char mul, div;
        
#ifdef CONF_640_480_60
        lcdc_conf = &lcdc_vga_std_conf;
        /* 25MHz pixel clock */
        mul = 25;
        div = 12;
#endif
#ifdef CONF_800_600_60
        lcdc_conf = &lcdc_800_600_60_conf;
        /* 40 MHz pixel clock */
        mul = 10;
        div = 3;
#endif
#ifdef CONF_1024_768_60
        lcdc_conf = &lcdc_1024_768_60_conf;
        /* 63,5 MHz pixel clock */
        mul = 37;
        div = 7;
#endif
        
        board_init();
        usart_print(usart, "board init complete\n");
        
        usart_print(usart, "Setting up PLL1 for LCD Controller\n");
        usart_print(usart, " -> PLL1 ... ");
        pm->pll1 = (1 << AVR32_PM_PLL1_PLLOSC_OFFSET) |
                                ( (mul - 1) << AVR32_PM_PLL1_PLLMUL_OFFSET) |
                                ( (div - 1) << AVR32_PM_PLL1_PLLDIV_OFFSET) |
                                ( 16 << AVR32_PM_PLL1_PLLCOUNT_OFFSET) |
                                ( 0x4 << AVR32_PM_PLL1_PLLOPT_OFFSET) |
                                ( 1 << AVR32_PM_PLL1_PLLEN_OFFSET);
                        
        while(!(pm->isr & (1 << AVR32_PM_ISR_LOCK1_OFFSET)));
        usart_print(usart, "OK\n");
        
        /* clear framebuffer */
        memset((void *)lcdc_conf->dmabaddr1, 0, lcdc_conf->xres * lcdc_conf->yres * lcdc_conf->pixelsize / 8);
        
        fill_frame_buffer(lcdc_conf);
        display_bm(lcdc_conf, ((void *) BITMAP_FILE_ADDRESS));
        
        usart_print(usart, "Setting up LCD controller\n");
        lcdc_pio_config();
        
        /* Power manager setup 
        * Enable CLOCK for LCDC in HSBMASK
        */
        pm->hsb_mask |= 0x00000080;
        /* Feed generic clock for LCD Controller from PLL1 */
        pm->gcctrl[7] |= 0x00000007;
        
        lcdc_init(lcdc_conf);
        usart_print(usart, "Setup complete\n");
        while(1);
        
        return 0;
}

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