#include "at32stk1000.h"
Go to the source code of this file.
Functions | |
| int | board_init (void) |
| static int | init_uart_a (void) |
| static int | mt481c2m32b2tg_init (const sdram_info *info) |
| void | usart_print (volatile struct avr32_usart_t *usart, char *str) |
| void | usart_printHex (volatile avr32_usart_t *usart, const unsigned long n) |
| int board_init | ( | void | ) |
Definition at line 130 of file at32stk1000.c.
Referenced by main().
00131 { 00132 volatile struct avr32_usart_t *usart = &AVR32_USART1; 00133 volatile struct pll_opt_t pll_opt; 00134 00135 /* Initialize USART */ 00136 if(init_uart_a()) 00137 return INVALID_ARGUMENT; 00138 usart_print(usart, "STK1000 initialization:\n"); 00139 usart_print(usart, " -> USART ... OK\n"); 00140 00141 00142 /* Setup PLL at 40 MHz */ 00143 usart_print(usart, " -> PLL0 ... "); 00144 pll_opt.oscillator=PM_OSC0; 00145 pll_opt.pll=PM_PLL0; 00146 pll_opt.multiplier=2; 00147 pll_opt.divider=1; 00148 pm_set_pll(&pll_opt); 00149 00150 pm_set_mclk_source(PM_PLL0); 00151 00152 if(init_uart_a()) /* reinitialize due to clock change */ 00153 return INVALID_ARGUMENT; 00154 usart_print(usart, "OK\n"); 00155 00156 /* Initialize SDRAMC */ 00157 usart_print(usart, " -> SDRAM ... "); 00158 if (mt481c2m32b2tg_init(&sdram) ) 00159 return ERROR; 00160 usart_print(usart, "OK\n"); 00161 00162 00163 /* Done. Print frequency and return */ 00164 usart_print(usart, "STK1000 is successfully initialized at 0x"); 00165 usart_printHex(usart, pm_read_mclk()/1000000 ); 00166 usart_print(usart, " MHz\n"); 00167 00168 return 0; 00169 }
| static int init_uart_a | ( | void | ) | [static] |
Definition at line 104 of file at32stk1000.c.
References usart_options_t::baudrate, usart_options_t::channelmode, usart_options_t::charlength, INVALID_ARGUMENT, usart_options_t::paritytype, pio_enable_module(), PM_PBA_USART1, pm_read_module_frequency(), usart_options_t::stopbits, SUCCESS, usart, USART_1_STOPBIT, usart_init_rs232(), USART_NO_PARITY, and USART_NORMAL_CHMODE.
Referenced by board_init().
00105 { 00106 struct usart_options_t opt; 00107 volatile struct avr32_usart_t *usart = &AVR32_USART1; 00108 00109 avr32_piomap_t usart_piomap = { \ 00110 {AVR32_USART1_RXD_0_PIN, AVR32_USART1_RXD_0_FUNCTION}, \ 00111 {AVR32_USART1_TXD_0_PIN, AVR32_USART1_TXD_0_FUNCTION} \ 00112 }; 00113 00114 opt.baudrate = 115200; 00115 opt.charlength = 8; 00116 opt.paritytype = USART_NO_PARITY; 00117 opt.stopbits = USART_1_STOPBIT; 00118 opt.channelmode = USART_NORMAL_CHMODE; 00119 00120 /* Initialize it in RS232 mode */ 00121 if(usart_init_rs232(usart, &opt, pm_read_module_frequency(PM_PBA_USART1) ) ) 00122 return INVALID_ARGUMENT; 00123 00124 /* Setup pio for USART */ 00125 pio_enable_module(usart_piomap, 2); 00126 00127 return SUCCESS; 00128 }
| static int mt481c2m32b2tg_init | ( | const sdram_info * | info | ) | [static] |
Definition at line 57 of file at32stk1000.c.
References INVALID_ARGUMENT, MODE_AUTOREFRESH, MODE_LOAD_MR, MODE_NORMAL, MODE_PRECHARGE, sdram_info::phys_addr, PM_HSB_SDRAMC, pm_read_module_frequency(), sdram, sdram_init(), and SUCCESS.
Referenced by board_init().
00058 { 00059 volatile unsigned long *sdram = (unsigned long *) info->phys_addr; 00060 volatile avr32_sdramc_t *sdramc = &AVR32_SDRAMC; 00061 unsigned long dummy_read; 00062 unsigned long busHz; 00063 unsigned int i; 00064 00065 if ( sdram_init(info) ) 00066 return INVALID_ARGUMENT; 00067 00068 /* Precharge All command is issued to the SDRAM */ 00069 sdramc->mr = MODE_PRECHARGE; 00070 dummy_read = sdramc->mr; 00071 sdram[0] = 0; 00072 00073 /* Provide eight auto-refresh (CBR) cycles */ 00074 sdramc->mr = MODE_AUTOREFRESH; 00075 dummy_read = sdramc->mr; 00076 for (i = 0; i < 8; i++) 00077 { 00078 sdram[0] = 0; 00079 } 00080 00081 /* A mode register set (MRS) cycle is issued to program 00082 * SDRAM parameters, in particular CAS latency and burst 00083 * length. 00084 */ 00085 00086 /* CAS from info struct, burst length 1, serial burst type */ 00087 sdramc->mr = MODE_LOAD_MR; 00088 dummy_read = sdramc->mr; 00089 sdram[0x020] = 0; 00090 00091 /* A Normal Mode command is provided, 3 clocks after tMRD is met. */ 00092 dummy_read = sdramc->mr; 00093 sdramc->mr = MODE_NORMAL; 00094 dummy_read = sdramc->mr; 00095 sdram[0] = 0; 00096 00097 /* Write refresh rate into SDRAMC refresh timer count register */ 00098 busHz = pm_read_module_frequency(PM_HSB_SDRAMC); 00099 sdramc->tr = ( ( 156 * (busHz / 1000) ) / 10000 ); 00100 00101 return SUCCESS; 00102 }
| void usart_print | ( | volatile struct avr32_usart_t * | usart, | |
| char * | str | |||
| ) |
Definition at line 29 of file at32stk1000.c.
Referenced by board_init(), ltv350qv_power_off(), ltv350qv_power_on(), main(), and usart_printHex().
00030 { 00031 while (*str != '\0') 00032 usart_putchar(usart, *str++); 00033 }
| void usart_printHex | ( | volatile avr32_usart_t * | usart, | |
| const unsigned long | n | |||
| ) |
Definition at line 36 of file at32stk1000.c.
Referenced by board_init().
00037 { 00038 char tmp[9]; 00039 int i; 00040 00041 for (i = 0; i < 8; i++) { 00042 unsigned long nibble; 00043 00044 nibble = (n >> (28 - 4 * i)) & 0x0F; 00045 00046 if (nibble < 10) { 00047 tmp[i] = nibble + '0'; 00048 } else { 00049 tmp[i] = nibble - 10 + 'a'; 00050 } 00051 } 00052 00053 tmp[8] = 0; 00054 usart_print(usart, tmp); 00055 }
1.5.3-20071008