spi.c

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/* Copyright (c) 2006, Atmel Corporation All rights reserved.
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 * 2. Redistributions in binary form must reproduce the above copyright notice,
 * this list of conditions and the following disclaimer in the documentation
 * and/or other materials provided with the distribution.
 *
 * 3. The name of ATMEL may not be used to endorse or promote products derived
 * from this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY ATMEL ``AS IS'' AND ANY EXPRESS OR IMPLIED
 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE EXPRESSLY AND
 * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
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#include "spi.h"

int getBaudDiv(struct spi_options_t * options, int cpuHz);


void spi_reset(volatile avr32_spi_t *spi)
{
    spi->cr = AVR32_SPI_CR_SWRST_MASK;
}


int spi_initSlave(volatile avr32_spi_t *spi,
        unsigned char bits,
        unsigned char spi_mode)
{
    /* Reset */
    spi->cr = AVR32_SPI_CR_SWRST_MASK;

    /* The number of bits and clock polarity/phase have to be set in
       csr0 for the SPI to communcate in slave mode */
    if (bits > 16 || bits < 8) {
        return SPI_ERROR_ARGUMENT;
    }

    spi->csr0 = (bits - 8) << AVR32_SPI_CSR0_BITS_OFFSET;

    switch (spi_mode) {
        case 0:
            spi->csr0 |= (1 << AVR32_SPI_CSR0_NCPHA_OFFSET);
        case 1:
            break;
        case 2:
            spi->csr0 |= (1<<AVR32_SPI_CSR0_NCPHA_OFFSET);
        case 3:
            spi->csr0 |= (1<<AVR32_SPI_CSR0_CPOL_OFFSET);
            break;
        default: /* Not in legal range */
            return SPI_ERROR_ARGUMENT;
    }

    return SPI_OK;
}


int spi_initTest(volatile avr32_spi_t *spi)
{
    /* Reset */
    spi->cr = AVR32_SPI_CR_SWRST_MASK;
    /* Master Mode */
    spi->mr |= AVR32_SPI_MR_MSTR_MASK;
    /* Local Loopback */
    spi->mr |= AVR32_SPI_MR_LLB_MASK;

    return SPI_OK;
}


int spi_initMaster(volatile avr32_spi_t *spi, struct spi_options_t *options)
{
    if (options->modfdis > 1 || options->fdiv > 1) {
        return SPI_ERROR_ARGUMENT;
    }

    /* Reset */
    spi->cr = AVR32_SPI_CR_SWRST_MASK;

    /* Master Mode */
    spi->mr = AVR32_SPI_MR_MSTR_MASK|
        AVR32_SPI_MR_PCS_MASK|
        (options->fdiv<<AVR32_SPI_MR_FDIV_OFFSET)|
        (options->modfdis<<AVR32_SPI_MR_MODFDIS_OFFSET);

    return SPI_OK;
}


int spi_selectionMode(volatile avr32_spi_t *spi,
        unsigned char variable_ps,
        unsigned char pcs_decode,
        unsigned char delay)
{
    if (variable_ps > 1 || pcs_decode > 1) {
        return SPI_ERROR_ARGUMENT;
    }

    /* Unset bitfields */
    spi->mr &= ~(AVR32_SPI_MR_PS_MASK|
            AVR32_SPI_MR_PCSDEC_MASK|
            AVR32_SPI_MR_DLYBCS_MASK);
    /* Set selction bits */
    spi->mr |=
        (variable_ps<<AVR32_SPI_MR_PS_OFFSET)|
        (pcs_decode<<AVR32_SPI_MR_PCSDEC_OFFSET)|
        (delay<<AVR32_SPI_MR_DLYBCS_OFFSET);

    return SPI_OK;
}


int spi_selectChip(volatile avr32_spi_t *spi, unsigned char chip)
{
    /* Assert all lines; no peripheral is selected */
    spi->mr |= AVR32_SPI_MR_PCS_MASK;

    if ((spi->mr & AVR32_SPI_MR_PCSDEC_MASK) != 0) {
        /* The signal is decoded; allow up to 15 chips */
        if (chip > 14) {
            return SPI_ERROR_ARGUMENT;
        }

        spi->mr = (spi->mr & ~AVR32_SPI_MR_PCS_MASK)|
            (chip << AVR32_SPI_MR_PCS_OFFSET);
    } else {
        if (chip > 3) {
            return SPI_ERROR_ARGUMENT;
        }

        spi->mr &= ~(1<<(AVR32_SPI_MR_PCS_OFFSET + chip));
    }

    return SPI_OK;
}


int spi_unselectChip(volatile avr32_spi_t *spi, unsigned char chip)
{
    /* Assert all lines; no peripheral is selected */
    spi->mr |= AVR32_SPI_MR_PCS_MASK;

    /* Last transfer, so deassert the current NPCS if CSAAT is set */
    spi->cr = AVR32_SPI_CR_LASTXFER_MASK;

    return SPI_OK;
}


int spi_setupChipReg(volatile avr32_spi_t *spi,
        struct spi_options_t *options,
        unsigned int cpuHz)
{
    int baudDiv = -1;
    unsigned long csr = 0;

    if (options->bits > 16 || options->bits < 8 || options->stay_act > 1) {
        return SPI_ERROR_ARGUMENT;
    }

    baudDiv = getBaudDiv(options, cpuHz);

    if (baudDiv < 0) {
        return -baudDiv;
    }

    /* Will use CSR0 offsets; these are the same for CSR0 - CSR3 */
    csr = ((options->bits - 8)<<AVR32_SPI_CSR0_BITS_OFFSET)|
        (baudDiv<<AVR32_SPI_CSR0_SCBR_OFFSET)|
        (options->spck_delay<<AVR32_SPI_CSR0_DLYBS_OFFSET)|
        (options->trans_delay<<AVR32_SPI_CSR0_DLYBCT_OFFSET)|
        (options->stay_act<<AVR32_SPI_CSR0_CSAAT_OFFSET);

    switch (options->spi_mode) {
        case 0:
            csr |= (1<<AVR32_SPI_CSR0_NCPHA_OFFSET);
        case 1:
            break;
        case 2:
            csr |= (1<<AVR32_SPI_CSR0_NCPHA_OFFSET);
        case 3:
            csr |= (1<<AVR32_SPI_CSR0_CPOL_OFFSET);
            break;
        default: /* Not in legal range */
            return SPI_ERROR_ARGUMENT;
    }

    switch (options->reg) {
        case 0:
            spi->csr0 = csr;
            break;
        case 1:
            spi->csr1 = csr;
            break;
        case 2:
            spi->csr2 = csr;
            break;
        case 3:
            spi->csr3 = csr;
            break;
        default:
            return SPI_ERROR_ARGUMENT;
    }

    return SPI_OK;
}


void spi_enable(volatile avr32_spi_t *spi)
{
    spi->cr = AVR32_SPI_CR_SPIEN_MASK;
}


void spi_disable(volatile avr32_spi_t *spi)
{
    spi->cr = AVR32_SPI_CR_SPIDIS_MASK;
}


int spi_write(volatile avr32_spi_t *spi, unsigned short data)
{
    unsigned int timeout = SPI_TIMEOUT;

    while ((spi->sr & AVR32_SPI_SR_TXEMPTY_MASK) == 0 && timeout > 0) {
        --timeout;
    }

    if (timeout == 0) {
        return SPI_ERROR_TIMEOUT;
    }

    spi->tdr = data & 0x0000FFFF;

    return SPI_OK;
}


int spi_variableSlaveWrite(volatile avr32_spi_t *spi, unsigned short data,
        unsigned char pcs, unsigned char lastxfer)
{
    unsigned int timeout = SPI_TIMEOUT;

    if (pcs > 14 || lastxfer > 1)
        return SPI_ERROR_ARGUMENT;

    while ((spi->sr & AVR32_SPI_SR_TXEMPTY_MASK) == 0 && --timeout) {
    }

    if (timeout == 0) {
        return SPI_ERROR_TIMEOUT;
    }

    spi->tdr = (data << AVR32_SPI_TDR_TD_OFFSET) |
        (pcs << AVR32_SPI_TDR_PCS_OFFSET) |
        (lastxfer << AVR32_SPI_TDR_LASTXFER_OFFSET);

    return SPI_OK;
}

unsigned char spi_readRegisterFullCheck(volatile avr32_spi_t * spi)
{
    if ((spi->sr & AVR32_SPI_SR_RDRF_MASK) != 0) {
        return 1;
    } else {
        return 0;
    }
}


int spi_read(volatile avr32_spi_t *spi, unsigned short *data)
{
    unsigned int timeout = SPI_TIMEOUT;

    do {
        --timeout;
    } while ((spi->sr & AVR32_SPI_SR_RDRF_MASK) == 0 && timeout > 0);

    if (timeout == 0) {
        return SPI_ERROR_TIMEOUT;
    }

    *data = spi->rdr & 0x0000FFFF;

    return SPI_OK;
}


#ifdef SPI_ENABLE_PDC

void spi_disablePDC(volatile avr32_spi_t * spi)
{
    volatile spi_pdc_t *pdc = (volatile spi_pdc_t *)spi;
    pdc->ptcr |= (1<<1); /* Disable RXT */
    pdc->ptcr |= (1<<9); /* Disable TXT */
}


void spi_enablePDC(volatile avr32_spi_t * spi)
{
    volatile spi_pdc_t *pdc = (volatile spi_pdc_t *)spi;
    pdc->ptcr |= (1<<0); /* Enable RXT */
    pdc->ptcr |= (1<<8); /* Enable TXT */
}


int spi_setRxBuf(volatile avr32_spi_t * spi,
        void * rp,
        unsigned short rc,
        void * rnp,
        unsigned short rnc)
{
    volatile spi_pdc_t *pdc = (volatile spi_pdc_t *)spi;

    /* Disable RX Transfer */
    pdc->ptcr |= (1<<1);

    if (rnp != 0) {
        pdc->rnpr = (long) rnp;
        pdc->rncr = rnc;
    } else {
        return SPI_ERROR_ARGUMENT;
    }

    if (rp != 0) {
        pdc->rpr = (long) rp;
        pdc->rcr = rc;
    } else {
        return SPI_ERROR_ARGUMENT;
    }

    /* Enable RX Transfer */
    pdc->ptcr |= (1<<0);

    return SPI_OK;
}


int spi_setTxBuf(volatile avr32_spi_t * spi,
        void * tp,
        unsigned short tc,
        void * tnp,
        unsigned short tnc)
{
    volatile spi_pdc_t *pdc = (volatile spi_pdc_t *)spi;

    /* Disable TX Transfer */
    pdc->ptcr |= (1<<9);

    if (tnp != 0) {
        pdc->tnpr = (long) tnp;
        pdc->tncr = tnc;
    } else {
        return SPI_ERROR_ARGUMENT;
    }

    if (tp != 0) {
        pdc->tpr = (long) tp;
        pdc->tcr = tc;
    } else {
        return SPI_ERROR_ARGUMENT;
    }

    /* Enable TX Transfer */
    pdc->ptcr |= (1<<8);

    return SPI_OK;
}


unsigned short spi_getRcr(volatile avr32_spi_t * spi)
{
    volatile spi_pdc_t *pdc = (volatile spi_pdc_t *)spi;
    return pdc->rcr;
}


unsigned short spi_getTcr(volatile avr32_spi_t * spi)
{
    volatile spi_pdc_t *pdc = (volatile spi_pdc_t *)spi;
    return pdc->tcr;
}
#endif /* SPI_ENABLE_PDC */


unsigned char spi_getStatus(volatile avr32_spi_t *spi)
{
    unsigned char ret = 0;

    if ((spi->sr & AVR32_SPI_SR_OVRES_MASK) != 0) {
        ret = SPI_ERROR_OVERRUN;
    }

    if ((spi->sr & AVR32_SPI_SR_MODF_MASK) != 0) {
        ret += SPI_ERROR_MODE_FAULT;
    }

    if (ret == (SPI_ERROR_OVERRUN + SPI_ERROR_MODE_FAULT)) {
        return SPI_ERROR_OVERRUN_AND_MODE_FAULT;
    }
    else if (ret > 0) {
        return ret;
    } else {
        return SPI_OK;
    }
}


int getBaudDiv(struct spi_options_t * options, int cpuHz) {
    int baudDiv = 0;

    if (options->fdiv == 0) {
        baudDiv = cpuHz / (options->baudrate);
    } else {
        baudDiv = cpuHz / (32 * options->baudrate);
    }

    if (baudDiv > (AVR32_SPI_CSR0_SCBR_MASK<<AVR32_SPI_CSR0_SCBR_OFFSET)
            || baudDiv <= 0) {
        return -SPI_ERROR_ARGUMENT;
    }

    return baudDiv;
}

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