Contains definitions to control PWM behaviour. More...
Go to the source code of this file.
Defines | |
| #define | PWM_OFFSET 12 |
| Needed for JumperCheck() to succeed. ADC is saturated otherwise! | |
| #define | PWM_MAX 255 |
| PWM duty cycle limit (must be less than 256). | |
Functions | |
| void | PWM_Start (void) |
| Initializes and starts PWM output. | |
| void | PWM_Stop (void) |
| Stops PWM output. | |
| unsigned char | PWM_IncrementDutyCycle (void) |
| Increments the PWM duty cycle, if not already at max. | |
| unsigned char | PWM_DecrementDutyCycle (void) |
| Decrements the PWM duty cycle, if not already at zero. | |
Contains definitions to control PWM behaviour.
Definition in file pwm.h.
| #define PWM_OFFSET 12 |
Needed for JumperCheck() to succeed. ADC is saturated otherwise!
Definition at line 49 of file pwm.h.
Referenced by PWM_Start().
| #define PWM_MAX 255 |
PWM duty cycle limit (must be less than 256).
Definition at line 52 of file pwm.h.
Referenced by PWM_IncrementDutyCycle().
| void PWM_Start | ( | void | ) |
Initializes and starts PWM output.
Initializes timer4 for use as a PWM with a clock rate of 64 MHz.
Its comparator is connected to PB3 and will output high until timer4 reaches the value of OCR4B. It is then dropped to 0.
The comparator outputs high again when the counter overflows, which will happen at a rate of 250 kHz.
Definition at line 89 of file pwm.c.
References Pll_set_hs_tmr_pscal_1dot5, PWM_OFFSET, Time_Left(), Time_Set(), and Time_Start().
{
// Clear OC4A on compare match, enable PWM on comparator OCR4A.
TCCR4A = (1<<COM4A1)|(1<<PWM4A);
// Non-inverted PWM, T/C stopped.
TCCR4B = 0;
// Copy shadow bits, disconnect OC4D.
TCCR4C = (TCCR4A & 0xF0);
// No fault protection, use phase & frequency correct PWM.
TCCR4D = (0<<WGM41)|(1<WGM40);
// Does not matter -- PWM6 mode not used.
TCCR4E = 0;
// Set reset compare level. (Offset is used, or JumperCheck() will fail.)
OCR4A = PWM_OFFSET;
// Does not matter -- OC4B is disabled.
OCR4B = 0;
// TOP value for PWM, f(PWM) = 64MHz / 255 = 251kHz.
OCR4C = 0xFF;
// Does not matter -- OC4D is disabled.
OCR4D = 0;
// No dead time values.
DT4 = 0;
// Set PWM port pin to output (PC7).
DDRC |= (1<<PORTC7);
// Enable PLL, use full speed mode.
// PLLCSR = (1<<PLLE);
//cgs update
#ifdef __GNUC__
Enable_interrupt();
#else
__enable_interrupt();
#endif
// Use general timer and wait 1 ms for PLL lock to settle.
Time_Set(TIMER_GEN,0,0,1);
//cgs update
Time_Start();
do{
}while(Time_Left(TIMER_GEN));
// Now wait for PLL to lock.
do{
}while((PLLCSR & (1<<PLOCK)) == 0);
//SELECT 64MHz for PWM
Pll_set_hs_tmr_pscal_1dot5();
// CLK PCK = 64MHz / 1 = 64MHz.
TCCR4B |= (0<<CS43)|(0<<CS42)|(0<<CS41)|(1<<CS40);
}

| void PWM_Stop | ( | void | ) |
Stops PWM output.
Definition at line 68 of file pwm.c.
{
OCR4B = 0; // Reset compare level.
TCCR4A = 0; // Set normal port operation, disable PWM modes.
TCCR4B = 0; // Stop timer/counter4.
TCCR4C = 0; // Set normal port operation.
TCCR4D = 0; // No fault protection, normal waveform.
OCR4C = 0; // Reset compare.
OCR4D = 0; // Reset compare.
DT4 = 0; // No dead time values.
}
| unsigned char PWM_IncrementDutyCycle | ( | void | ) |
| unsigned char PWM_DecrementDutyCycle | ( | void | ) |
1.7.2