ATMEL: mcu.h Source File

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00001 /****** THIS IS A MACHINE GENERATED FILE - DO NOT EDIT ******************** */
00002 /****** Created: 2008-01-29 19:00 ******* Source: ATmega32U4.XML ********** */
00003 /**************************************************************************
00004  *
00005  * - File Name          : "iom32U4.h"
00006  * - Title              : Register/Bit Definitions for the ATmega32U4
00007  * - Date               : 2008-01-29
00008  * - Version            : 2.21
00009  * - Support E-Mail     : avr@atmel.com
00010  * - Target MCU         : ATmega32U4
00011  *
00012  * - Compiler           : IAR Embedded Workbench - iccAVR and aAVR.
00013  *
00014  **************************************************************************
00015  */
00016 
00017 
00018 #include "iomacro.h"
00019 
00020 #if TID_GUARD(3)
00021 #error This file should only be compiled with iccavr or aavr whith processor option -v3
00022 #endif /* TID_GUARD(3) */
00023 
00024 /* Include the SFR part if this file has not been included before,
00025 * OR this file is included by the assembler (SFRs must be defined in
00026 * each assembler module). */
00027 #if !defined(__IOM32U4_H) || defined(__IAR_SYSTEMS_ASM__)
00028 
00029 #pragma language=extended
00030 
00031 /*==========================*/
00032 /* Predefined SFR Addresses */
00033 /*==========================*/
00034 
00035 
00036 /* ***** SPECIFY DEVICE *************************************************** */
00037 //#define  PART_NAME       ATmega32U4
00038 #define    SIGNATURE_000   0x1e
00039 #define    SIGNATURE_001   0x95
00040 #define    SIGNATURE_002   0x87
00041 
00042 
00043 
00044 /* ***** I/O REGISTER DEFINITIONS ***************************************** */
00045 /* NOTE:
00046  * Definitions marked "MEMORY MAPPED"are extended I/O ports
00047  * and cannot be used with IN/OUT instructions
00048  */
00049 SFR_B(PLLCSR,   0x29)
00050 SFR_B(PLLFRQ,   0x32)
00051 SFR_B(TESTPADSTATUS,   0xfd)
00052 SFR_B(TESTPADPULL,   0xfe)
00053 SFR_B(TESTPADCTRL,   0xff)
00054 SFR_B(UPERRX,   0xf5)
00055 SFR_B(UEINT,   0xf4)
00056 SFR_B(UPINT,   0xf8)
00057 SFR_B(UEBCHX,   0xf3)
00058 SFR_B(UPBCHX,   0xf7)
00059 SFR_B(UEBCLX,   0xf2)
00060 SFR_B(UPBCLX,   0xf6)
00061 SFR_B(UEDATX,   0xf1)
00062 SFR_B(UPDATX,   0xaf)
00063 SFR_B(UEIENX,   0xf0)
00064 SFR_B(UPIENX,   0xae)
00065 SFR_B(UESTA1X,   0xef)
00066 SFR_B(UPCFG2X,   0xad)
00067 SFR_B(UESTA0X,   0xee)
00068 SFR_B(UPSTAX,   0xac)
00069 SFR_B(UECFG1X,   0xed)
00070 SFR_B(UPCFG1X,   0xab)
00071 SFR_B(UECFG0X,   0xec)
00072 SFR_B(UPCFG0X,   0xaa)
00073 SFR_B(UECONX,   0xeb)
00074 SFR_B(UPCONX,   0xa9)
00075 SFR_B(UERST,   0xea)
00076 SFR_B(UPRST,   0xa8)
00077 SFR_B(UENUM,   0xe9)
00078 SFR_B(UPNUM,   0xa7)
00079 SFR_B(UEINTX,   0xe8)
00080 SFR_B(UPINTX,   0xa6)
00081 SFR_B(UDTST,   0xe7)
00082 SFR_B(UPINRQX,   0xa5)
00083 SFR_B(UDMFN,   0xe6)
00084 SFR_B(UHFLEN,   0xa4)
00085 SFR_B(UDFNUMH,   0xe5)
00086 SFR_B(UHFNUMH,   0xa3)
00087 SFR_B(UDFNUML,   0xe4)
00088 SFR_B(UHFNUML,   0xa2)
00089 SFR_B(UDADDR,   0xe3)
00090 SFR_B(UHADDR,   0xa1)
00091 SFR_B(UDIEN,   0xe2)
00092 SFR_B(UHIEN,   0xa0)
00093 SFR_B(UDINT,   0xe1)
00094 SFR_B(UHINT,   0x9f)
00095 SFR_B(UDCON,   0xe0)
00096 SFR_B(UHCON,   0x9e)
00097 SFR_B(OTGINT,   0xdf)
00098 SFR_B(OTGIEN,   0xde)
00099 SFR_B(OTGCON,   0xdd)
00100 SFR_B(OTGTCON,   0xf9)
00101 SFR_B(USBINT,   0xda)
00102 SFR_B(USBSTA,   0xd9)
00103 SFR_B(USBCON,   0xd8)
00104 SFR_B(UHWCON,   0xd7)
00105 SFR_B(UDR1,   0xce)
00106 SFR_W(UBRR1,   0xcc)
00107 SFR_B(UCSR1C,   0xca)
00108 SFR_B(UCSR1B,   0xc9)
00109 SFR_B(UCSR1A,   0xc8)
00110 SFR_B(TWAMR,   0xbd)
00111 SFR_B(TWCR,   0xbc)
00112 SFR_B(TWDR,   0xbb)
00113 SFR_B(TWAR,   0xba)
00114 SFR_B(TWSR,   0xb9)
00115 SFR_B(TWBR,   0xb8)
00116 SFR_B(OCR2B,   0xb4)
00117 SFR_B(OCR2A,   0xb3)
00118 SFR_B(TCNT2,   0xb2)
00119 SFR_B(TCCR2B,   0xb1)
00120 SFR_B(TCCR2A,   0xb0)
00121 SFR_W(OCR3C,   0x9c)
00122 SFR_W(OCR3B,   0x9a)
00123 SFR_W(OCR3A,   0x98)
00124 SFR_W(ICR3,   0x96)
00125 SFR_W(TCNT3,   0x94)
00126 SFR_B(TCCR3C,   0x92)
00127 SFR_B(TCCR3B,   0x91)
00128 SFR_B(TCCR3A,   0x90)
00129 SFR_W(OCR1C,   0x8c)
00130 SFR_W(OCR1B,   0x8a)
00131 SFR_W(OCR1A,   0x88)
00132 SFR_W(ICR1,   0x86)
00133 SFR_W(TCNT1,   0x84)
00134 SFR_B(TCCR1C,   0x82)
00135 SFR_B(TCCR1B,   0x81)
00136 SFR_B(TCCR1A,   0x80)
00137 SFR_B(DIDR1,   0x7f)
00138 SFR_B(DIDR0,   0x7e)
00139 SFR_B(DIDR2,   0x7d)
00140 SFR_B(ADMUX,   0x7c)
00141 SFR_B(ADCSRB,   0x7b)
00142 SFR_B(ADCSRA,   0x7a)
00143 SFR_B(ADCH,   0x79)
00144 SFR_B(ADCL,   0x78)
00145 SFR_B(TIMSK5,   0x73)
00146 SFR_B(TIMSK4,   0x72)
00147 SFR_B(TIMSK3,   0x71)
00148 SFR_B(TIMSK2,   0x70)
00149 SFR_B(TIMSK1,   0x6f)
00150 SFR_B(TIMSK0,   0x6e)
00151 SFR_B(PCMSK2,   0x6d)
00152 SFR_B(PCMSK1,   0x6c)
00153 SFR_B(PCMSK0,   0x6b)
00154 SFR_B(EICRB,   0x6a)
00155 SFR_B(EICRA,   0x69)
00156 SFR_B(PCICR,   0x68)
00157 SFR_B(OSCCAL,   0x66)
00158 SFR_B(RCCTRL,   0x67)
00159 SFR_B(PRR1,   0x65)
00160 SFR_B(PRR0,   0x64)
00161 SFR_B(CLKPR,   0x61)
00162 SFR_B(WDTCSR,   0x60)
00163 SFR_B(SREG,   0x3f)
00164 SFR_W(SP,   0x3d)
00165 SFR_B(EIND,   0x3c)
00166 SFR_B(RAMPZ,   0x3b)
00167 SFR_B(SPMCSR,   0x37)
00168 SFR_B(MCUCR,   0x35)
00169 SFR_B(MCUSR,   0x34)
00170 SFR_B(SMCR,   0x33)
00171 SFR_B(OCDR,   0x31)
00172 SFR_B(ACSR,   0x30)
00173 SFR_B(SPDR,   0x2e)
00174 SFR_B(SPSR,   0x2d)
00175 SFR_B(SPCR,   0x2c)
00176 SFR_B(GPIOR2,   0x2b)
00177 SFR_B(GPIOR1,   0x2a)
00178 SFR_B(OCR0B,   0x28)
00179 SFR_B(OCR0A,   0x27)
00180 SFR_B(TCNT0,   0x26)
00181 SFR_B(TCCR0B,   0x25)
00182 SFR_B(TCCR0A,   0x24)
00183 SFR_B(GTCCR,   0x23)
00184 //SFR_B(EEARH,   0x22)
00185 //SFR_B(EEARL,   0x21)
00186 SFR_W(EEAR,   0x21)     /* EEPROM Address Register */
00187 SFR_B(EEDR,   0x20)
00188 SFR_B(EECR,   0x1f)
00189 SFR_B(GPIOR0,   0x1e)
00190 SFR_B(EIMSK,   0x1d)
00191 SFR_B(EIFR,   0x1c)
00192 SFR_B(PCIFR,   0x1b)
00193 SFR_B(TIFR5,   0x1a)
00194 SFR_B(TIFR4,   0x19)
00195 SFR_B(TIFR3,   0x18)
00196 SFR_B(TIFR2,   0x17)
00197 SFR_B(TIFR1,   0x16)
00198 SFR_B(TIFR0,   0x15)
00199 SFR_B(PORTF,   0x11)
00200 SFR_B(DDRF,   0x10)
00201 SFR_B(PINF,   0x0f)
00202 SFR_B(PORTE,   0x0e)
00203 SFR_B(DDRE,   0x0d)
00204 SFR_B(PINE,   0x0c)
00205 SFR_B(PORTD,   0x0b)
00206 SFR_B(DDRD,   0x0a)
00207 SFR_B(PIND,   0x09)
00208 SFR_B(PORTC,   0x08)
00209 SFR_B(DDRC,   0x07)
00210 SFR_B(PINC,   0x06)
00211 SFR_B(PORTB,   0x05)
00212 SFR_B(DDRB,   0x04)
00213 SFR_B(PINB,   0x03)
00214 SFR_B(DT4,   0xd4)
00215 SFR_B(OCR4D,   0xd2)
00216 SFR_B(OCR4C,   0xd1)
00217 SFR_B(OCR4B,   0xd0)
00218 SFR_B(OCR4A,   0xcf)
00219 SFR_B(TCCR4E,   0xc4)
00220 SFR_B(TCCR4D,   0xc3)
00221 SFR_B(TCCR4C,   0xc2)
00222 SFR_B(TCCR4B,   0xc1)
00223 SFR_B(TCCR4A,   0xc0)
00224 SFR_B(TC4H,   0xbf)
00225 SFR_B(TCNT4,   0xbe)
00226 SFR_B(DIDR2,   0x7d)
00227 SFR_B(CLKSEL1,   0xc6)
00228 SFR_B(CLKSEL0,   0xc5)
00229 SFR_B(CLKSTA,   0xc7)
00230 
00231 
00232 
00233 #ifndef __IOM32U4_H
00234 #define __IOM32U4_H
00235 
00236 #ifdef __IAR_SYSTEMS_ASM__ 
00237 #ifndef ENABLE_BIT_DEFINITIONS
00238 #define  ENABLE_BIT_DEFINITIONS
00239 #endif /* ENABLE_BIT_DEFINITIONS */
00240 #endif /* __IAR_SYSTEMS_ASM__ */
00241 
00242 #ifdef ENABLE_BIT_DEFINITIONS
00243 /* ***** BIT DEFINITIONS ************************************************** */
00244 
00245 /* ***** WATCHDOG ********************* */
00246 /* WDTCSR - Watchdog Timer Control Register */
00247 #define    WDP0            0       // Watch Dog Timer Prescaler bit 0
00248 #define    WDP1            1       // Watch Dog Timer Prescaler bit 1
00249 #define    WDP2            2       // Watch Dog Timer Prescaler bit 2
00250 #define    WDE             3       // Watch Dog Enable
00251 #define    WDCE            4       // Watchdog Change Enable
00252 #define    WDP3            5       // Watchdog Timer Prescaler Bit 3
00253 #define    WDIE            6       // Watchdog Timeout Interrupt Enable
00254 #define    WDIF            7       // Watchdog Timeout Interrupt Flag
00255 
00256 
00257 /* ***** PORTD ************************ */
00258 /* PORTD - Port D Data Register */
00259 #define    PORTD0          0       // Port D Data Register bit 0
00260 #define    PORTD1          1       // Port D Data Register bit 1
00261 #define    PORTD2          2       // Port D Data Register bit 2
00262 #define    PORTD3          3       // Port D Data Register bit 3
00263 #define    PORTD4          4       // Port D Data Register bit 4
00264 #define    PORTD5          5       // Port D Data Register bit 5
00265 #define    PORTD6          6       // Port D Data Register bit 6
00266 #define    PORTD7          7       // Port D Data Register bit 7
00267 
00268 /* DDRD - Port D Data Direction Register */
00269 #define    DDD0            0       // Port D Data Direction Register bit 0
00270 #define    DDD1            1       // Port D Data Direction Register bit 1
00271 #define    DDD2            2       // Port D Data Direction Register bit 2
00272 #define    DDD3            3       // Port D Data Direction Register bit 3
00273 #define    DDD4            4       // Port D Data Direction Register bit 4
00274 #define    DDD5            5       // Port D Data Direction Register bit 5
00275 #define    DDD6            6       // Port D Data Direction Register bit 6
00276 #define    DDD7            7       // Port D Data Direction Register bit 7
00277 
00278 /* PIND - Port D Input Pins */
00279 #define    PIND0           0       // Port D Input Pins bit 0
00280 #define    PIND1           1       // Port D Input Pins bit 1
00281 #define    PIND2           2       // Port D Input Pins bit 2
00282 #define    PIND3           3       // Port D Input Pins bit 3
00283 #define    PIND4           4       // Port D Input Pins bit 4
00284 #define    PIND5           5       // Port D Input Pins bit 5
00285 #define    PIND6           6       // Port D Input Pins bit 6
00286 #define    PIND7           7       // Port D Input Pins bit 7
00287 
00288 
00289 /* ***** TWI ************************** */
00290 /* TWAMR - TWI (Slave) Address Mask Register */
00291 #define    TWAM0           1       // 
00292 #define    TWAMR0          TWAM0   // For compatibility
00293 #define    TWAM1           2       // 
00294 #define    TWAMR1          TWAM1   // For compatibility
00295 #define    TWAM2           3       // 
00296 #define    TWAMR2          TWAM2   // For compatibility
00297 #define    TWAM3           4       // 
00298 #define    TWAMR3          TWAM3   // For compatibility
00299 #define    TWAM4           5       // 
00300 #define    TWAMR4          TWAM4   // For compatibility
00301 #define    TWAM5           6       // 
00302 #define    TWAMR5          TWAM5   // For compatibility
00303 #define    TWAM6           7       // 
00304 #define    TWAMR6          TWAM6   // For compatibility
00305 
00306 /* TWBR - TWI Bit Rate register */
00307 #define    TWBR0           0       // 
00308 #define    TWBR1           1       // 
00309 #define    TWBR2           2       // 
00310 #define    TWBR3           3       // 
00311 #define    TWBR4           4       // 
00312 #define    TWBR5           5       // 
00313 #define    TWBR6           6       // 
00314 #define    TWBR7           7       // 
00315 
00316 /* TWCR - TWI Control Register */
00317 #define    TWIE            0       // TWI Interrupt Enable
00318 #define    TWEN            2       // TWI Enable Bit
00319 #define    TWWC            3       // TWI Write Collition Flag
00320 #define    TWSTO           4       // TWI Stop Condition Bit
00321 #define    TWSTA           5       // TWI Start Condition Bit
00322 #define    TWEA            6       // TWI Enable Acknowledge Bit
00323 #define    TWINT           7       // TWI Interrupt Flag
00324 
00325 /* TWSR - TWI Status Register */
00326 #define    TWPS0           0       // TWI Prescaler
00327 #define    TWPS1           1       // TWI Prescaler
00328 #define    TWS3            3       // TWI Status
00329 #define    TWS4            4       // TWI Status
00330 #define    TWS5            5       // TWI Status
00331 #define    TWS6            6       // TWI Status
00332 #define    TWS7            7       // TWI Status
00333 
00334 /* TWDR - TWI Data register */
00335 #define    TWD0            0       // TWI Data Register Bit 0
00336 #define    TWD1            1       // TWI Data Register Bit 1
00337 #define    TWD2            2       // TWI Data Register Bit 2
00338 #define    TWD3            3       // TWI Data Register Bit 3
00339 #define    TWD4            4       // TWI Data Register Bit 4
00340 #define    TWD5            5       // TWI Data Register Bit 5
00341 #define    TWD6            6       // TWI Data Register Bit 6
00342 #define    TWD7            7       // TWI Data Register Bit 7
00343 
00344 /* TWAR - TWI (Slave) Address register */
00345 #define    TWGCE           0       // TWI General Call Recognition Enable Bit
00346 #define    TWA0            1       // TWI (Slave) Address register Bit 0
00347 #define    TWA1            2       // TWI (Slave) Address register Bit 1
00348 #define    TWA2            3       // TWI (Slave) Address register Bit 2
00349 #define    TWA3            4       // TWI (Slave) Address register Bit 3
00350 #define    TWA4            5       // TWI (Slave) Address register Bit 4
00351 #define    TWA5            6       // TWI (Slave) Address register Bit 5
00352 #define    TWA6            7       // TWI (Slave) Address register Bit 6
00353 
00354 
00355 /* ***** SPI ************************** */
00356 /* SPDR - SPI Data Register */
00357 #define    SPDR0           0       // SPI Data Register bit 0
00358 #define    SPDR1           1       // SPI Data Register bit 1
00359 #define    SPDR2           2       // SPI Data Register bit 2
00360 #define    SPDR3           3       // SPI Data Register bit 3
00361 #define    SPDR4           4       // SPI Data Register bit 4
00362 #define    SPDR5           5       // SPI Data Register bit 5
00363 #define    SPDR6           6       // SPI Data Register bit 6
00364 #define    SPDR7           7       // SPI Data Register bit 7
00365 
00366 /* SPSR - SPI Status Register */
00367 #define    SPI2X           0       // Double SPI Speed Bit
00368 #define    WCOL            6       // Write Collision Flag
00369 #define    SPIF            7       // SPI Interrupt Flag
00370 
00371 /* SPCR - SPI Control Register */
00372 #define    SPR0            0       // SPI Clock Rate Select 0
00373 #define    SPR1            1       // SPI Clock Rate Select 1
00374 #define    CPHA            2       // Clock Phase
00375 #define    CPOL            3       // Clock polarity
00376 #define    MSTR            4       // Master/Slave Select
00377 #define    DORD            5       // Data Order
00378 #define    SPE             6       // SPI Enable
00379 #define    SPIE            7       // SPI Interrupt Enable
00380 
00381 
00382 /* ***** USART1 *********************** */
00383 /* UDR1 - USART I/O Data Register */
00384 #define    UDR1_0          0       // USART I/O Data Register bit 0
00385 #define    UDR1_1          1       // USART I/O Data Register bit 1
00386 #define    UDR1_2          2       // USART I/O Data Register bit 2
00387 #define    UDR1_3          3       // USART I/O Data Register bit 3
00388 #define    UDR1_4          4       // USART I/O Data Register bit 4
00389 #define    UDR1_5          5       // USART I/O Data Register bit 5
00390 #define    UDR1_6          6       // USART I/O Data Register bit 6
00391 #define    UDR1_7          7       // USART I/O Data Register bit 7
00392 
00393 /* UCSR1A - USART Control and Status Register A */
00394 #define    MPCM1           0       // Multi-processor Communication Mode
00395 #define    U2X1            1       // Double the USART transmission speed
00396 #define    UPE1            2       // Parity Error
00397 #define    DOR1            3       // Data overRun
00398 #define    FE1             4       // Framing Error
00399 #define    UDRE1           5       // USART Data Register Empty
00400 #define    TXC1            6       // USART Transmitt Complete
00401 #define    RXC1            7       // USART Receive Complete
00402 
00403 /* UCSR1B - USART Control and Status Register B */
00404 #define    TXB81           0       // Transmit Data Bit 8
00405 #define    RXB81           1       // Receive Data Bit 8
00406 #define    UCSZ12          2       // Character Size
00407 #define    TXEN1           3       // Transmitter Enable
00408 #define    RXEN1           4       // Receiver Enable
00409 #define    UDRIE1          5       // USART Data register Empty Interrupt Enable
00410 #define    TXCIE1          6       // TX Complete Interrupt Enable
00411 #define    RXCIE1          7       // RX Complete Interrupt Enable
00412 
00413 /* UCSR1C - USART Control and Status Register C */
00414 #define    UCPOL1          0       // Clock Polarity
00415 #define    UCSZ10          1       // Character Size
00416 #define    UCPHA1          UCSZ10  // For compatibility
00417 #define    UCSZ11          2       // Character Size
00418 #define    UDORD1          UCSZ11  // For compatibility
00419 #define    USBS1           3       // Stop Bit Select
00420 #define    UPM10           4       // Parity Mode Bit 0
00421 #define    UPM11           5       // Parity Mode Bit 1
00422 #define    UMSEL10         6       // USART Mode Select
00423 #define    UMSEL11         7       // USART Mode Select
00424 
00425 
00426 /* ***** BOOT_LOAD ******************** */
00427 /* SPMCSR - Store Program Memory Control Register */
00428 #define    SPMEN           0       // Store Program Memory Enable
00429 #define    PGERS           1       // Page Erase
00430 #define    PGWRT           2       // Page Write
00431 #define    BLBSET          3       // Boot Lock Bit Set
00432 #define    RWWSRE          4       // Read While Write section read enable
00433 #define    SIGRD           5       // Signature Row Read
00434 #define    RWWSB           6       // Read While Write Section Busy
00435 #define    SPMIE           7       // SPM Interrupt Enable
00436 
00437 
00438 /* ***** EEPROM *********************** */
00439 /* EEARH - EEPROM Address Register Low Byte */
00440 #define    EEAR8           0       // EEPROM Read/Write Access Bit 8
00441 #define    EEAR9           1       // EEPROM Read/Write Access Bit 9
00442 #define    EEAR10          2       // EEPROM Read/Write Access Bit 10
00443 #define    EEAR11          3       // EEPROM Read/Write Access Bit 11
00444 
00445 /* EEARL - EEPROM Address Register Low Byte */
00446 #define    EEAR0           0       // EEPROM Read/Write Access Bit 0
00447 #define    EEAR1           1       // EEPROM Read/Write Access Bit 1
00448 #define    EEAR2           2       // EEPROM Read/Write Access Bit 2
00449 #define    EEAR3           3       // EEPROM Read/Write Access Bit 3
00450 #define    EEAR4           4       // EEPROM Read/Write Access Bit 4
00451 #define    EEAR5           5       // EEPROM Read/Write Access Bit 5
00452 #define    EEAR6           6       // EEPROM Read/Write Access Bit 6
00453 #define    EEAR7           7       // EEPROM Read/Write Access Bit 7
00454 
00455 /* EEDR - EEPROM Data Register */
00456 #define    EEDR0           0       // EEPROM Data Register bit 0
00457 #define    EEDR1           1       // EEPROM Data Register bit 1
00458 #define    EEDR2           2       // EEPROM Data Register bit 2
00459 #define    EEDR3           3       // EEPROM Data Register bit 3
00460 #define    EEDR4           4       // EEPROM Data Register bit 4
00461 #define    EEDR5           5       // EEPROM Data Register bit 5
00462 #define    EEDR6           6       // EEPROM Data Register bit 6
00463 #define    EEDR7           7       // EEPROM Data Register bit 7
00464 
00465 /* EECR - EEPROM Control Register */
00466 #define    EERE            0       // EEPROM Read Enable
00467 #define    EEPE            1       // EEPROM Write Enable
00468 #define    EEMPE           2       // EEPROM Master Write Enable
00469 #define    EERIE           3       // EEPROM Ready Interrupt Enable
00470 #define    EEPM0           4       // EEPROM Programming Mode Bit 0
00471 #define    EEPM1           5       // EEPROM Programming Mode Bit 1
00472 
00473 
00474 /* ***** TIMER_COUNTER_0 ************** */
00475 /* TIMSK0 - Timer/Counter0 Interrupt Mask Register */
00476 #define    TOIE0           0       // Timer/Counter0 Overflow Interrupt Enable
00477 #define    OCIE0A          1       // Timer/Counter0 Output Compare Match A Interrupt Enable
00478 #define    OCIE0B          2       // Timer/Counter0 Output Compare Match B Interrupt Enable
00479 
00480 /* TIFR0 - Timer/Counter0 Interrupt Flag register */
00481 #define    TOV0            0       // Timer/Counter0 Overflow Flag
00482 #define    OCF0A           1       // Timer/Counter0 Output Compare Flag 0A
00483 #define    OCF0B           2       // Timer/Counter0 Output Compare Flag 0B
00484 
00485 /* TCCR0A - Timer/Counter  Control Register A */
00486 #define    WGM00           0       // Waveform Generation Mode
00487 #define    WGM01           1       // Waveform Generation Mode
00488 #define    COM0B0          4       // Compare Output Mode, Fast PWm
00489 #define    COM0B1          5       // Compare Output Mode, Fast PWm
00490 #define    COM0A0          6       // Compare Output Mode, Phase Correct PWM Mode
00491 #define    COM0A1          7       // Compare Output Mode, Phase Correct PWM Mode
00492 
00493 /* TCCR0B - Timer/Counter Control Register B */
00494 #define    CS00            0       // Clock Select
00495 #define    CS01            1       // Clock Select
00496 #define    CS02            2       // Clock Select
00497 #define    WGM02           3       // 
00498 #define    FOC0B           6       // Force Output Compare B
00499 #define    FOC0A           7       // Force Output Compare A
00500 
00501 /* TCNT0 - Timer/Counter0 */
00502 #define    TCNT0_0         0       // 
00503 #define    TCNT0_1         1       // 
00504 #define    TCNT0_2         2       // 
00505 #define    TCNT0_3         3       // 
00506 #define    TCNT0_4         4       // 
00507 #define    TCNT0_5         5       // 
00508 #define    TCNT0_6         6       // 
00509 #define    TCNT0_7         7       // 
00510 
00511 /* OCR0A - Timer/Counter0 Output Compare Register */
00512 #define    OCROA_0         0       // 
00513 #define    OCROA_1         1       // 
00514 #define    OCROA_2         2       // 
00515 #define    OCROA_3         3       // 
00516 #define    OCROA_4         4       // 
00517 #define    OCROA_5         5       // 
00518 #define    OCROA_6         6       // 
00519 #define    OCROA_7         7       // 
00520 
00521 /* OCR0B - Timer/Counter0 Output Compare Register */
00522 #define    OCR0B_0         0       // 
00523 #define    OCR0B_1         1       // 
00524 #define    OCR0B_2         2       // 
00525 #define    OCR0B_3         3       // 
00526 #define    OCR0B_4         4       // 
00527 #define    OCR0B_5         5       // 
00528 #define    OCR0B_6         6       // 
00529 #define    OCR0B_7         7       // 
00530 
00531 /* GTCCR - General Timer/Counter Control Register */
00532 #define    PSRSYNC         0       // Prescaler Reset Timer/Counter1 and Timer/Counter0
00533 #define    PSR10           PSRSYNC // For compatibility
00534 #define    TSM             7       // Timer/Counter Synchronization Mode
00535 
00536 
00537 /* ***** TIMER_COUNTER_3 ************** */
00538 /* TIMSK3 - Timer/Counter3 Interrupt Mask Register */
00539 #define    TOIE3           0       // Timer/Counter3 Overflow Interrupt Enable
00540 #define    OCIE3A          1       // Timer/Counter3 Output Compare A Match Interrupt Enable
00541 #define    OCIE3B          2       // Timer/Counter3 Output Compare B Match Interrupt Enable
00542 #define    OCIE3C          3       // Timer/Counter3 Output Compare C Match Interrupt Enable
00543 #define    ICIE3           5       // Timer/Counter3 Input Capture Interrupt Enable
00544 
00545 /* TIFR3 - Timer/Counter3 Interrupt Flag register */
00546 #define    TOV3            0       // Timer/Counter3 Overflow Flag
00547 #define    OCF3A           1       // Output Compare Flag 3A
00548 #define    OCF3B           2       // Output Compare Flag 3B
00549 #define    OCF3C           3       // Output Compare Flag 3C
00550 #define    ICF3            5       // Input Capture Flag 3
00551 
00552 /* TCCR3A - Timer/Counter3 Control Register A */
00553 #define    WGM30           0       // Waveform Generation Mode
00554 #define    WGM31           1       // Waveform Generation Mode
00555 #define    COM3C0          2       // Compare Output Mode 3C, bit 0
00556 #define    COM3C1          3       // Compare Output Mode 3C, bit 1
00557 #define    COM3B0          4       // Compare Output Mode 3B, bit 0
00558 #define    COM3B1          5       // Compare Output Mode 3B, bit 1
00559 #define    COM3A0          6       // Compare Output Mode 3A, bit 0
00560 #define    COM3A1          7       // Compare Output Mode 1A, bit 1
00561 
00562 /* TCCR3B - Timer/Counter3 Control Register B */
00563 #define    CS30            0       // Prescaler source of Timer/Counter 3
00564 #define    CS31            1       // Prescaler source of Timer/Counter 3
00565 #define    CS32            2       // Prescaler source of Timer/Counter 3
00566 #define    WGM32           3       // Waveform Generation Mode
00567 #define    WGM33           4       // Waveform Generation Mode
00568 #define    ICES3           6       // Input Capture 3 Edge Select
00569 #define    ICNC3           7       // Input Capture 3 Noise Canceler
00570 
00571 /* TCCR3C - Timer/Counter 3 Control Register C */
00572 #define    FOC3C           5       // Force Output Compare 3C
00573 #define    FOC3B           6       // Force Output Compare 3B
00574 #define    FOC3A           7       // Force Output Compare 3A
00575 
00576 
00577 /* ***** TIMER_COUNTER_1 ************** */
00578 /* TIMSK1 - Timer/Counter1 Interrupt Mask Register */
00579 #define    TOIE1           0       // Timer/Counter1 Overflow Interrupt Enable
00580 #define    OCIE1A          1       // Timer/Counter1 Output Compare A Match Interrupt Enable
00581 #define    OCIE1B          2       // Timer/Counter1 Output Compare B Match Interrupt Enable
00582 #define    OCIE1C          3       // Timer/Counter1 Output Compare C Match Interrupt Enable
00583 #define    ICIE1           5       // Timer/Counter1 Input Capture Interrupt Enable
00584 
00585 /* TIFR1 - Timer/Counter1 Interrupt Flag register */
00586 #define    TOV1            0       // Timer/Counter1 Overflow Flag
00587 #define    OCF1A           1       // Output Compare Flag 1A
00588 #define    OCF1B           2       // Output Compare Flag 1B
00589 #define    OCF1C           3       // Output Compare Flag 1C
00590 #define    ICF1            5       // Input Capture Flag 1
00591 
00592 /* TCCR1A - Timer/Counter1 Control Register A */
00593 #define    WGM10           0       // Waveform Generation Mode
00594 #define    WGM11           1       // Waveform Generation Mode
00595 #define    COM1C0          2       // Compare Output Mode 1C, bit 0
00596 #define    COM1C1          3       // Compare Output Mode 1C, bit 1
00597 #define    COM1B0          4       // Compare Output Mode 1B, bit 0
00598 #define    COM1B1          5       // Compare Output Mode 1B, bit 1
00599 #define    COM1A0          6       // Compare Output Mode 1A, bit 0
00600 #define    COM1A1          7       // Compare Output Mode 1A, bit 1
00601 
00602 /* TCCR1B - Timer/Counter1 Control Register B */
00603 #define    CS10            0       // Prescaler source of Timer/Counter 1
00604 #define    CS11            1       // Prescaler source of Timer/Counter 1
00605 #define    CS12            2       // Prescaler source of Timer/Counter 1
00606 #define    WGM12           3       // Waveform Generation Mode
00607 #define    WGM13           4       // Waveform Generation Mode
00608 #define    ICES1           6       // Input Capture 1 Edge Select
00609 #define    ICNC1           7       // Input Capture 1 Noise Canceler
00610 
00611 /* TCCR1C - Timer/Counter 1 Control Register C */
00612 #define    FOC1C           5       // Force Output Compare 1C
00613 #define    FOC1B           6       // Force Output Compare 1B
00614 #define    FOC1A           7       // Force Output Compare 1A
00615 
00616 
00617 /* ***** JTAG ************************* */
00618 /* OCDR - On-Chip Debug Related Register in I/O Memory */
00619 #define    OCDR0           0       // On-Chip Debug Register Bit 0
00620 #define    OCDR1           1       // On-Chip Debug Register Bit 1
00621 #define    OCDR2           2       // On-Chip Debug Register Bit 2
00622 #define    OCDR3           3       // On-Chip Debug Register Bit 3
00623 #define    OCDR4           4       // On-Chip Debug Register Bit 4
00624 #define    OCDR5           5       // On-Chip Debug Register Bit 5
00625 #define    OCDR6           6       // On-Chip Debug Register Bit 6
00626 #define    OCDR7           7       // On-Chip Debug Register Bit 7
00627 #define    IDRD            OCDR7   // For compatibility
00628 
00629 /* MCUCR - MCU Control Register */
00630 #define    JTD             7       // JTAG Interface Disable
00631 
00632 /* MCUSR - MCU Status Register */
00633 #define    JTRF            4       // JTAG Reset Flag
00634 
00635 
00636 /* ***** EXTERNAL_INTERRUPT *********** */
00637 /* EICRA - External Interrupt Control Register A */
00638 #define    ISC00           0       // External Interrupt Sense Control Bit
00639 #define    ISC01           1       // External Interrupt Sense Control Bit
00640 #define    ISC10           2       // External Interrupt Sense Control Bit
00641 #define    ISC11           3       // External Interrupt Sense Control Bit
00642 #define    ISC20           4       // External Interrupt Sense Control Bit
00643 #define    ISC21           5       // External Interrupt Sense Control Bit
00644 #define    ISC30           6       // External Interrupt Sense Control Bit
00645 #define    ISC31           7       // External Interrupt Sense Control Bit
00646 
00647 /* EICRB - External Interrupt Control Register B */
00648 #define    ISC40           0       // External Interrupt 7-4 Sense Control Bit
00649 #define    ISC41           1       // External Interrupt 7-4 Sense Control Bit
00650 #define    ISC50           2       // External Interrupt 7-4 Sense Control Bit
00651 #define    ISC51           3       // External Interrupt 7-4 Sense Control Bit
00652 #define    ISC60           4       // External Interrupt 7-4 Sense Control Bit
00653 #define    ISC61           5       // External Interrupt 7-4 Sense Control Bit
00654 #define    ISC70           6       // External Interrupt 7-4 Sense Control Bit
00655 #define    ISC71           7       // External Interrupt 7-4 Sense Control Bit
00656 
00657 /* EIMSK - External Interrupt Mask Register */
00658 #define    INT0            0       // External Interrupt Request 0 Enable
00659 #define    INT1            1       // External Interrupt Request 1 Enable
00660 #define    INT2            2       // External Interrupt Request 2 Enable
00661 #define    INT3            3       // External Interrupt Request 3 Enable
00662 #define    INT4            4       // External Interrupt Request 4 Enable
00663 #define    INT5            5       // External Interrupt Request 5 Enable
00664 #define    INT6            6       // External Interrupt Request 6 Enable
00665 #define    INT7            7       // External Interrupt Request 7 Enable
00666 
00667 /* EIFR - External Interrupt Flag Register */
00668 #define    INTF0           0       // External Interrupt Flag 0
00669 #define    INTF1           1       // External Interrupt Flag 1
00670 #define    INTF2           2       // External Interrupt Flag 2
00671 #define    INTF3           3       // External Interrupt Flag 3
00672 #define    INTF4           4       // External Interrupt Flag 4
00673 #define    INTF5           5       // External Interrupt Flag 5
00674 #define    INTF6           6       // External Interrupt Flag 6
00675 #define    INTF7           7       // External Interrupt Flag 7
00676 
00677 /* PCICR - Pin Change Interrupt Control Register */
00678 #define    PCIE0           0       // Pin Change Interrupt Enable 0
00679 
00680 /* PCIFR - Pin Change Interrupt Flag Register */
00681 #define    PCIF0           0       // Pin Change Interrupt Flag 0
00682 
00683 /* PCMSK0 - Pin Change Mask Register 0 */
00684 #define    PCINT0          0       // Pin Change Enable Mask 0
00685 #define    PCINT1          1       // Pin Change Enable Mask 1
00686 #define    PCINT2          2       // Pin Change Enable Mask 2
00687 #define    PCINT3          3       // Pin Change Enable Mask 3
00688 #define    PCINT4          4       // Pin Change Enable Mask 4
00689 #define    PCINT5          5       // Pin Change Enable Mask 5
00690 #define    PCINT6          6       // Pin Change Enable Mask 6
00691 #define    PCINT7          7       // Pin Change Enable Mask 7
00692 
00693 
00694 /* ***** TIMER_COUNTER_4 ************** */
00695 /* DT4 - Timer/Counter 4 Dead Time Value */
00696 #define    DT4L0           0       // Timer/Counter 4 Dead Time Value Bit 0
00697 #define    DT4L1           1       // Timer/Counter 4 Dead Time Value Bit 1
00698 #define    DT4L2           2       // Timer/Counter 4 Dead Time Value Bit 2
00699 #define    DT4L3           3       // Timer/Counter 4 Dead Time Value Bit 3
00700 #define    DT4L4           4       // Timer/Counter 4 Dead Time Value Bit 4
00701 #define    DT4L5           5       // Timer/Counter 4 Dead Time Value Bit 5
00702 #define    DT4L6           6       // Timer/Counter 4 Dead Time Value Bit 6
00703 #define    DT4L7           7       // Timer/Counter 4 Dead Time Value Bit 7
00704 
00705 /* TIFR4 - Timer/Counter4 Interrupt Flag register */
00706 #define    TOV4            2       // Timer/Counter4 Overflow Flag
00707 #define    OCF4B           5       // Output Compare Flag 4B
00708 #define    OCF4A           6       // Output Compare Flag 4A
00709 #define    OCF4D           7       // Output Compare Flag 4D
00710 
00711 /* TIMSK4 - Timer/Counter4 Interrupt Mask Register */
00712 #define    TOIE4           2       // Timer/Counter4 Overflow Interrupt Enable
00713 #define    OCIE4B          5       // Timer/Counter4 Output Compare B Match Interrupt Enable
00714 #define    OCIE4A          6       // Timer/Counter4 Output Compare A Match Interrupt Enable
00715 #define    OCIE4D          7       // Timer/Counter4 Output Compare D Match Interrupt Enable
00716 
00717 /* OCR4D - Timer/Counter4 Output Compare Register D */
00718 #define    OCR4D0          0       // Timer/Counter4 Output Compare Register Low Byte bit 0
00719 #define    OCR4D1          1       // Timer/Counter4 Output Compare Register Low Byte bit 1
00720 #define    OCR4D2          2       // Timer/Counter4 Output Compare Register Low Byte bit 2
00721 #define    OCR4D3          3       // Timer/Counter4 Output Compare Register Low Byte bit 3
00722 #define    OCR4D4          4       // Timer/Counter4 Output Compare Register Low Byte bit 4
00723 #define    OCR4D5          5       // Timer/Counter4 Output Compare Register Low Byte bit 5
00724 #define    OCR4D6          6       // Timer/Counter4 Output Compare Register Low Byte bit 6
00725 #define    OCR4D7          7       // Timer/Counter4 Output Compare Register Low Byte bit 7
00726 
00727 /* OCR4C - Timer/Counter4 Output Compare Register C */
00728 #define    OCR4C0          0       // Timer/Counter4 Output Compare Register bit 0
00729 #define    OCR4C1          1       // Timer/Counter4 Output Compare Register bit 1
00730 #define    OCR4C2          2       // Timer/Counter4 Output Compare Register bit 2
00731 #define    OCR4C3          3       // Timer/Counter4 Output Compare Register bit 3
00732 #define    OCR4C4          4       // Timer/Counter4 Output Compare Register bit 4
00733 #define    OCR4C5          5       // Timer/Counter4 Output Compare Register bit 5
00734 #define    OCR4C6          6       // Timer/Counter4 Output Compare Register 6
00735 #define    OCR4C7          7       // Timer/Counter4 Output Compare Register bit 7
00736 
00737 /* OCR4B - Timer/Counter4 Output Compare Register B */
00738 #define    OCR4B0          0       // Timer/Counter4 Output Compare Register bit 0
00739 #define    OCR4B1          1       // Timer/Counter4 Output Compare Register bit 1
00740 #define    OCR4B2          2       // Timer/Counter4 Output Compare Register bit 2
00741 #define    OCR4B3          3       // Timer/Counter4 Output Compare Register bit 3
00742 #define    OCR4B4          4       // Timer/Counter4 Output Compare Register bit 4
00743 #define    OCR4B5          5       // Timer/Counter4 Output Compare Register bit 5
00744 #define    OCR4B6          6       // Timer/Counter4 Output Compare Register bit 6
00745 #define    OCR4B7          7       // Timer/Counter4 Output Compare Register bit 7
00746 
00747 /* OCR4A - Timer/Counter4 Outbut Compare Register A */
00748 #define    OCR4A0          0       // Timer/Counter4 Outbut Compare Register Bit 0
00749 #define    OCR4A1          1       // Timer/Counter4 Outbut Compare Register Bit 1
00750 #define    OCR4A2          2       // Timer/Counter4 Outbut Compare Register Low Byte Bit 2
00751 #define    OCR4A3          3       // Timer/Counter4 Outbut Compare Register Low Byte Bit 3
00752 #define    OCR4A4          4       // Timer/Counter4 Outbut Compare Register Bit 4
00753 #define    OCR4A5          5       // Timer/Counter4 Outbut Compare Register Bit 5
00754 #define    OCR4A6          6       // Timer/Counter4 Outbut Compare Register Bit 6
00755 #define    OCR4A7          7       // Timer/Counter4 Outbut Compare Register Bit 7
00756 
00757 /* TC4H - Timer/Counter4 */
00758 #define    TC48            0       // Timer/Counter4 bit 8
00759 #define    TC49            1       // Timer/Counter4 bit 9
00760 #define    TC410           2       // Timer/Counter4 bit 10
00761 
00762 /* TCNT4 - Timer/Counter4 Low Bytes */
00763 #define    TC40            0       // Timer/Counter4 bit 0
00764 #define    TC41            1       // Timer/Counter4 bit 1
00765 #define    TC42            2       // Timer/Counter4 bit 2
00766 #define    TC43            3       // Timer/Counter4  bit 3
00767 #define    TC44            4       // Timer/Counter4 bit 4
00768 #define    TC45            5       // Timer/Counter4 bit 5
00769 #define    TC46            6       // Timer/Counter4 bit 6
00770 #define    TC47            7       // Timer/Counter4 bit 7
00771 
00772 /* TCCR4E - Timer/Counter 4 Control Register E */
00773 #define    OC4OE0          0       // Output Compare Override Enable bit
00774 #define    OC4OE1          1       // Output Compare Override Enable bit
00775 #define    OC4OE2          2       // Output Compare Override Enable bit
00776 #define    OC4OE3          3       // Output Compare Override Enable bit
00777 #define    OC4OE4          4       // Output Compare Override Enable bit
00778 #define    OC4OE5          5       // Output Compare Override Enable bit
00779 #define    ENHC4           6       // Enhanced Compare/PWM Mode
00780 #define    TLOCK4          7       // Register Update Lock
00781 
00782 /* TCCR4D - Timer/Counter 4 Control Register D */
00783 #define    WGM40           0       // Waveform Generation Mode bits
00784 #define    WGM41           1       // Waveform Generation Mode bits
00785 #define    FPF4            2       // Fault Protection Interrupt Flag
00786 #define    FPAC4           3       // Fault Protection Analog Comparator Enable
00787 #define    FPES4           4       // Fault Protection Edge Select
00788 #define    FPNC4           5       // Fault Protection Noise Canceler
00789 #define    FPEN4           6       // Fault Protection Mode Enable
00790 #define    FPIE4           7       // Fault Protection Interrupt Enable
00791 
00792 /* TCCR4C - Timer/Counter 4 Control Register C */
00793 #define    PWM4D           0       // Pulse Width Modulator D Enable
00794 #define    FOC4D           1       // Force Output Compare Match 4D
00795 #define    COM4D0          2       // Comparator D Output Mode
00796 #define    COM4D1          3       // Comparator D Output Mode
00797 #define    COM4B0S         4       // Comparator B Output Mode
00798 #define    COM4B1S         5       // Comparator B Output Mode
00799 #define    COM4A0S         6       // Comparator A Output Mode
00800 #define    COM4A1S         7       // Comparator A Output Mode
00801 
00802 /* TCCR4B - Timer/Counter4 Control Register B */
00803 #define    CS40            0       // Clock Select Bit 0
00804 #define    CS41            1       // Clock Select Bit 1
00805 #define    CS42            2       // Clock Select Bit 2
00806 #define    CS43            3       // Clock Select Bit 3
00807 #define    DTPS40          4       // Dead Time Prescaler Bit 0
00808 #define    DTPS41          5       // Dead Time Prescaler Bit 1
00809 #define    PSR4            6       // Prescaler Reset Timer/Counter 4
00810 #define    PWM4X           7       // PWM Inversion Mode
00811 
00812 /* TCCR4A - Timer/Counter4 Control Register A */
00813 #define    PWM4B           0       // 
00814 #define    PWM4A           1       // 
00815 #define    FOC4B           2       // Force Output Compare Match 4B
00816 #define    FOC4A           3       // Force Output Compare Match 4A
00817 #define    COM4B0          4       // Compare Output Mode 4B, bit 0
00818 #define    COM4B1          5       // Compare Output Mode 4B, bit 1
00819 #define    COM4A0          6       // Compare Output Mode 4A, bit 0
00820 #define    COM4A1          7       // Compare Output Mode 1A, bit 1
00821 
00822 
00823 /* ***** PORTB ************************ */
00824 /* PORTB - Port B Data Register */
00825 #define    PORTB0          0       // Port B Data Register bit 0
00826 #define    PORTB1          1       // Port B Data Register bit 1
00827 #define    PORTB2          2       // Port B Data Register bit 2
00828 #define    PORTB3          3       // Port B Data Register bit 3
00829 #define    PORTB4          4       // Port B Data Register bit 4
00830 #define    PORTB5          5       // Port B Data Register bit 5
00831 #define    PORTB6          6       // Port B Data Register bit 6
00832 #define    PORTB7          7       // Port B Data Register bit 7
00833 
00834 /* DDRB - Port B Data Direction Register */
00835 #define    DDB0            0       // Port B Data Direction Register bit 0
00836 #define    DDB1            1       // Port B Data Direction Register bit 1
00837 #define    DDB2            2       // Port B Data Direction Register bit 2
00838 #define    DDB3            3       // Port B Data Direction Register bit 3
00839 #define    DDB4            4       // Port B Data Direction Register bit 4
00840 #define    DDB5            5       // Port B Data Direction Register bit 5
00841 #define    DDB6            6       // Port B Data Direction Register bit 6
00842 #define    DDB7            7       // Port B Data Direction Register bit 7
00843 
00844 /* PINB - Port B Input Pins */
00845 #define    PINB0           0       // Port B Input Pins bit 0
00846 #define    PINB1           1       // Port B Input Pins bit 1
00847 #define    PINB2           2       // Port B Input Pins bit 2
00848 #define    PINB3           3       // Port B Input Pins bit 3
00849 #define    PINB4           4       // Port B Input Pins bit 4
00850 #define    PINB5           5       // Port B Input Pins bit 5
00851 #define    PINB6           6       // Port B Input Pins bit 6
00852 #define    PINB7           7       // Port B Input Pins bit 7
00853 
00854 
00855 /* ***** PORTC ************************ */
00856 /* PORTC - Port C Data Register */
00857 #define    PORTC6          6       // Port C Data Register bit 6
00858 #define    PORTC7          7       // Port C Data Register bit 7
00859 
00860 /* DDRC - Port C Data Direction Register */
00861 #define    DDC6            6       // Port C Data Direction Register bit 6
00862 #define    DDC7            7       // Port C Data Direction Register bit 7
00863 
00864 /* PINC - Port C Input Pins */
00865 #define    PINC6           6       // Port C Input Pins bit 6
00866 #define    PINC7           7       // Port C Input Pins bit 7
00867 
00868 
00869 /* ***** PORTE ************************ */
00870 /* PORTE - Data Register, Port E */
00871 #define    PORTE2          2       // 
00872 #define    PORTE6          6       // 
00873 
00874 /* DDRE - Data Direction Register, Port E */
00875 #define    DDE2            2       // 
00876 #define    DDE6            6       // 
00877 
00878 /* PINE - Input Pins, Port E */
00879 #define    PINE2           2       // 
00880 #define    PINE6           6       // 
00881 
00882 
00883 /* ***** PORTF ************************ */
00884 /* PORTF - Data Register, Port F */
00885 #define    PORTF0          0       // 
00886 #define    PORTF1          1       // 
00887 #define    PORTF4          4       // 
00888 #define    PORTF5          5       // 
00889 #define    PORTF6          6       // 
00890 #define    PORTF7          7       // 
00891 
00892 /* DDRF - Data Direction Register, Port F */
00893 #define    DDF0            0       // 
00894 #define    DDF1            1       // 
00895 #define    DDF4            4       // 
00896 #define    DDF5            5       // 
00897 #define    DDF6            6       // 
00898 #define    DDF7            7       // 
00899 
00900 /* PINF - Input Pins, Port F */
00901 #define    PINF0           0       // 
00902 #define    PINF1           1       // 
00903 #define    PINF4           4       // 
00904 #define    PINF5           5       // 
00905 #define    PINF6           6       // 
00906 #define    PINF7           7       // 
00907 
00908 
00909 /* ***** AD_CONVERTER ***************** */
00910 /* ADMUX - The ADC multiplexer Selection Register */
00911 #define    MUX0            0       // Analog Channel and Gain Selection Bits
00912 #define    MUX1            1       // Analog Channel and Gain Selection Bits
00913 #define    MUX2            2       // Analog Channel and Gain Selection Bits
00914 #define    MUX3            3       // Analog Channel and Gain Selection Bits
00915 #define    MUX4            4       // Analog Channel and Gain Selection Bits
00916 #define    ADLAR           5       // Left Adjust Result
00917 #define    REFS0           6       // Reference Selection Bit 0
00918 #define    REFS1           7       // Reference Selection Bit 1
00919 
00920 /* ADCSRA - The ADC Control and Status register */
00921 #define    ADPS0           0       // ADC  Prescaler Select Bits
00922 #define    ADPS1           1       // ADC  Prescaler Select Bits
00923 #define    ADPS2           2       // ADC  Prescaler Select Bits
00924 #define    ADIE            3       // ADC Interrupt Enable
00925 #define    ADIF            4       // ADC Interrupt Flag
00926 #define    ADATE           5       // ADC Auto Trigger Enable
00927 #define    ADSC            6       // ADC Start Conversion
00928 #define    ADEN            7       // ADC Enable
00929 
00930 /* ADCH - ADC Data Register High Byte */
00931 #define    ADCH0           0       // ADC Data Register High Byte Bit 0
00932 #define    ADCH1           1       // ADC Data Register High Byte Bit 1
00933 #define    ADCH2           2       // ADC Data Register High Byte Bit 2
00934 #define    ADCH3           3       // ADC Data Register High Byte Bit 3
00935 #define    ADCH4           4       // ADC Data Register High Byte Bit 4
00936 #define    ADCH5           5       // ADC Data Register High Byte Bit 5
00937 #define    ADCH6           6       // ADC Data Register High Byte Bit 6
00938 #define    ADCH7           7       // ADC Data Register High Byte Bit 7
00939 
00940 /* ADCL - ADC Data Register Low Byte */
00941 #define    ADCL0           0       // ADC Data Register Low Byte Bit 0
00942 #define    ADCL1           1       // ADC Data Register Low Byte Bit 1
00943 #define    ADCL2           2       // ADC Data Register Low Byte Bit 2
00944 #define    ADCL3           3       // ADC Data Register Low Byte Bit 3
00945 #define    ADCL4           4       // ADC Data Register Low Byte Bit 4
00946 #define    ADCL5           5       // ADC Data Register Low Byte Bit 5
00947 #define    ADCL6           6       // ADC Data Register Low Byte Bit 6
00948 #define    ADCL7           7       // ADC Data Register Low Byte Bit 7
00949 
00950 /* ADCSRB - ADC Control and Status Register B */
00951 #define    ADTS0           0       // ADC Auto Trigger Source 0
00952 #define    ADTS1           1       // ADC Auto Trigger Source 1
00953 #define    ADTS2           2       // ADC Auto Trigger Source 2
00954 #define    ADTS3           4       // ADC Auto Trigger Source 3
00955 #define    MUX5            5       // Analog Channel and Gain Selection Bits
00956 #define    ADHSM           7       // ADC High Speed Mode
00957 
00958 /* DIDR0 - Digital Input Disable Register 1 */
00959 #define    ADC0D           0       // ADC0 Digital input Disable
00960 #define    ADC1D           1       // ADC1 Digital input Disable
00961 #define    ADC2D           2       // ADC2 Digital input Disable
00962 #define    ADC3D           3       // ADC3 Digital input Disable
00963 #define    ADC4D           4       // ADC4 Digital input Disable
00964 #define    ADC5D           5       // ADC5 Digital input Disable
00965 #define    ADC6D           6       // ADC6 Digital input Disable
00966 #define    ADC7D           7       // ADC7 Digital input Disable
00967 
00968 /* DDIR2 - Digital Input Disable Register 1 */
00969 #define    ADC8D           0       // ADC8 Digital input Disable
00970 #define    ADC9D           1       // ADC9 Digital input Disable
00971 #define    ADC10D          2       // ADC10 Digital input Disable
00972 #define    ADC11D          3       // ADC11 Digital input Disable
00973 #define    ADC12D          4       // ADC12 Digital input Disable
00974 #define    ADC13D          5       // ADC13 Digital input Disable
00975 
00976 
00977 /* ***** ANALOG_COMPARATOR ************ */
00978 /* ADCSRB - ADC Control and Status Register B */
00979 #define    ACME            6       // Analog Comparator Multiplexer Enable
00980 
00981 /* ACSR - Analog Comparator Control And Status Register */
00982 #define    ACIS0           0       // Analog Comparator Interrupt Mode Select bit 0
00983 #define    ACIS1           1       // Analog Comparator Interrupt Mode Select bit 1
00984 #define    ACIC            2       // Analog Comparator Input Capture Enable
00985 #define    ACIE            3       // Analog Comparator Interrupt Enable
00986 #define    ACI             4       // Analog Comparator Interrupt Flag
00987 #define    ACO             5       // Analog Compare Output
00988 #define    ACBG            6       // Analog Comparator Bandgap Select
00989 #define    ACD             7       // Analog Comparator Disable
00990 
00991 /* DIDR1 -  */
00992 #define    AIN0D           0       // AIN0 Digital Input Disable
00993 #define    AIN1D           1       // AIN1 Digital Input Disable
00994 
00995 
00996 /* ***** CPU ************************** */
00997 /* SREG - Status Register */
00998 #define    SREG_C          0       // Carry Flag
00999 #define    SREG_Z          1       // Zero Flag
01000 #define    SREG_N          2       // Negative Flag
01001 #define    SREG_V          3       // Two's Complement Overflow Flag
01002 #define    SREG_S          4       // Sign Bit
01003 #define    SREG_H          5       // Half Carry Flag
01004 #define    SREG_T          6       // Bit Copy Storage
01005 #define    SREG_I          7       // Global Interrupt Enable
01006 
01007 /* MCUCR - MCU Control Register */
01008 #define    IVCE            0       // Interrupt Vector Change Enable
01009 #define    IVSEL           1       // Interrupt Vector Select
01010 #define    PUD             4       // Pull-up disable
01011 //#define  JTD             7       // JTAG Interface Disable
01012 
01013 /* MCUSR - MCU Status Register */
01014 #define    PORF            0       // Power-on reset flag
01015 #define    EXTRF           1       // External Reset Flag
01016 #define    BORF            2       // Brown-out Reset Flag
01017 #define    WDRF            3       // Watchdog Reset Flag
01018 //#define  JTRF            4       // JTAG Reset Flag
01019 
01020 /* OSCCAL - Oscillator Calibration Value */
01021 #define    CAL0            0       // Oscillator Calibration Value Bit0
01022 #define    CAL1            1       // Oscillator Calibration Value Bit1
01023 #define    CAL2            2       // Oscillator Calibration Value Bit2
01024 #define    CAL3            3       // Oscillator Calibration Value Bit3
01025 #define    CAL4            4       // Oscillator Calibration Value Bit4
01026 #define    CAL5            5       // Oscillator Calibration Value Bit5
01027 #define    CAL6            6       // Oscillator Calibration Value Bit6
01028 #define    CAL7            7       // Oscillator Calibration Value Bit7
01029 
01030 /* RCCTRL - Oscillator Control Register */
01031 #define    RCFREQ          0       // 
01032 
01033 /* CLKPR -  */
01034 #define    CLKPS0          0       // 
01035 #define    CLKPS1          1       // 
01036 #define    CLKPS2          2       // 
01037 #define    CLKPS3          3       // 
01038 #define    CLKPCE          7       // 
01039 
01040 /* SMCR - Sleep Mode Control Register */
01041 #define    SE              0       // Sleep Enable
01042 #define    SM0             1       // Sleep Mode Select bit 0
01043 #define    SM1             2       // Sleep Mode Select bit 1
01044 #define    SM2             3       // Sleep Mode Select bit 2
01045 
01046 /* RAMPZ - RAM Page Z Select Register */
01047 #define    RAMPZ0          0       // RAM Page Z Select Register Bit 0
01048 
01049 /* EIND - Extended Indirect Register */
01050 #define    EIND0           0       // Bit 0
01051 
01052 /* GPIOR2 - General Purpose IO Register 2 */
01053 #define    GPIOR20         0       // General Purpose IO Register 2 bit 0
01054 #define    GPIOR21         1       // General Purpose IO Register 2 bit 1
01055 #define    GPIOR22         2       // General Purpose IO Register 2 bit 2
01056 #define    GPIOR23         3       // General Purpose IO Register 2 bit 3
01057 #define    GPIOR24         4       // General Purpose IO Register 2 bit 4
01058 #define    GPIOR25         5       // General Purpose IO Register 2 bit 5
01059 #define    GPIOR26         6       // General Purpose IO Register 2 bit 6
01060 #define    GPIOR27         7       // General Purpose IO Register 2 bit 7
01061 
01062 /* GPIOR1 - General Purpose IO Register 1 */
01063 #define    GPIOR10         0       // General Purpose IO Register 1 bit 0
01064 #define    GPIOR11         1       // General Purpose IO Register 1 bit 1
01065 #define    GPIOR12         2       // General Purpose IO Register 1 bit 2
01066 #define    GPIOR13         3       // General Purpose IO Register 1 bit 3
01067 #define    GPIOR14         4       // General Purpose IO Register 1 bit 4
01068 #define    GPIOR15         5       // General Purpose IO Register 1 bit 5
01069 #define    GPIOR16         6       // General Purpose IO Register 1 bit 6
01070 #define    GPIOR17         7       // General Purpose IO Register 1 bit 7
01071 
01072 /* GPIOR0 - General Purpose IO Register 0 */
01073 #define    GPIOR00         0       // General Purpose IO Register 0 bit 0
01074 #define    GPIOR01         1       // General Purpose IO Register 0 bit 1
01075 #define    GPIOR02         2       // General Purpose IO Register 0 bit 2
01076 #define    GPIOR03         3       // General Purpose IO Register 0 bit 3
01077 #define    GPIOR04         4       // General Purpose IO Register 0 bit 4
01078 #define    GPIOR05         5       // General Purpose IO Register 0 bit 5
01079 #define    GPIOR06         6       // General Purpose IO Register 0 bit 6
01080 #define    GPIOR07         7       // General Purpose IO Register 0 bit 7
01081 
01082 /* PRR1 - Power Reduction Register1 */
01083 #define    PRUSART1        0       // Power Reduction USART1
01084 #define    PRTIM3          3       // Power Reduction Timer/Counter3
01085 #define    PRUSB           7       // Power Reduction USB
01086 
01087 /* PRR0 - Power Reduction Register0 */
01088 #define    PRADC           0       // Power Reduction ADC
01089 #define    PRUSART0        1       // Power Reduction USART
01090 #define    PRSPI           2       // Power Reduction Serial Peripheral Interface
01091 #define    PRTIM1          3       // Power Reduction Timer/Counter1
01092 #define    PRTIM0          5       // Power Reduction Timer/Counter0
01093 #define    PRTIM2          6       // Power Reduction Timer/Counter2
01094 #define    PRTWI           7       // Power Reduction TWI
01095 
01096 /* CLKSTA -  */
01097 #define    EXTON           0       // 
01098 #define    RCON            1       // 
01099 
01100 /* CLKSEL0 -  */
01101 #define    CLKS            0       // 
01102 #define    EXTE            2       // 
01103 #define    RCE             3       // 
01104 #define    EXSUT0          4       // 
01105 #define    EXSUT1          5       // 
01106 #define    RCSUT0          6       // 
01107 #define    RCSUT1          7       // 
01108 
01109 /* CLKSEL1 -  */
01110 #define    EXCKSEL0        0       // 
01111 #define    EXCKSEL1        1       // 
01112 #define    EXCKSEL2        2       // 
01113 #define    EXCKSEL3        3       // 
01114 #define    RCCKSEL0        4       // 
01115 #define    RCCKSEL1        5       // 
01116 #define    RCCKSEL2        6       // 
01117 #define    RCCKSEL3        7       // 
01118 
01119 
01120 /* ***** TIMER_COUNTER_2 ************** */
01121 /* TIMSK2 - Timer/Counter Interrupt Mask register */
01122 #define    TOIE2           0       // Timer/Counter2 Overflow Interrupt Enable
01123 #define    TOIE2A          TOIE2   // For compatibility
01124 #define    OCIE2A          1       // Timer/Counter2 Output Compare Match A Interrupt Enable
01125 #define    OCIE2B          2       // Timer/Counter2 Output Compare Match B Interrupt Enable
01126 
01127 /* TIFR2 - Timer/Counter Interrupt Flag Register */
01128 #define    TOV2            0       // Timer/Counter2 Overflow Flag
01129 #define    OCF2A           1       // Output Compare Flag 2A
01130 #define    OCF2B           2       // Output Compare Flag 2B
01131 
01132 /* TCCR2A - Timer/Counter2 Control Register A */
01133 #define    WGM20           0       // Waveform Genration Mode
01134 #define    WGM21           1       // Waveform Genration Mode
01135 #define    COM2B0          4       // Compare Output Mode bit 0
01136 #define    COM2B1          5       // Compare Output Mode bit 1
01137 #define    COM2A0          6       // Compare Output Mode bit 1
01138 #define    COM2A1          7       // Compare Output Mode bit 1
01139 
01140 /* TCCR2B - Timer/Counter2 Control Register B */
01141 #define    CS20            0       // Clock Select bit 0
01142 #define    CS21            1       // Clock Select bit 1
01143 #define    CS22            2       // Clock Select bit 2
01144 #define    WGM22           3       // Waveform Generation Mode
01145 #define    FOC2B           6       // Force Output Compare B
01146 #define    FOC2A           7       // Force Output Compare A
01147 
01148 /* TCNT2 - Timer/Counter2 */
01149 #define    TCNT2_0         0       // Timer/Counter 2 bit 0
01150 #define    TCNT2_1         1       // Timer/Counter 2 bit 1
01151 #define    TCNT2_2         2       // Timer/Counter 2 bit 2
01152 #define    TCNT2_3         3       // Timer/Counter 2 bit 3
01153 #define    TCNT2_4         4       // Timer/Counter 2 bit 4
01154 #define    TCNT2_5         5       // Timer/Counter 2 bit 5
01155 #define    TCNT2_6         6       // Timer/Counter 2 bit 6
01156 #define    TCNT2_7         7       // Timer/Counter 2 bit 7
01157 
01158 /* OCR2A - Timer/Counter2 Output Compare Register A */
01159 #define    OCR2_0          0       // Timer/Counter2 Output Compare Register Bit 0
01160 #define    OCR2_1          1       // Timer/Counter2 Output Compare Register Bit 1
01161 #define    OCR2_2          2       // Timer/Counter2 Output Compare Register Bit 2
01162 #define    OCR2_3          3       // Timer/Counter2 Output Compare Register Bit 3
01163 #define    OCR2_4          4       // Timer/Counter2 Output Compare Register Bit 4
01164 #define    OCR2_5          5       // Timer/Counter2 Output Compare Register Bit 5
01165 #define    OCR2_6          6       // Timer/Counter2 Output Compare Register Bit 6
01166 #define    OCR2_7          7       // Timer/Counter2 Output Compare Register Bit 7
01167 
01168 /* OCR2B - Timer/Counter2 Output Compare Register B */
01169 //#define  OCR2_0          0       // Timer/Counter2 Output Compare Register Bit 0
01170 //#define  OCR2_1          1       // Timer/Counter2 Output Compare Register Bit 1
01171 //#define  OCR2_2          2       // Timer/Counter2 Output Compare Register Bit 2
01172 //#define  OCR2_3          3       // Timer/Counter2 Output Compare Register Bit 3
01173 //#define  OCR2_4          4       // Timer/Counter2 Output Compare Register Bit 4
01174 //#define  OCR2_5          5       // Timer/Counter2 Output Compare Register Bit 5
01175 //#define  OCR2_6          6       // Timer/Counter2 Output Compare Register Bit 6
01176 //#define  OCR2_7          7       // Timer/Counter2 Output Compare Register Bit 7
01177 
01178 /* GTCCR - General Timer Counter Control register */
01179 #define    PSRASY          1       // Prescaler Reset Timer/Counter2
01180 #define    PSR2            PSRASY  // For compatibility
01181 //#define  TSM             7       // Timer/Counter Synchronization Mode
01182 
01183 
01184 /* ***** PLL ************************** */
01185 /* PLLCSR - PLL Status and Control register */
01186 #define    PLOCK           0       // PLL Lock Status Bit
01187 #define    PLLE            1       // PLL Enable Bit
01188 #define    PINDIV          4       // PLL prescaler Bit 2
01189 
01190 /* PLLFRQ - PLL Frequency Control Register */
01191 #define    PDIV0           0       // 
01192 #define    PDIV1           1       // 
01193 #define    PDIV2           2       // 
01194 #define    PDIV3           3       // 
01195 #define    PLLTM0          4       // 
01196 #define    PLLTM1          5       // 
01197 #define    PLLUSB          6       // 
01198 #define    PINMUX          7       // 
01199 
01200 
01201 /* ***** USB_DEVICE ******************* */
01202 /* USBCON - USB General Control Register */
01203 #define    VBUSTE          0       // 
01204 #define    OTGPADE         4       // 
01205 #define    FRZCLK          5       // 
01206 #define    USBE            7       // 
01207 
01208 /* UDCON -  */
01209 #define    DETACH          0       // 
01210 #define    RMWKUP          1       // 
01211 #define    LSM             2       // USB low speed mode
01212 #define    RSTCPU          3       // 
01213 
01214 /* UDINT -  */
01215 #define    SUSPI           0       // 
01216 #define    SOFI            2       // 
01217 #define    EORSTI          3       // 
01218 #define    WAKEUPI         4       // 
01219 #define    EORSMI          5       // 
01220 #define    UPRSMI          6       // 
01221 
01222 /* UDIEN -  */
01223 #define    SUSPE           0       // 
01224 #define    SOFE            2       // 
01225 #define    EORSTE          3       // 
01226 #define    WAKEUPE         4       // 
01227 #define    EORSME          5       // 
01228 #define    UPRSME          6       // 
01229 
01230 /* UDADDR -  */
01231 #define    UADD0           0       // 
01232 #define    UADD1           1       // 
01233 #define    UADD2           2       // 
01234 #define    UADD3           3       // 
01235 #define    UADD4           4       // 
01236 #define    UADD5           5       // 
01237 #define    UADD6           6       // 
01238 #define    ADDEN           7       // 
01239 
01240 /* UDFNUML -  */
01241 #define    FNUM0           0       // 
01242 #define    FNUM1           1       // 
01243 #define    FNUM2           2       // 
01244 #define    FNUM3           3       // 
01245 #define    FNUM4           4       // 
01246 #define    FNUM5           5       // 
01247 #define    FNUM6           6       // 
01248 #define    FNUM7           7       // 
01249 
01250 /* UDFNUMH -  */
01251 #define    FNUM8           0       // 
01252 #define    FNUM9           1       // 
01253 #define    FNUM10          2       // 
01254 
01255 /* UDMFN -  */
01256 #define    FNCERR          4       // 
01257 
01258 /* UEINTX -  */
01259 #define    TXINI           0       // 
01260 #define    STALLEDI        1       // 
01261 #define    RXOUTI          2       // 
01262 #define    RXSTPI          3       // 
01263 #define    NAKOUTI         4       // 
01264 #define    RWAL            5       // 
01265 #define    NAKINI          6       // 
01266 #define    FIFOCON         7       // 
01267 
01268 /* UENUM -  */
01269 #define    UENUM_0         0       // 
01270 #define    UENUM_1         1       // 
01271 #define    UENUM_2         2       // 
01272 
01273 /* UERST -  */
01274 #define    EPRST0          0       // 
01275 #define    EPRST1          1       // 
01276 #define    EPRST2          2       // 
01277 #define    EPRST3          3       // 
01278 #define    EPRST4          4       // 
01279 #define    EPRST5          5       // 
01280 #define    EPRST6          6       // 
01281 
01282 /* UECONX -  */
01283 #define    EPEN            0       // 
01284 #define    RSTDT           3       // 
01285 #define    STALLRQC        4       // 
01286 #define    STALLRQ         5       // 
01287 
01288 /* UECFG0X -  */
01289 #define    EPDIR           0       // 
01290 #define    EPTYPE0         6       // 
01291 #define    EPTYPE1         7       // 
01292 
01293 /* UECFG1X -  */
01294 #define    ALLOC           1       // 
01295 #define    EPBK0           2       // 
01296 #define    EPBK1           3       // 
01297 #define    EPSIZE0         4       // 
01298 #define    EPSIZE1         5       // 
01299 #define    EPSIZE2         6       // 
01300 
01301 /* UESTA0X -  */
01302 #define    NBUSYBK0        0       // 
01303 #define    NBUSYBK1        1       // 
01304 #define    DTSEQ0          2       // 
01305 #define    DTSEQ1          3       // 
01306 #define    UNDERFI         5       // 
01307 #define    OVERFI          6       // 
01308 #define    CFGOK           7       // 
01309 
01310 /* UESTA1X -  */
01311 #define    CURRBK0         0       // 
01312 #define    CURRBK1         1       // 
01313 #define    CTRLDIR         2       // 
01314 
01315 /* UEIENX -  */
01316 #define    TXINE           0       // 
01317 #define    STALLEDE        1       // 
01318 #define    RXOUTE          2       // 
01319 #define    RXSTPE          3       // 
01320 #define    NAKOUTE         4       // 
01321 #define    NAKINE          6       // 
01322 #define    FLERRE          7       // 
01323 
01324 /* UEDATX -  */
01325 #define    DAT0            0       // 
01326 #define    DAT1            1       // 
01327 #define    DAT2            2       // 
01328 #define    DAT3            3       // 
01329 #define    DAT4            4       // 
01330 #define    DAT5            5       // 
01331 #define    DAT6            6       // 
01332 #define    DAT7            7       // 
01333 
01334 /* UEBCLX -  */
01335 #define    BYCT0           0       // 
01336 #define    BYCT1           1       // 
01337 #define    BYCT2           2       // 
01338 #define    BYCT3           3       // 
01339 #define    BYCT4           4       // 
01340 #define    BYCT5           5       // 
01341 #define    BYCT6           6       // 
01342 #define    BYCT7           7       // 
01343 
01344 /* UEINT -  */
01345 #define    EPINT0          0       // 
01346 #define    EPINT1          1       // 
01347 #define    EPINT2          2       // 
01348 #define    EPINT3          3       // 
01349 #define    EPINT4          4       // 
01350 #define    EPINT5          5       // 
01351 #define    EPINT6          6       // 
01352 
01353 /* USBINT -  */
01354 #define    VBUSTI          0       // 
01355 
01356 /* USBSTA -  */
01357 #define    VBUS            0       // 
01358 #define    SPEED           3       // 
01359 
01360 /* USBCON - USB General Control Register */
01361 //#define  VBUSTE          0       // 
01362 //#define  OTGPADE         4       // 
01363 //#define  FRZCLK          5       // 
01364 //#define  USBE            7       // 
01365 
01366 /* UHWCON -  */
01367 #define    UVREGE          0       // 
01368 
01369 
01370 
01371 /* ***** LOCKSBITS ******************************************************** */
01372 #define    LB1             0       // Lock bit
01373 #define    LB2             1       // Lock bit
01374 #define    BLB01           2       // Boot Lock bit
01375 #define    BLB02           3       // Boot Lock bit
01376 #define    BLB11           4       // Boot lock bit
01377 #define    BLB12           5       // Boot lock bit
01378 
01379 
01380 /* ***** FUSES ************************************************************ */
01381 /* LOW fuse bits */
01382 #define    CKSEL0          0       // Select Clock Source
01383 #define    CKSEL1          1       // Select Clock Source
01384 #define    CKSEL2          2       // Select Clock Source
01385 #define    CKSEL3          3       // Select Clock Source
01386 #define    SUT0            4       // Select start-up time
01387 #define    SUT1            5       // Select start-up time
01388 #define    CKOUT           6       // Oscillator options
01389 #define    CKDIV8          7       // Divide clock by 8
01390 
01391 /* HIGH fuse bits */
01392 #define    BOOTRST         0       // Select Reset Vector
01393 #define    BOOTSZ0         1       // Select Boot Size
01394 #define    BOOTSZ1         2       // Select Boot Size
01395 #define    EESAVE          3       // EEPROM memory is preserved through chip erase
01396 #define    WDTON           4       // Watchdog timer always on
01397 #define    SPIEN           5       // Enable Serial programming and Data Downloading
01398 #define    JTAGEN          6       // Enable JTAG
01399 #define    OCDEN           7       // Enable OCD
01400 
01401 /* EXTENDED fuse bits */
01402 #define    BODLEVEL0       0       // Brown-out Detector trigger level
01403 #define    BODLEVEL1       1       // Brown-out Detector trigger level
01404 #define    BODLEVEL2       2       // Brown-out Detector trigger level
01405 #define    HWBE            3       // Hardware Boot Enable
01406 
01407 
01408 
01409 /* ***** CPU REGISTER DEFINITIONS ***************************************** */
01410 #define    XH              r27
01411 #define    XL              r26
01412 #define    YH              r29
01413 #define    YL              r28
01414 #define    ZH              r31
01415 #define    ZL              r30
01416 
01417 
01418 
01419 /* ***** DATA MEMORY DECLARATIONS ***************************************** */
01420 #define    FLASHEND        0x7fff  // Note: Byte address
01421 #define    IOEND           0x00ff
01422 #define    SRAM_START      0x0100
01423 #define    SRAM_SIZE       2560
01424 #define    RAMEND          0x0aff
01425 #define    XRAMEND         0xffff
01426 #define    E2END           0x03ff
01427 #define    EEPROMEND       0x03ff
01428 #define    EEADRBITS       10
01429 
01430 
01431 
01432 /* ***** BOOTLOADER DECLARATIONS ****************************************** */
01433 #define    NRWW_START_ADDR 0xf000
01434 #define    NRWW_STOP_ADDR  0xffff
01435 #define    RWW_START_ADDR  0x0
01436 #define    RWW_STOP_ADDR   0xefff
01437 #define    PAGESIZE        64
01438 #define    FIRSTBOOTSTART  0x3f00
01439 #define    SECONDBOOTSTART 0x3e00
01440 #define    THIRDBOOTSTART  0x3c00
01441 #define    FOURTHBOOTSTART 0x3800
01442 #define    SMALLBOOTSTART  FIRSTBOOTSTART
01443 #define    LARGEBOOTSTART  FOURTHBOOTSTART
01444 
01445 #endif /* ENABLE_BIT_DEFINITIONS */
01446 
01447 
01448 
01449 /* ***** INTERRUPT VECTORS ************************************************ */
01450 #define    RESET_vect      (0x00)  // External Pin,Power-on Reset,Brown-out Reset,Watchdog Reset,and JTAG AVR Reset. See Datasheet.
01451 #define    INT0_vect       (0x04)  // External Interrupt Request 0
01452 #define    INT1_vect       (0x08)  // External Interrupt Request 1
01453 #define    INT2_vect       (0x0c)  // External Interrupt Request 2
01454 #define    INT3_vect       (0x10)  // External Interrupt Request 3
01455 #define    Reserved1_vect  (0x14)  // Reserved1
01456 #define    Reserved2_vect  (0x18)  // Reserved2
01457 #define    INT6_vect       (0x1c)  // External Interrupt Request 6
01458 #define    Reserved3_vect  (0x20)  // Reserved3
01459 #define    PCINT0_vect     (0x24)  // Pin Change Interrupt Request 0
01460 #define    USB_GEN_vect    (0x28)  // USB General Interrupt Request
01461 #define    USB_COM_vect    (0x2c)  // USB Endpoint/Pipe Interrupt Communication Request
01462 #define    WDT_vect        (0x30)  // Watchdog Time-out Interrupt
01463 #define    Reserved4_vect  (0x34)  // Reserved4
01464 #define    Reserved5_vect  (0x38)  // Reserved5
01465 #define    Reserved6_vect  (0x3c)  // Reserved6
01466 #define    TIMER1_CAPT_vect (0x40)  // Timer/Counter1 Capture Event
01467 #define    TIMER1_COMPA_vect (0x44)  // Timer/Counter1 Compare Match A
01468 #define    TIMER1_COMPB_vect (0x48)  // Timer/Counter1 Compare Match B
01469 #define    TIMER1_COMPC_vect (0x4c)  // Timer/Counter1 Compare Match C
01470 #define    TIMER1_OVF_vect (0x50)  // Timer/Counter1 Overflow
01471 #define    TIMER0_COMPA_vect (0x54)  // Timer/Counter0 Compare Match A
01472 #define    TIMER0_COMPB_vect (0x58)  // Timer/Counter0 Compare Match B
01473 #define    TIMER0_OVF_vect (0x5c)  // Timer/Counter0 Overflow
01474 #define    SPI_STC_vect    (0x60)  // SPI Serial Transfer Complete
01475 #define    USART1_RX_vect (0x64)  // USART1, Rx Complete
01476 #define    USART1_UDRE_vect (0x68)  // USART1 Data register Empty
01477 #define    USART1_TX_vect (0x6c)  // USART1, Tx Complete
01478 #define    ANALOG_COMP_vect   (0x70)  // Analog Comparator
01479 #define    ADC_vect        (0x74)  // ADC Conversion Complete
01480 #define    EE_READY_vect     (0x78)  // EEPROM Ready
01481 #define    TIMER3_CAPT_vect (0x7c)  // Timer/Counter3 Capture Event
01482 #define    TIMER3_COMPA_vect (0x80)  // Timer/Counter3 Compare Match A
01483 #define    TIMER3_COMPB_vect (0x84)  // Timer/Counter3 Compare Match B
01484 #define    TIMER3_COMPC_vect (0x88)  // Timer/Counter3 Compare Match C
01485 #define    TIMER3_OVF_vect (0x8c)  // Timer/Counter3 Overflow
01486 #define    TWI_vect        (0x90)  // 2-wire Serial Interface
01487 #define    SPM_READY_vect    (0x94)  // Store Program Memory Read
01488 #define    TIMER4_COMPA_vect (0x98)  // Timer/Counter4 Compare Match A
01489 #define    TIMER4_COMPB_vect (0x9c)  // Timer/Counter4 Compare Match B
01490 #define    TIMER4_COMPD_vect (0xa0)  // Timer/Counter4 Compare Match D
01491 #define    TIMER4_OVF_vect (0xa4)  // Timer/Counter4 Overflow
01492 #define    TIMER4_FPF_vect (0xa8)  // Timer/Counter4 Fault Protection Interrupt
01493 
01494 
01495 
01496 #endif /* __IOM32U4_H (define part) */
01497 
01498 #pragma language=default
01499 
01500 #endif  /* __IOM32U4_H (SFR part)*/
01501 
01502 /* ***** END OF FILE ****************************************************** */