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00044 #ifndef EXT_INT_DRV_H
00045 #define EXT_INT_DRV_H
00046
00047
00048
00049
00053
00054
00058 #define Enable_int0_interrupt() (EIMSK|=(1<<INT0))
00059 #define Enable_int1_interrupt() (EIMSK|=(1<<INT1))
00060 #define Enable_int2_interrupt() (EIMSK|=(1<<INT2))
00061 #define Enable_int3_interrupt() (EIMSK|=(1<<INT3))
00062 #define Enable_int4_interrupt() (EIMSK|=(1<<INT4))
00063 #define Enable_int5_interrupt() (EIMSK|=(1<<INT5))
00064 #define Enable_int6_interrupt() (EIMSK|=(1<<INT6))
00065 #define Enable_int7_interrupt() (EIMSK|=(1<<INT7))
00066
00067
00071 #define Disable_int0_interrupt() (EIMSK&=~(1<<INT0))
00072 #define Disable_int1_interrupt() (EIMSK&=~(1<<INT1))
00073 #define Disable_int2_interrupt() (EIMSK&=~(1<<INT2))
00074 #define Disable_int3_interrupt() (EIMSK&=~(1<<INT3))
00075 #define Disable_int4_interrupt() (EIMSK&=~(1<<INT4))
00076 #define Disable_int5_interrupt() (EIMSK&=~(1<<INT5))
00077 #define Disable_int6_interrupt() (EIMSK&=~(1<<INT6))
00078 #define Disable_int7_interrupt() (EIMSK&=~(1<<INT7))
00079
00080
00084 #define Enable_pc_interrupt() (PCICR|=(1<<PCIE0))
00085 #define Enable_pcint0_interrupt() (PCMSK0|=(1<<PCINT0),Enable_pc_interrupt())
00086 #define Enable_pcint1_interrupt() (PCMSK0|=(1<<PCINT1),Enable_pc_interrupt())
00087 #define Enable_pcint2_interrupt() (PCMSK0|=(1<<PCINT2),Enable_pc_interrupt())
00088 #define Enable_pcint3_interrupt() (PCMSK0|=(1<<PCINT3),Enable_pc_interrupt())
00089 #define Enable_pcint4_interrupt() (PCMSK0|=(1<<PCINT4),Enable_pc_interrupt())
00090 #define Enable_pcint5_interrupt() (PCMSK0|=(1<<PCINT5),Enable_pc_interrupt())
00091 #define Enable_pcint6_interrupt() (PCMSK0|=(1<<PCINT6),Enable_pc_interrupt())
00092 #define Enable_pcint7_interrupt() (PCMSK0|=(1<<PCINT7),Enable_pc_interrupt())
00093
00094
00098 #define Disable_pc_interrupt() (PCICR|=~(1<<PCIE0))
00099 #define Disable_pcint0_interrupt() (PCMSK0&=~(1<<PCINT0))
00100 #define Disable_pcint1_interrupt() (PCMSK0&=~(1<<PCINT1))
00101 #define Disable_pcint2_interrupt() (PCMSK0&=~(1<<PCINT2))
00102 #define Disable_pcint3_interrupt() (PCMSK0&=~(1<<PCINT3))
00103 #define Disable_pcint4_interrupt() (PCMSK0&=~(1<<PCINT4))
00104 #define Disable_pcint5_interrupt() (PCMSK0&=~(1<<PCINT5))
00105 #define Disable_pcint6_interrupt() (PCMSK0&=~(1<<PCINT6))
00106 #define Disable_pcint7_interrupt() (PCMSK0&=~(1<<PCINT7))
00107
00108
00112 #define Configure_int0_low_level() (EICRA&=~((1<<ISC00)+(1<<ISC01)))
00113 #define Configure_int0_logic_change() (EICRA|=(1<<ISC00),EICRA&=~(1<<ISC01))
00114 #define Configure_int0_falling_edge() (EICRA&=~(1<<ISC00),EICRA|=(1<<ISC01))
00115 #define Configure_int0_rising_edge() (EICRA|=(1<<ISC00)+(1<<ISC01))
00116
00117
00121 #define Configure_int1_low_level() (EICRA&=~((1<<ISC10)+(1<<ISC11)))
00122 #define Configure_int1_logic_change() (EICRA|=(1<<ISC10),EICRA&=~(1<<ISC11))
00123 #define Configure_int1_falling_edge() (EICRA&=~(1<<ISC10),EICRA|=(1<<ISC11))
00124 #define Configure_int1_rising_edge() (EICRA|=(1<<ISC10)+(1<<ISC11))
00125
00126
00130 #define Configure_int2_low_level() (EICRA&=~((1<<ISC20)+(1<<ISC21)))
00131 #define Configure_int2_logic_change() (EICRA|=(1<<ISC20),EICRA&=~(1<<ISC21))
00132 #define Configure_int2_falling_edge() (EICRA&=~(1<<ISC20),EICRA|=(1<<ISC21))
00133 #define Configure_int2_rising_edge() (EICRA|=(1<<ISC20)+(1<<ISC21))
00134
00135
00139 #define Configure_int3_low_level() (EICRA&=~((1<<ISC30)+(1<<ISC31)))
00140 #define Configure_int3_logic_change() (EICRA|=(1<<ISC30),EICRA&=~(1<<ISC31))
00141 #define Configure_int3_falling_edge() (EICRA&=~(1<<ISC30),EICRA|=(1<<ISC31))
00142 #define Configure_int3_rising_edge() (EICRA|=(1<<ISC30)+(1<<ISC31))
00143
00144
00148 #define Configure_int4_low_level() (EICRB&=~((1<<ISC40)+(1<<ISC41)))
00149 #define Configure_int4_logic_change() (EICRB|=(1<<ISC40),EICRB&=~(1<<ISC41))
00150 #define Configure_int4_falling_edge() (EICRB&=~(1<<ISC40),EICRB|=(1<<ISC41))
00151 #define Configure_int4_rising_edge() (EICRB|=(1<<ISC40)+(1<<ISC41))
00152
00153
00157 #define Configure_int5_low_level() (EICRB&=~((1<<ISC50)+(1<<ISC51)))
00158 #define Configure_int5_logic_change() (EICRB|=(1<<ISC50),EICRB&=~(1<<ISC51))
00159 #define Configure_int5_falling_edge() (EICRB&=~(1<<ISC50),EICRB|=(1<<ISC51))
00160 #define Configure_int5_rising_edge() (EICRB|=(1<<ISC50)+(1<<ISC51))
00161
00162
00166 #define Configure_int6_low_level() (EICRB&=~((1<<ISC60)+(1<<ISC61)))
00167 #define Configure_int6_logic_change() (EICRB|=(1<<ISC60),EICRB&=~(1<<ISC61))
00168 #define Configure_int6_falling_edge() (EICRB&=~(1<<ISC60),EICRB|=(1<<ISC61))
00169 #define Configure_int6_rising_edge() (EICRB|=(1<<ISC60)+(1<<ISC61))
00170
00171
00175 #define Configure_int7_low_level() (EICRB&=~((1<<ISC70)+(1<<ISC71)))
00176 #define Configure_int7_logic_change() (EICRB|=(1<<ISC70),EICRB&=~(1<<ISC71))
00177 #define Configure_int7_falling_edge() (EICRB&=~(1<<ISC70),EICRB|=(1<<ISC71))
00178 #define Configure_int7_rising_edge() (EICRB|=(1<<ISC70)+(1<<ISC71))
00179
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00188
00189 #endif // EXT_INT_DRV_H