- Main Page
- Related Pages
- Modules
- Data Structures
- Files

- File List
- Globals

# ext_int_drv.h

Go to the documentation of this file.

    00001 /*This file is prepared for Doxygen automatic documentation generation.*/
    00013
    00014 /* Copyright (c) 2009 Atmel Corporation. All rights reserved.
    00015  *
    00016  * Redistribution and use in source and binary forms, with or without
    00017  * modification, are permitted provided that the following conditions are met:
    00018  *
    00019  * 1. Redistributions of source code must retain the above copyright notice,
    00020  * this list of conditions and the following disclaimer.
    00021  *
    00022  * 2. Redistributions in binary form must reproduce the above copyright notice,
    00023  * this list of conditions and the following disclaimer in the documentation
    00024  * and/or other materials provided with the distribution.
    00025  *
    00026  * 3. The name of Atmel may not be used to endorse or promote products derived
    00027  * from this software without specific prior written permission.
    00028  *
    00029  * 4. This software may only be redistributed and used in connection with an Atmel
    00030  * AVR product.
    00031  *
    00032  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
    00033  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    00034  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE EXPRESSLY AND
    00035  * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
    00036  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
    00037  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
    00038  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
    00039  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    00040  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
    00041  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    00042  */
    00043
    00044 #ifndef EXT_INT_DRV_H
    00045 #define EXT_INT_DRV_H
    00046
    00047 //_____ I N C L U D E S ____________________________________________________
    00048
    00049
    00053 //_____ M A C R O S ________________________________________________________
    00054
    00058 #define Enable_int0_interrupt()  (EIMSK|=(1<<INT0))
    00059 #define Enable_int1_interrupt()  (EIMSK|=(1<<INT1))
    00060 #define Enable_int2_interrupt()  (EIMSK|=(1<<INT2))
    00061 #define Enable_int3_interrupt()  (EIMSK|=(1<<INT3))
    00062 #define Enable_int4_interrupt()  (EIMSK|=(1<<INT4))
    00063 #define Enable_int5_interrupt()  (EIMSK|=(1<<INT5))
    00064 #define Enable_int6_interrupt()  (EIMSK|=(1<<INT6))
    00065 #define Enable_int7_interrupt()  (EIMSK|=(1<<INT7))
    00066
    00067
    00071 #define Disable_int0_interrupt()  (EIMSK&=~(1<<INT0))
    00072 #define Disable_int1_interrupt()  (EIMSK&=~(1<<INT1))
    00073 #define Disable_int2_interrupt()  (EIMSK&=~(1<<INT2))
    00074 #define Disable_int3_interrupt()  (EIMSK&=~(1<<INT3))
    00075 #define Disable_int4_interrupt()  (EIMSK&=~(1<<INT4))
    00076 #define Disable_int5_interrupt()  (EIMSK&=~(1<<INT5))
    00077 #define Disable_int6_interrupt()  (EIMSK&=~(1<<INT6))
    00078 #define Disable_int7_interrupt()  (EIMSK&=~(1<<INT7))
    00079
    00080
    00084 #define Enable_pc_interrupt()      (PCICR|=(1<<PCIE0))
    00085 #define Enable_pcint0_interrupt()  (PCMSK0|=(1<<PCINT0),Enable_pc_interrupt())
    00086 #define Enable_pcint1_interrupt()  (PCMSK0|=(1<<PCINT1),Enable_pc_interrupt())
    00087 #define Enable_pcint2_interrupt()  (PCMSK0|=(1<<PCINT2),Enable_pc_interrupt())
    00088 #define Enable_pcint3_interrupt()  (PCMSK0|=(1<<PCINT3),Enable_pc_interrupt())
    00089 #define Enable_pcint4_interrupt()  (PCMSK0|=(1<<PCINT4),Enable_pc_interrupt())
    00090 #define Enable_pcint5_interrupt()  (PCMSK0|=(1<<PCINT5),Enable_pc_interrupt())
    00091 #define Enable_pcint6_interrupt()  (PCMSK0|=(1<<PCINT6),Enable_pc_interrupt())
    00092 #define Enable_pcint7_interrupt()  (PCMSK0|=(1<<PCINT7),Enable_pc_interrupt())
    00093
    00094
    00098 #define Disable_pc_interrupt()      (PCICR|=~(1<<PCIE0))
    00099 #define Disable_pcint0_interrupt()  (PCMSK0&=~(1<<PCINT0))
    00100 #define Disable_pcint1_interrupt()  (PCMSK0&=~(1<<PCINT1))
    00101 #define Disable_pcint2_interrupt()  (PCMSK0&=~(1<<PCINT2))
    00102 #define Disable_pcint3_interrupt()  (PCMSK0&=~(1<<PCINT3))
    00103 #define Disable_pcint4_interrupt()  (PCMSK0&=~(1<<PCINT4))
    00104 #define Disable_pcint5_interrupt()  (PCMSK0&=~(1<<PCINT5))
    00105 #define Disable_pcint6_interrupt()  (PCMSK0&=~(1<<PCINT6))
    00106 #define Disable_pcint7_interrupt()  (PCMSK0&=~(1<<PCINT7))
    00107
    00108
    00112 #define Configure_int0_low_level()     (EICRA&=~((1<<ISC00)+(1<<ISC01)))
    00113 #define Configure_int0_logic_change()  (EICRA|=(1<<ISC00),EICRA&=~(1<<ISC01))
    00114 #define Configure_int0_falling_edge()  (EICRA&=~(1<<ISC00),EICRA|=(1<<ISC01))
    00115 #define Configure_int0_rising_edge()   (EICRA|=(1<<ISC00)+(1<<ISC01))
    00116
    00117
    00121 #define Configure_int1_low_level()     (EICRA&=~((1<<ISC10)+(1<<ISC11)))
    00122 #define Configure_int1_logic_change()  (EICRA|=(1<<ISC10),EICRA&=~(1<<ISC11))
    00123 #define Configure_int1_falling_edge()  (EICRA&=~(1<<ISC10),EICRA|=(1<<ISC11))
    00124 #define Configure_int1_rising_edge()   (EICRA|=(1<<ISC10)+(1<<ISC11))
    00125
    00126
    00130 #define Configure_int2_low_level()     (EICRA&=~((1<<ISC20)+(1<<ISC21)))
    00131 #define Configure_int2_logic_change()  (EICRA|=(1<<ISC20),EICRA&=~(1<<ISC21))
    00132 #define Configure_int2_falling_edge()  (EICRA&=~(1<<ISC20),EICRA|=(1<<ISC21))
    00133 #define Configure_int2_rising_edge()   (EICRA|=(1<<ISC20)+(1<<ISC21))
    00134
    00135
    00139 #define Configure_int3_low_level()     (EICRA&=~((1<<ISC30)+(1<<ISC31)))
    00140 #define Configure_int3_logic_change()  (EICRA|=(1<<ISC30),EICRA&=~(1<<ISC31))
    00141 #define Configure_int3_falling_edge()  (EICRA&=~(1<<ISC30),EICRA|=(1<<ISC31))
    00142 #define Configure_int3_rising_edge()   (EICRA|=(1<<ISC30)+(1<<ISC31))
    00143
    00144
    00148 #define Configure_int4_low_level()     (EICRB&=~((1<<ISC40)+(1<<ISC41)))
    00149 #define Configure_int4_logic_change()  (EICRB|=(1<<ISC40),EICRB&=~(1<<ISC41))
    00150 #define Configure_int4_falling_edge()  (EICRB&=~(1<<ISC40),EICRB|=(1<<ISC41))
    00151 #define Configure_int4_rising_edge()   (EICRB|=(1<<ISC40)+(1<<ISC41))
    00152
    00153
    00157 #define Configure_int5_low_level()     (EICRB&=~((1<<ISC50)+(1<<ISC51)))
    00158 #define Configure_int5_logic_change()  (EICRB|=(1<<ISC50),EICRB&=~(1<<ISC51))
    00159 #define Configure_int5_falling_edge()  (EICRB&=~(1<<ISC50),EICRB|=(1<<ISC51))
    00160 #define Configure_int5_rising_edge()   (EICRB|=(1<<ISC50)+(1<<ISC51))
    00161
    00162
    00166 #define Configure_int6_low_level()     (EICRB&=~((1<<ISC60)+(1<<ISC61)))
    00167 #define Configure_int6_logic_change()  (EICRB|=(1<<ISC60),EICRB&=~(1<<ISC61))
    00168 #define Configure_int6_falling_edge()  (EICRB&=~(1<<ISC60),EICRB|=(1<<ISC61))
    00169 #define Configure_int6_rising_edge()   (EICRB|=(1<<ISC60)+(1<<ISC61))
    00170
    00171
    00175 #define Configure_int7_low_level()     (EICRB&=~((1<<ISC70)+(1<<ISC71)))
    00176 #define Configure_int7_logic_change()  (EICRB|=(1<<ISC70),EICRB&=~(1<<ISC71))
    00177 #define Configure_int7_falling_edge()  (EICRB&=~(1<<ISC70),EICRB|=(1<<ISC71))
    00178 #define Configure_int7_rising_edge()   (EICRB|=(1<<ISC70)+(1<<ISC71))
    00179
    00180
    00182
    00183
    00184 //_____ D E F I N I T I O N S ______________________________________________
    00185
    00186 //_____ F U N C T I O N S __________________________________________________
    00187
    00188
    00189 #endif  // EXT_INT_DRV_H