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# pll_drv.h

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    00001 /*This file is prepared for Doxygen automatic documentation generation.*/
    00013
    00014 /* Copyright (c) 2009 Atmel Corporation. All rights reserved.
    00015  *
    00016  * Redistribution and use in source and binary forms, with or without
    00017  * modification, are permitted provided that the following conditions are met:
    00018  *
    00019  * 1. Redistributions of source code must retain the above copyright notice,
    00020  * this list of conditions and the following disclaimer.
    00021  *
    00022  * 2. Redistributions in binary form must reproduce the above copyright notice,
    00023  * this list of conditions and the following disclaimer in the documentation
    00024  * and/or other materials provided with the distribution.
    00025  *
    00026  * 3. The name of Atmel may not be used to endorse or promote products derived
    00027  * from this software without specific prior written permission.
    00028  *
    00029  * 4. This software may only be redistributed and used in connection with an Atmel
    00030  * AVR product.
    00031  *
    00032  * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED
    00033  * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
    00034  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE EXPRESSLY AND
    00035  * SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT,
    00036  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
    00037  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
    00038  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
    00039  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
    00040  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
    00041  * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
    00042  */
    00043
    00044
    00045 #ifndef PLL_DRV_H
    00046 #define PLL_DRV_H
    00047
    00048 //_____ I N C L U D E S ____________________________________________________
    00049
    00053 //_____ M A C R O S ________________________________________________________
    00054
    00058
    00059 #ifndef PLL_OUT_FRQ
    00060    #define  PLL_OUT_FRQ  PLL_OUT_96MHZ
    00061    #warning PLL_OUT_FRQ not defined in config file using 96MHz Default
    00062 #endif
    00063
    00064
    00065 #define PLL_IN_PRESCAL_DISABLE         ( 0<<PINDIV )
    00066 #define PLL_IN_PRESCAL_ENABLE          ( 1<<PINDIV )
    00067
    00068 #define PLL_OUT_32MHZ     ( (0<<PDIV3)| (O<<PDIV2) | (1<<PDIV1)| (0<<PDIV0))
    00069 #define PLL_OUT_40MHZ     ( (0<<PDIV3)| (O<<PDIV2) | (1<<PDIV1)| (1<<PDIV0))
    00070 #define PLL_OUT_48MHZ     ( (0<<PDIV3)| (1<<PDIV2) | (0<<PDIV1)| (0<<PDIV0))
    00071 #define PLL_OUT_56MHZ     ( (0<<PDIV3)| (1<<PDIV2) | (0<<PDIV1)| (1<<PDIV0))
    00072 #define PLL_OUT_64MHZ     ( (0<<PDIV3)| (1<<PDIV2) | (1<<PDIV1)| (0<<PDIV0))
    00073 #define PLL_OUT_72MHZ     ( (0<<PDIV3)| (1<<PDIV2) | (1<<PDIV1)| (1<<PDIVO))
    00074 #define PLL_OUT_80MHZ     ( (1<<PDIV3)| (0<<PDIV2) | (0<<PDIV1)| (0<<PDIVO))
    00075 #define PLL_OUT_88MHZ     ( (1<<PDIV3)| (0<<PDIV2) | (0<<PDIV1)| (1<<PDIV0))
    00076 #define PLL_OUT_96MHZ     ( (1<<PDIV3)| (0<<PDIV2) | (1<<PDIV1)| (0<<PDIV0))
    00077 #define PLL_OUT_MSK       ( (1<<PDIV3)| (1<<PDIV2) | (1<<PDIV1)| (1<<PDIV0))
    00078
    00079 #if (PLL_OUT_FRQ==PLL_OUT_96MHZ)
    00080    #define PLL_USB_DIV  (1<<PLLUSB)
    00081 #else
    00082    #define PLL_USB_DIV  (0<<PLLUSB)
    00083 #endif
    00084
    00085 #define PLL_HS_TMR_PSCAL_NULL          ( (0<<PLLTM1) | (0<<PLLTM0) )
    00086 #define PLL_HS_TMR_PSCAL_1             ( (0<<PLLTM1) | (1<<PLLTM0) )
    00087 #define PLL_HS_TMR_PSCAL_1DOT5         ( (1<<PLLTM1) | (0<<PLLTM0) )
    00088 #define PLL_HS_TMR_PSCAL_2             ( (1<<PLLTM1) | (1<<PLLTM0) )
    00089
    00090 #define PLL_HS_TMR_PSCAL_MSK           ( (1<<PLLTM1) | (1<<PLLTM0) )
    00091
    00092 #define Pll_set_hs_tmr_pscal_null()    (PLLFRQ&=~PLL_HS_TMR_PSCAL_MSK,PLLFRQ|=PLL_HS_TMR_PSCAL_NULL)
    00093 #define Pll_set_hs_tmr_pscal_1()       (PLLFRQ&=~PLL_HS_TMR_PSCAL_MSK,PLLFRQ|=PLL_HS_TMR_PSCAL_1)
    00094 #define Pll_set_hs_tmr_pscal_1dot5()   (PLLFRQ&=~PLL_HS_TMR_PSCAL_MSK,PLLFRQ|=PLL_HS_TMR_PSCAL_1DOT5)
    00095 #define Pll_set_hs_tmr_pscal_2()       (PLLFRQ&=~PLL_HS_TMR_PSCAL_MSK,PLLFRQ|=PLL_HS_TMR_PSCAL_2)
    00096
    00097
    00101 #if USB_LOW_SPEED_DEVICE==ENABLE
    00102 #define Start_pll(in_prescal)       \
    00103            (Set_RC_pll_clock(),PLLFRQ &= ~PLL_OUT_MSK,PLLFRQ|= PLL_OUT_FRQ| PLL_USB_DIV , PLLCSR = (in_prescal | (1<<PLLE)))
    00104 #else
    00105 #define Start_pll(in_prescal)       \
    00106            (PLLFRQ &= ~PLL_OUT_MSK,PLLFRQ|= PLL_OUT_FRQ| PLL_USB_DIV , PLLCSR = (in_prescal | (1<<PLLE)))
    00107 #endif
    00108
    00109 #define Is_pll_ready()       (PLLCSR & (1<<PLOCK) )
    00110
    00112 #define Wait_pll_ready()     while (!(PLLCSR & (1<<PLOCK)))
    00113
    00115 #define Stop_pll()           (PLLCSR  &= (~(1<<PLLE)),PLLCSR=0 )
    00116
    00118 #define Set_RC_pll_clock()    (PLLFRQ |= (1<<PINMUX))
    00119
    00121 #define Set_XTAL_pll_clock()    (PLLFRQ &= ~(1<<PINMUX))
    00122
    00123       // Start the PLL in autofactor mode
    00124       // regarding FOSC define
    00125 #if   (FOSC==8000)
    00126
    00127
    00128    #define Pll_start_auto()   Start_pll(PLL_IN_PRESCAL_DISABLE)
    00129 #elif (FOSC==16000)
    00130    #define Pll_start_auto()   Start_pll(PLL_IN_PRESCAL_ENABLE)
    00131 #else
    00132    #error   "FOSC should be defined in config.h"
    00133 #endif
    00134
    00136
    00137
    00138 /*
    00139       Example
    00140
    00141    Pll_start_auto();
    00142    Pll_set_hs_tmr_pscal_1dot5();
    00143    Timerhs_clear();
    00144    Timerhs_set_waveform_mode(TIMERHS_WGM_FAST_PWM);
    00145    Timerhs_set_nb_bit(8);
    00146
    00147    Timerhs_enable_pwm_a_and_na();
    00148    Timerhs_enable_pwm_b_and_nb();
    00149    Timerhs_enable_pwm_d_and_nd();
    00150
    00151    Timerhs_set_compare_a(dt);
    00152    Timerhs_set_compare_b(dt);
    00153    Timerhs_set_compare_d(dt);
    00154    Timerhs_set_clock(TIMERHS_CLK_BY_1);
    00155
    00156    while (1)
    00157    {
    00158       for(tempo=1;tempo;tempo++);
    00159       Timerhs_set_compare_a(dt++);
    00160       Timerhs_set_compare_b(dt++);
    00161       Timerhs_set_compare_d(dt++);
    00162    }
    00163 */
    00164
    00165
    00167 #endif  // PLL_DRV_H
    00168
    00169