Microcontroller Wireless Solutions


pal_mcu_generic.h
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00001 
00013 /*
00014  * Copyright (c) 2009, Atmel Corporation All rights reserved.
00015  *
00016  * Licensed under Atmel's Limited License Agreement --> EULA.txt
00017  */
00018 
00019 /* Prevent double inclusion */
00020 #ifndef PAL_MCU_GENERIC_H
00021 #define PAL_MCU_GENERIC_H
00022 
00023 /* === Includes =============================================================*/
00024 
00025 #include "pal_types.h"
00026 
00027 #if (PAL_TYPE == ATMEGA128RFA1)
00028 
00029 /*
00030  * This header file is required since pal_trx_frame_read() and
00031  * pal_trx_frame_write() depend on memcpy()
00032  */
00033 #include <string.h>
00034 
00035 /* === Types ================================================================*/
00036 
00041 typedef enum port_type_tag
00042 {
00043     PORT_B,
00044     PORT_D,
00045     PORT_E,
00046     PORT_F,
00047     PORT_G
00048 } port_type_t;
00049 
00053 typedef enum port_pin_direction_type_tag
00054 {
00055     DDR_B,
00056     DDR_D,
00057     DDR_E,
00058     DDR_F,
00059     DDR_G
00060 } port_pin_direction_type_t;
00061 
00062 /* === Externals ============================================================*/
00063 
00064 
00065 /* === Macros ===============================================================*/
00066 
00067 /*
00068  * Set TRX GPIO pins.
00069  */
00070 #define RST_HIGH()                      (TRXPR |= _BV(TRXRST))  
00071 #define RST_LOW()                       (TRXPR &= ~_BV(TRXRST)) 
00072 #define SLP_TR_HIGH()                   (TRXPR |= _BV(SLPTR))   
00073 #define SLP_TR_LOW()                    (TRXPR &= ~_BV(SLPTR))  
00077 #define CLEAR_TRX_IRQ_TX_END()          (IRQ_STATUS = _BV(TX_END))
00078 
00080 #define CLEAR_TRX_IRQ_TSTAMP()          (IRQ_STATUS = _BV(RX_START))
00081 
00083 #define CLEAR_TRX_IRQ_RX_END()          (IRQ_STATUS = _BV(RX_END))
00084 
00086 #define CLEAR_TRX_IRQ_CCA_ED()          (IRQ_STATUS = _BV(CCA_ED_DONE_EN))
00087 
00089 #define CLEAR_TRX_IRQ_AMI()             (IRQ_STATUS = _BV(AMI))
00090 
00092 #define CLEAR_TRX_IRQ_BATMON()          (BATMON = _BV(BAT_LOW))
00093 
00095 #define CLEAR_TRX_IRQ_AWAKE()           (IRQ_STATUS = _BV(AWAKE))
00096 
00098 #define CLEAR_TRX_IRQ_PLL_LOCK()        (IRQ_STATUS = _BV(PLL_LOCK))
00099 
00101 #define CLEAR_TRX_IRQ_PLL_UNLOCK()      (IRQ_STATUS = _BV(PLL_UNLOCK))
00102 
00103 /*
00104  * Note: TRX AES RDY is cleared on read/write of
00105  * AES_STATE, which has to be done in the AES
00106  * application.
00107  */
00108 
00109 
00111 #define ENABLE_GLOBAL_IRQ()             sei()
00112 
00114 #define DISABLE_GLOBAL_IRQ()            cli()
00115 
00117 #define ENTER_CRITICAL_REGION()         {uint8_t sreg = SREG; cli()
00118 
00120 #define LEAVE_CRITICAL_REGION()         SREG = sreg;}
00121 
00122 
00133 #define pal_trx_reg_write(addr, data) \
00134     (*(volatile uint8_t *)(addr)) = (data)
00135 
00147 #define pal_trx_reg_read(addr) \
00148     (*(volatile uint8_t *)(addr))
00149 
00160 #define pal_trx_frame_read(data, length) \
00161     memcpy((data), (void *)&TRXFBST, (length))
00162 
00172 #define pal_trx_frame_write(data, length) \
00173     memcpy((void *)&TRXFBST, (data), (length))
00174 
00175 #ifndef DOXYGEN
00176 #define _pal_trx_bit_read(addr, mask, pos) \
00177     (((*(volatile uint8_t *)(addr)) & (mask)) >> (pos))
00178 #endif
00179 
00187 #define pal_trx_bit_read(arg) \
00188     _pal_trx_bit_read(arg)
00189 
00190 #ifndef DOXYGEN
00191 #define _pal_trx_bit_write(addr, mask, pos, val) do {   \
00192         (*(volatile uint8_t *)(addr)) =                 \
00193             ((*(volatile uint8_t *)(addr)) & ~(mask)) | \
00194             (((val) << (pos)) & (mask));                \
00195     } while (0)
00196 #endif
00197 
00204 #define pal_trx_bit_write(arg1, val) \
00205     _pal_trx_bit_write(arg1, val)
00206 
00208 #define MIN_TIMEOUT                     (0x80)
00209 
00211 #define MAX_TIMEOUT                     (0x7FFFFFFF)
00212 
00213 
00215 #define MAX_NO_OF_TIMERS                (25)
00216 #if (MAX_NO_OF_TIMERS > 255)
00217 #error "MAX_NO_OF_TIMERS must not be larger than 255"
00218 #endif
00219 
00220 /*
00221  *  This macro is a place holder for delay function for high speed processors
00222  */
00223 #if ((F_CPU == (16000000UL)) || (F_CPU == (15384600UL)))
00224 #define PAL_WAIT_1_US()                 {nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); \
00225                                          nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); }
00226 #elif (F_CPU == (8000000UL))
00227 #define PAL_WAIT_1_US()                 {nop(); nop(); nop(); nop(); nop(); nop(); nop(); nop(); }
00228 #else
00229 #error "Unsupported F_CPU value"
00230 #endif
00231 
00232 
00233 
00234 
00235 /* === Prototypes ===========================================================*/
00236 
00237 #ifdef __cplusplus
00238 extern "C" {
00239 #endif
00240 
00241 
00242 #ifdef __cplusplus
00243 } /* extern "C" */
00244 #endif
00245 
00246 
00247 #endif /* (PAL_TYPE == ATMEGA128RFA1) */
00248 
00249 #endif /* PAL_MCU_GENERIC_H */
00250 
00251 /* EOF */