pal_irq.c

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/*
 * Copyright (c) 2009, Atmel Corporation All rights reserved.
 *
 * Licensed under Atmel's Limited License Agreement --> EULA.txt
 */

/* === Includes ============================================================ */

#include <stdint.h>
#include "pal.h"

#if (PAL_TYPE == ATMEGA128RFA1)

/* === Types =============================================================== */


/* === Externals =========================================================== */

#ifdef WATCHDOG_TIMER
#include "pal_timer.h"
extern volatile bool timer_trigger;
extern timer_info_t timer_array[TOTAL_NUMBER_OF_TIMERS];
extern uint8_t running_timers;
#endif

/* === Globals ============================================================= */

/*
 * Function pointers to store the callback function of
 * the transceiver interrupt
 */
static irq_handler_t irq_hdl_trx_tx_end;
static irq_handler_t irq_hdl_trx_rx_end;
static irq_handler_t irq_hdl_trx_cca_ed;

#if (defined BEACON_SUPPORT) || (defined ENABLE_TSTAMP) || (defined DOXYGEN)

static irq_handler_t irq_hdl_trx_tstamp;
#endif

#if (defined ENABLE_ALL_TRX_IRQS) || (defined DOXYGEN)

static irq_handler_t irq_hdl_trx_awake;
static irq_handler_t irq_hdl_trx_ami;
static irq_handler_t irq_hdl_trx_batmon;
static irq_handler_t irq_hdl_trx_pll_lock;
static irq_handler_t irq_hdl_trx_pll_unlock;
static irq_handler_t irq_hdl_trx_aes_ready;
#endif  /* ENABLE_ALL_TRX_IRQS */

/* === Prototypes ========================================================== */


/* === Implementation ====================================================== */

void pal_trx_irq_init_tx_end(FUNC_PTR trx_irq_cb)
{
    irq_hdl_trx_tx_end = (irq_handler_t)trx_irq_cb;
}


void pal_trx_irq_init_rx_end(FUNC_PTR trx_irq_cb)
{
    irq_hdl_trx_rx_end = (irq_handler_t)trx_irq_cb;
}


void pal_trx_irq_init_cca_ed(FUNC_PTR trx_irq_cb)
{
    irq_hdl_trx_cca_ed = (irq_handler_t)trx_irq_cb;
}


#if (defined BEACON_SUPPORT) || (defined ENABLE_TSTAMP) || (defined DOXYGEN)

void pal_trx_irq_init_tstamp(FUNC_PTR trx_irq_cb)
{
    irq_hdl_trx_tstamp = (irq_handler_t)trx_irq_cb;
}
#endif  /* #if (defined BEACON_SUPPORT) || (defined ENABLE_TSTAMP) || (defined DOXYGEN) */


#if defined(ENABLE_ALL_TRX_IRQS) || defined(DOXYGEN)

void pal_trx_irq_init_awake(FUNC_PTR trx_irq_cb)
{
    irq_hdl_trx_awake = (irq_handler_t)trx_irq_cb;
}


void pal_trx_irq_init_ami(FUNC_PTR trx_irq_cb)
{
    irq_hdl_trx_ami = (irq_handler_t)trx_irq_cb;
}


void pal_trx_irq_init_batmon(FUNC_PTR trx_irq_cb)
{
    irq_hdl_trx_batmon = (irq_handler_t)trx_irq_cb;
}


void pal_trx_irq_init_pll_lock(FUNC_PTR trx_irq_cb)
{
    irq_hdl_trx_pll_lock = (irq_handler_t)trx_irq_cb;
}


void pal_trx_irq_init_pll_unlock(FUNC_PTR trx_irq_cb)
{
    irq_hdl_trx_pll_unlock = (irq_handler_t)trx_irq_cb;
}


void pal_trx_irq_init_aes_ready(FUNC_PTR trx_irq_cb)
{
    irq_hdl_trx_aes_ready = (irq_handler_t)trx_irq_cb;
}
#endif  /* ENABLE_ALL_TRX_IRQS */


ISR(TRX24_TX_END_vect)
{
    irq_hdl_trx_tx_end();
}

ISR(TRX24_RX_END_vect)
{
    irq_hdl_trx_rx_end();
}

ISR(TRX24_CCA_ED_DONE_vect)
{
    irq_hdl_trx_cca_ed();
}

ISR(TRX24_AWAKE_vect)
{
#ifdef ENABLE_ALL_TRX_IRQS
    irq_hdl_trx_awake();
#endif
}

ISR(TRX24_RX_START_vect)
{
#if (defined BEACON_SUPPORT) || (defined ENABLE_TSTAMP)
    irq_hdl_trx_tstamp();
#endif  /* #if (defined BEACON_SUPPORT) || (defined ENABLE_TSTAMP) */
}

ISR(TRX24_PLL_LOCK_vect)
{
#ifdef ENABLE_ALL_TRX_IRQS
    irq_hdl_trx_pll_lock();
#endif  /*  ENABLE_ALL_TRX_IRQS*/
}

ISR(TRX24_PLL_UNLOCK_vect)
{
#ifdef ENABLE_ALL_TRX_IRQS
    irq_hdl_trx_pll_unlock();
#endif  /*  ENABLE_ALL_TRX_IRQS*/
}

ISR(TRX24_XAH_AMI_vect)
{
#ifdef ENABLE_ALL_TRX_IRQS
    irq_hdl_trx_ami();
#endif  /*  ENABLE_ALL_TRX_IRQS*/
}

ISR(BAT_LOW_vect)
{
#ifdef ENABLE_ALL_TRX_IRQS
    irq_hdl_trx_batmon();
#endif  /*  ENABLE_ALL_TRX_IRQS*/
}

ISR(AES_READY_vect)
{
#ifdef ENABLE_ALL_TRX_IRQS
    irq_hdl_trx_aes_ready();
#endif  /*  ENABLE_ALL_TRX_IRQS*/
}


#if defined(WATCHDOG_TIMER) || defined(DOXYGEN)

ISR(WDT_vect)
{
    /* Disable Watchdog Interrupt Mode */
    WDTCSR &= ~(1 << WDIE);

#ifdef NO_32KHZ_CRYSTAL
    /* Wakeup the trx to enable clock source for symbol counter. */
    PAL_SLP_TR_LOW();

    /* Adjust system time */
    uint32_t cnt_val = SC_READ32(SCCNT) & MASK_LOW28;
    cnt_val += WDT_WAKEUP_INTERVAL_US / PAL_US_PER_SYMBOLS;
    cnt_val &= MASK_LOW28;
    SC_WRITE32(SCCNT, cnt_val);

    /* Check for any pending timer event. */
    uint32_t now;
    pal_get_current_time(&now);

    /* Check for any pending timer event */
    if (running_timers > 0)
    {
        for (uint8_t i = 0; i < TOTAL_NUMBER_OF_TIMERS; i++)
        {
            if (timer_array[i].timer_cb != NULL)
            {
                if (now >= timer_array[i].abs_exp_timer)
                {
                    /* Trigger timer event handling */
                    timer_trigger = true;
                    break;
                }
            }
        }
    }

    /* Wait until 16MHz oscillator is ready. */
    while (pal_trx_bit_read(SR_TRX_STATUS) != TRX_OFF)
    {
        /* wait */
        /* Reduce CPU clock speed (1 MHz) to consume less power during wait period. */
        clock_prescale_set(clock_div_8);
    }
    /* Restore to 16MHz CPU clock speed. */
#if (F_CPU == 16000000)
    clock_prescale_set(0x0F);
#endif
#if (F_CPU == 8000000)
    clock_prescale_set(clock_div_1);
#endif
#if (F_CPU == 4000000)
    clock_prescale_set(clock_div_2);
#endif

    /* Toggle AS2 to trigger internal 32kHz crystal oscillator output. */
    ASSR = _BV(AS2);
    ASSR &= ~_BV(AS2);
#endif
}
#endif


#endif /* (PAL_TYPE == ATMEGA128RFA1) */

/* EOF */