Extended Configuration of RX_AACK mode

The radio transceiver provides lots of configuration possibilities. They allow an operation in RX_AACK mode even though the received frame did not match the IEEE 802.15.4-2006 filter rules. Also, extended features are activated using certain configuration bits.

The table below lists all configuration bits, which are useful in RX_AACK mode, its programming is shown in the MSC below.

Parameter	Sub Register Bit	Explanation	References
safe_mode	SR_RX_SAFE_MODE	Protect buffer after frame reception	Dynamic Frame Buffer Protection
prom_mode	SR_AACK_PROM_MODE	Support promiscuous mode	Sniffer configuration
ack_time	SR_AACK_ACK_TIME	Change auto acknowledge start time	Enable shorter ACK frame start time
upld_res_ft_mode	SR_AACK_UPLD_RES_FT	Enable reserved frame type reception	Enable reception of reserved frame types
fltr_res_ft	SR_AACK_FLTR_RES_FT	Filter reserved frame types like data frame type "Enable reception of reserved frame types"	Enable reception of reserved frame types
dis_ack	SR_AACK_DIS_ACK	Disable generation of acknowledgment	Sniffer configuration
fvn_mode	SR_AACK_FVN_MODE	Controls the ACK behavior, depending on FCF frame version number	Examples for IEEE 802.15.4 compliant RX_AACK Configuration Examples for non-IEEE-802.15.4-compliant RX_AACK Configurations

Configurations which lead to a standard compliant behavior are described in:

• Address Filter Configuration
• Configuration of RX_AACK mode
• Setting Data Pending Bit
• Setting Data Pending Bit during Frame Reception

Take a look at the examples for IEEE 802.15.4.compliant behavior and non-IEEE. 802.15.4. compliant behavior For a detailed description refer to section 7.2.3.1 of the datasheet.

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PHY_CFG_RX_AACK_EXT

Code example

    /* AT86RF231::[CONFIG] && MCU::[Frame Handling] */
    trx_bit_write(SR_RX_SAFE_MODE, safe_mode);
    trx_bit_write(SR_AACK_PROM_MODE, prom_mode);
    trx_bit_write(SR_AACK_ACK_TIME, ack_time);
    trx_bit_write(SR_AACK_UPLD_RES_FT, upld_res_ft);
    trx_bit_write(SR_AACK_FLTR_RES_FT, fltr_res_ft);
    trx_bit_write(SR_AACK_DIS_ACK, dis_ack);
    trx_bit_write(SR_AACK_FVN_MODE, fvn_mode);
    trx_bit_write(SR_AACK_SET_PD, pendd);
    /* MCU::[Addr. Filter] */
    trx_reg_write(RG_PAN_ID_0, panid_7_0);
    trx_reg_write(RG_PAN_ID_1, panid_15_8);
    trx_reg_write(RG_SHORT_ADDR_0, short_addr_7_0);
    trx_reg_write(RG_SHORT_ADDR_1, short_addr_15_8);
    trx_reg_write(RG_IEEE_ADDR_0, ext_addr_7_0);
    trx_reg_write(RG_IEEE_ADDR_1, ext_addr_15_8);
    trx_reg_write(RG_IEEE_ADDR_2, ext_addr_23_16);
    trx_reg_write(RG_IEEE_ADDR_3, ext_addr_31_24);
    trx_reg_write(RG_IEEE_ADDR_4, ext_addr_39_32);
    trx_reg_write(RG_IEEE_ADDR_5, ext_addr_47_40);
    trx_reg_write(RG_IEEE_ADDR_6, ext_addr_55_48);
    trx_reg_write(RG_IEEE_ADDR_7, ext_addr_63_56);
    /* MCU::[Network] */
    trx_bit_write(SR_AACK_I_AM_COORD, coord);
    trx_bit_write(SR_SLOTTED_OPERATION, slmode);

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