Examples for IEEE 802.15.4 compliant RX_AACK Configuration

This chapter provides configuration examples that will enable the transceiver to act as an IEEE-802.15.4-compliant network node when put into RX_AACK mode.

An IEEE 802.15.4 network node can be operated as:

• Device
• PAN Coordinator
• Promiscuous Mode Device/Sniffer

Use Cases:

• CFG_IEEE_DEVICE
• CFG_IEEE_COORDINATOR
• CFG_IEEE_SNIFFER

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CFG_IEEE_DEVICE

The following sequence configures the transceiver as a IEEE-802.15.4-compliant normal network device without PAN coordinator functionality when using the RX_AACK mode.

1. Configure the address filter: panid, short_addr, ext_addr.
2. Configure frame buffer protection: safe_mode.
3. Configure slotted operation: slmode.
4. Configure, which IEEE 802.15.4 frame versions have to be processed: fvn_mode.
5. Disable promiscuous mode: prom_mode = 0.
6. Disable PAN coordinator behavior: coord = 0.
7. Disable short Ack timing: ack_time = 0.
8. Disable processing of reserved frame types: fltr_res_ft = 0, upld_res_ft_mode = 0.
9. Enable automatic acknowledgement frame generation: dis_ack = 0.

Note:

• The order of the steps may be changed.
• The parameters prom_mode, coord, ack_time, fltr_res_ft, upld_res_ft_mode, dis_ack are configured according to the reset values of the respective registers. Therefore they do not need to be reconfigured after reset.

Example
A valid configuration sequence for a normal network device is:

Code example

    /* AT86RF231::[CONFIG] */
    trx_reg_write(RG_PAN_ID_0, panid_7_0);
    trx_reg_write(RG_PAN_ID_1, panid_15_8);
    trx_reg_write(RG_SHORT_ADDR_0, short_addr_7_0);
    trx_reg_write(RG_SHORT_ADDR_1, short_addr_15_8);
    trx_reg_write(RG_IEEE_ADDR_0, ext_addr_7_0);
    trx_reg_write(RG_IEEE_ADDR_1, ext_addr_15_8);
    trx_reg_write(RG_IEEE_ADDR_2, ext_addr_23_16);
    trx_reg_write(RG_IEEE_ADDR_3, ext_addr_31_24);
    trx_reg_write(RG_IEEE_ADDR_4, ext_addr_39_32);
    trx_reg_write(RG_IEEE_ADDR_5, ext_addr_47_40);
    trx_reg_write(RG_IEEE_ADDR_6, ext_addr_55_48);
    trx_reg_write(RG_IEEE_ADDR_7, ext_addr_63_56);
    trx_bit_write(SR_RX_SAFE_MODE, safe_mode);
    trx_bit_write(SR_SLOTTED_OPERATION, slotted_op);
    trx_bit_write(SR_AACK_FVN_MODE, fvn_mode);
    trx_bit_write(SR_AACK_PROM_MODE, 0);
    trx_bit_write(SR_AACK_I_AM_COORD, 0);
    trx_bit_write(SR_AACK_ACK_TIME, 0);
    trx_bit_write(SR_AACK_UPLD_RES_FT, 0);
    trx_bit_write(SR_AACK_FLTR_RES_FT, 0);
    trx_bit_write(SR_AACK_DIS_ACK, 0);

CFG_IEEE_COORDINATOR

The list below describes the configuration of the radio transceiver as an IEEE 802.15.4 PAN coordinator.

Compared to a device node, a PAN coordinator implements different address filtering mechanisms, which is described in detail in section section 7.2.3.5 (Frame Filter) of the AT86RF231 datasheet.

1. Configure the address filter: panid, short_addr, ext_addr.
2. Configure frame buffer protection: safe_mode.
3. Configure slotted operation: slmode.
4. Configure, which IEEE 802.15.4 frame versions have to be processed: fvn_mode.
5. Disable promiscuous mode: prom_mode = 0.
6. Enable PAN coordinator behavior: coord = 1.
7. Disable short Ack timing: ack_time = 0.
8. Disable processing of reserved frame types: fltr_res_ft = 0, upld_res_ft_mode = 0.
9. Enable automatic acknowledgement frame generation: dis_ack = 0.

Note:

• The order of the steps may be changed.
• The parameters prom_mode, ack_time, fltr_res_ft, upld_res_ft_mode, dis_ack are configured according to the reset values of the respective registers. Therefore they do not need to be reconfigured after reset.

Example

Code example

    /* AT86RF231::[CONFIG] */
    trx_reg_write(RG_PAN_ID_0, panid_7_0);
    trx_reg_write(RG_PAN_ID_1, panid_15_8);
    trx_reg_write(RG_SHORT_ADDR_0, short_addr_7_0);
    trx_reg_write(RG_SHORT_ADDR_1, short_addr_15_8);
    trx_reg_write(RG_IEEE_ADDR_0, ext_addr_7_0);
    trx_reg_write(RG_IEEE_ADDR_1, ext_addr_15_8);
    trx_reg_write(RG_IEEE_ADDR_2, ext_addr_23_16);
    trx_reg_write(RG_IEEE_ADDR_3, ext_addr_31_24);
    trx_reg_write(RG_IEEE_ADDR_4, ext_addr_39_32);
    trx_reg_write(RG_IEEE_ADDR_5, ext_addr_47_40);
    trx_reg_write(RG_IEEE_ADDR_6, ext_addr_55_48);
    trx_reg_write(RG_IEEE_ADDR_7, ext_addr_63_56);
    trx_bit_write(SR_RX_SAFE_MODE, safe_mode);
    trx_bit_write(SR_SLOTTED_OPERATION, slotted_op);
    trx_bit_write(SR_AACK_FVN_MODE, fvn_mode);
    trx_bit_write(SR_AACK_PROM_MODE, 0);
    trx_bit_write(SR_AACK_I_AM_COORD, 1);
    trx_bit_write(SR_AACK_ACK_TIME, 0);
    trx_bit_write(SR_AACK_UPLD_RES_FT, 0);
    trx_bit_write(SR_AACK_FLTR_RES_FT, 0);
    trx_bit_write(SR_AACK_DIS_ACK, 0);

CFG_IEEE_SNIFFER

The following sequence configures the transceiver as a IEEE-802.15.4-2006-compliant promiscuous mode device (sniffer) when using the RX_AACK receive mode. Compared to a device node, a radio transceiver in promiscuous mode does not do address filtering and must not acknowledge received frames.

1. Configure the address filter: panid, short_addr, ext_addr.
2. Configure frame buffer protection: safe_mode.
3. Configure, which IEEE 802.15.4 frame versions have to be processed: fvn_mode.
4. Enable promiscuous mode: prom_mode = 1.
5. Disable PAN coordinator behavior: coord = 0.
6. Disable processing of reserved frame types: fltr_res_ft = 0, upld_res_ft_mode = 0.
7. Disable automatic acknowledgement frame generation: dis_ack = 1.

Note:

• The order of the steps may be changed.
• Instead of using RX_AACK in promiscuous mode, receiving frames in the RX_ON mode will lead to the same behavior, since no frame filtering is done.
• Since no automatic acknowledgement is performed (SR_AACK_DIS_ACK =1), the parameters slmode and ack_time are ignored. The parameters coord, fltr_res_ft, and upld_res_ft_mode are configured according to the reset values of the respective registers. Therefore they do not need to be reconfigured after reset.

Example
A valid configuration sequence for a sniffer device is:

Code example

    /* AT86RF231::[CONFIG] */
    trx_reg_write(RG_PAN_ID_0, 0);
    trx_reg_write(RG_PAN_ID_1, 0);
    trx_reg_write(RG_SHORT_ADDR_0, 0);
    trx_reg_write(RG_SHORT_ADDR_1, 0);
    trx_reg_write(RG_IEEE_ADDR_0, 0);
    trx_reg_write(RG_IEEE_ADDR_1, 0);
    trx_reg_write(RG_IEEE_ADDR_2, 0);
    trx_reg_write(RG_IEEE_ADDR_3, 0);
    trx_reg_write(RG_IEEE_ADDR_4, 0);
    trx_reg_write(RG_IEEE_ADDR_5, 0);
    trx_reg_write(RG_IEEE_ADDR_6, 0);
    trx_reg_write(RG_IEEE_ADDR_7, 0);
    trx_bit_write(SR_RX_SAFE_MODE, safe_mode);
    trx_bit_write(SR_AACK_FVN_MODE, fvn_mode);
    trx_bit_write(SR_AACK_PROM_MODE, 1);
    trx_bit_write(SR_AACK_I_AM_COORD, 0);
    trx_bit_write(SR_AACK_UPLD_RES_FT, 0);
    trx_bit_write(SR_AACK_FLTR_RES_FT, 0);
    trx_bit_write(SR_AACK_DIS_ACK, 1);

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