Interrupt Configuration and Handling

The interrupt signal on pin TRX_PIN_IRQ can be configured regarding to the masking of interrupt causes (see IRQ Mask Configuration) and to the signal polarity (see IRQ Polarity Configuration). A more detailed description can also be found section 6.6 (Interrupt Logic) of the AT86RF231 datasheet. The configuration of TRX_PIN_DIG2 is described in section RX Frame Time Stamping.

Use Cases:

• IRQ Mask Configuration
• IRQ Polarity Configuration
• IRQ Handling

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IRQ Mask Configuration

The value of the register RG_IRQ_MASK determines, which of the interrupt causes generate interrupt requests at TRX_PIN_IRQ. Additionally the generation of interrupt events can be controlled with the subregister SR_IRQ_MASK_MODE.

Parameters:

	mskirqs	The mask value, which is written to RG_IRQ_MASK. An IRQ is signalled on TRX_PIN_IRQ, if the apropriate bit in this register is set to 1.
	mskmode	IRQ mask mode. {0} : Only IRQs are enabled by mskirqs will be shown in RG_IRQ_STATUS. {1} : All IRQs will be shown in RG_IRQ_STATUS.

The following table explains the interrupt behavior for combinations of mskirqs and mskmode.

mskirqs	mskmode	Description
0	0	IRQ is suppressed entirely and none of interrupt causes is shown in RG_IRQ_STATUS
0	1	IRQ is suppressed entirely but all interrupt causes are shown in RG_IRQ_STATUS
[IC]	0	All by [IC] enabled IRQs are signalled on TRX_PIN_IRQ and are also shown in RG_IRQ_STATUS
[IC]	1	All by [IC] enabled IRQs are signalled on TRX_PIN_IRQ and all IRQ causes are shown in RG_IRQ_STATUS

Note:

• The registers RG_IRQ_MASK and SR_IRQ_MASK_MODE should not be changed in any of the [BUSY] states.
• The register RG_IRQ_MASK and can set in P_ON as described in Power-On Reset.
• The pin TRX_PIN_IRQ can be alternatively used as Frame Buffer Empty Indicator. The functionality of the IRQ pin can be configured using SR_RX_BL_CTRL.
• The current IRQ status can also be monitored with the SPI Command Mode.

Example: Using SR_IRQ_MASK_MODE=1 for address match in Basic Operating Mode

It is assumed, that the radio transceiver is in the state BUSY_RX and the registers have the following values: RG_IRQ_MASK = TRX_IRQ_TRX_END, SR_IRQ_MASK_MODE = 1. At the end of a received frame, the interrupt TRX_IRQ_TRX_END is generated. If the address of the received frame matches the settings in the address registers (see section Extended Configuration of RX_AACK mode), also the bit TRX_IRQ_AMI will be set in the register RG_IRQ_STATUS.

Code example

    /* AT86RF231::[ACTIVE] */
    trx_reg_write(RG_IRQ_MASK, mskirqs);
    trx_bit_write(SR_IRQ_MASK_MODE, mskmode);

IRQ Polarity Configuration

The polarity of the pin TRX_PIN_IRQ is configured with the sub register SR_IRQ_POLARITY. Before doing so, the content of the RG_IRQ_MASK has to be saved, in order to restore it after changing the polarity.

Parameters:

irqpol

Polarity of the IRQ {0} : IRQ is active high {1} : IRQ is active low

Code example

    /* AT86RF231::TRX_OFF */
    irqmsk = trx_reg_read(RG_IRQ_MASK);
    trx_reg_write(RG_IRQ_MASK, 0);
    dummy = trx_reg_read(RG_IRQ_STATUS);
    trx_bit_write(SR_IRQ_POLARITY, irqpol);
    trx_reg_write(RG_IRQ_MASK, irqmsk);

IRQ Handling

If an interrupt event in the radio transceiver occurs, the TRX_PIN_IRQ is raised to active level. While processing this interrupt request, the MCU acknowledges the interrupt by reading the register RG_IRQ_STATUS. The read operation also switches the signal on the TRX_PIN_IRQ back to inactive level and clears the register RG_IRQ_STATUS.

Note:

• Dependent on the actual interrupt latency time of the MCU, more than one flag bits can be set within one interrupt event.
• During the transition from P_ON (not contained in [ACTIVE]) to TRX_OFF the TRX_IRQ_AWAKE_END occurs, as described in Power-On Reset.

Return values:

cause

This return parameter contains a flag value, indicating the interrupt root cause.

Code example

    /* AT86RF231::[ACTIVE] */
    /* TRX_IRQ_[*] occurs here */
    /* MCU::ISR */
    cause = trx_reg_read(RG_IRQ_STATUS);
    proc_irq(cause);

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