| #define ACK_DISABLE (1) |
Constant ACK_DISABLE for sub-register SR_AACK_DIS_ACK
| #define ACK_ENABLE (0) |
Constant ACK_ENABLE for sub-register SR_AACK_DIS_ACK
| #define ACK_TIME_12_SYMBOLS (0) |
Constant ACK_TIME_12_SYMBOLS for sub-register SR_AACK_ACK_TIME
| #define ACK_TIME_2_SYMBOLS (1) |
Constant ACK_TIME_2_SYMBOLS for sub-register SR_AACK_ACK_TIME
| #define AES_CTRL (0x83) |
Security module control, AES mode, SRAM address
| #define AES_CTRL_MIRROR (0x94) |
mirrored version of AES_CTRL, SRAM address
| #define AES_DIR_DECRYPT (0x08) |
AES core operation direction: Decryption (ECB)
| #define AES_DIR_ENCRYPT (0) |
AES core operation direction: Encryption (ECB, CBC)
| #define AES_DONE (0x01) |
AES core operation status: AES core operation status
| #define AES_MODE_CBC (0x20) |
Set CBC mode
| #define AES_MODE_ECB (0x0) |
Set ECB mode
| #define AES_MODE_KEY (0x10) |
Set key mode
| #define AES_OP_DONE (1) |
AES core operation status: AES module finished
| #define AES_OP_NOT_DONE (0) |
AES core operation status: AES module did not finish
| #define AES_REQUEST (0x80) |
Initiate an AES operation
| #define AES_STATE (0x82) |
Signal status of the security module and operation, SRAM address
| #define AES_STATE_KEY (0x84) |
depending on AES mode, it contains either AES key or AES state, SRAM address
| #define ALTRATE_1MBPS (2) |
Constant ALTRATE_1MBPS for sub-register SR_OQPSK_DATA_RATE
| #define ALTRATE_250KBPS (0) |
Constant ALTRATE_250KBPS for sub-register SR_OQPSK_DATA_RATE
| #define ALTRATE_2MBPS (3) |
Constant ALTRATE_2MBPS for sub-register SR_OQPSK_DATA_RATE
| #define ALTRATE_500KBPS (1) |
Constant ALTRATE_500KBPS for sub-register SR_OQPSK_DATA_RATE
| #define ANT_DIV_DISABLE (0) |
Constant ANT_DIV_DISABLE for sub-register SR_ANT_DIV_EN
| #define ANT_DIV_ENABLE (1) |
Constant ANT_DIV_ENABLE for sub-register SR_ANT_DIV_EN
| #define ANT_SEL_ANTENNA_0 (0) |
Constant ANT_SEL_ANTENNA_0 for sub-register SR_ANT_SEL
| #define ANT_SEL_ANTENNA_1 (1) |
Constant ANT_SEL_ANTENNA_1 for sub-register SR_ANT_SEL
| #define BATMON_NOT_VALID (0) |
Constant BATMON_NOT_VALID for sub-register SR_BATMON_OK
| #define BATMON_VALID (1) |
Constant BATMON_VALID for sub-register SR_BATMON_OK
| #define BUSY_RX (1) |
Constant BUSY_RX for sub-register SR_TRX_STATUS
| #define BUSY_RX_AACK (17) |
Constant BUSY_RX_AACK for sub-register SR_TRX_STATUS
| #define BUSY_RX_AACK_NOCLK (30) |
Constant BUSY_RX_AACK_NOCLK for sub-register SR_TRX_STATUS
| #define BUSY_TX (2) |
Constant BUSY_TX for sub-register SR_TRX_STATUS
| #define BUSY_TX_ARET (18) |
Constant BUSY_TX_ARET for sub-register SR_TRX_STATUS
| #define CCA_CH_BUSY (0) |
Constant CCA_CH_BUSY for sub-register SR_CCA_STATUS
| #define CCA_CH_IDLE (1) |
Constant CCA_CH_IDLE for sub-register SR_CCA_STATUS
| #define CCA_COMPLETED (1) |
Constant CCA_COMPLETED for sub-register SR_CCA_DONE
| #define CCA_MODE_0 (0) |
Constant CCA_MODE_0 for sub-register SR_CCA_MODE
| #define CCA_MODE_1 (1) |
Constant CCA_MODE_1 for sub-register SR_CCA_MODE
| #define CCA_MODE_2 (2) |
Constant CCA_MODE_2 for sub-register SR_CCA_MODE
| #define CCA_MODE_3 (3) |
Constant CCA_MODE_3 for sub-register SR_CCA_MODE
| #define CCA_ONGOING (0) |
Constant CCA_ONGOING for sub-register SR_CCA_DONE
| #define CCA_START (1) |
Constant CCA_START for sub-register SR_CCA_REQUEST
| #define CLEAR_PD (0) |
Constant CLEAR_PD for sub-register SR_AACK_SET_PD
| #define CLKM_16MHZ (5) |
Constant CLKM_16MHZ for sub-register SR_CLKM_CTRL
| #define CLKM_1_16MHZ (7) |
Constant CLKM_1_16MHZ for sub-register SR_CLKM_CTRL
| #define CLKM_1_4MHZ (6) |
Constant CLKM_1_4MHZ for sub-register SR_CLKM_CTRL
| #define CLKM_1MHZ (1) |
Constant CLKM_1MHZ for sub-register SR_CLKM_CTRL
| #define CLKM_2MHZ (2) |
Constant CLKM_2MHZ for sub-register SR_CLKM_CTRL
| #define CLKM_4MHZ (3) |
Constant CLKM_4MHZ for sub-register SR_CLKM_CTRL
| #define CLKM_8MHZ (4) |
Constant CLKM_8MHZ for sub-register SR_CLKM_CTRL
| #define CLKM_NO_CLOCK (0) |
Constant CLKM_NO_CLOCK for sub-register SR_CLKM_CTRL
| #define CLKM_SHA_DISABLE (0) |
Constant CLKM_SHA_DISABLE for sub-register SR_CLKM_SHA_SEL
| #define CLKM_SHA_ENABLE (1) |
Constant CLKM_SHA_ENABLE for sub-register SR_CLKM_SHA_SEL
| #define CMD_FORCE_PLL_ON (4) |
Constant CMD_FORCE_PLL_ON for sub-register SR_TRX_CMD
| #define CMD_FORCE_TRX_OFF (3) |
Constant CMD_FORCE_TRX_OFF for sub-register SR_TRX_CMD
| #define CMD_NOP (0) |
Constant CMD_NOP for sub-register SR_TRX_CMD
| #define CMD_PLL_ON (9) |
Constant CMD_PLL_ON for sub-register SR_TRX_CMD
| #define CMD_RX_AACK_ON (22) |
Constant CMD_RX_AACK_ON for sub-register SR_TRX_CMD
| #define CMD_RX_ON (6) |
Constant CMD_RX_ON for sub-register SR_TRX_CMD
| #define CMD_TRX_OFF (8) |
Constant CMD_TRX_OFF for sub-register SR_TRX_CMD
| #define CMD_TX_ARET_ON (25) |
Constant CMD_TX_ARET_ON for sub-register SR_TRX_CMD
| #define CMD_TX_START (2) |
Constant CMD_TX_START for sub-register SR_TRX_CMD
| #define CRC16_NOT_VALID (0) |
Constant CRC16_NOT_VALID for sub-register SR_RX_CRC_VALID
| #define CRC16_VALID (1) |
Constant CRC16_VALID for sub-register SR_RX_CRC_VALID
| #define EXT_SWITCH_DISABLE (0) |
Constant EXT_SWITCH_DISABLE for sub-register SR_ANT_EXT_SW_EN
| #define EXT_SWITCH_ENABLE (1) |
Constant EXT_SWITCH_ENABLE for sub-register SR_ANT_EXT_SW_EN
| #define FRAME_VERSION_00 (0) |
Constant FRAME_VERSION_00 for sub-register SR_AACK_FVN_MODE
| #define FRAME_VERSION_01 (1) |
Constant FRAME_VERSION_01 for sub-register SR_AACK_FVN_MODE
| #define FRAME_VERSION_012 (2) |
Constant FRAME_VERSION_012 for sub-register SR_AACK_FVN_MODE
| #define FRAME_VERSION_IGNORED (3) |
Constant FRAME_VERSION_IGNORED for sub-register SR_AACK_FVN_MODE
| #define IRQ_HIGH_ACTIVE (0) |
Constant IRQ_HIGH_ACTIVE for sub-register SR_IRQ_POLARITY
| #define IRQ_LOW_ACTIVE (1) |
Constant IRQ_LOW_ACTIVE for sub-register SR_IRQ_POLARITY
| #define IRQ_MASK_MODE_OFF (0) |
Constant IRQ_MASK_MODE_OFF for sub-register SR_IRQ_MASK_MODE
| #define IRQ_MASK_MODE_ON (1) |
Constant IRQ_MASK_MODE_ON for sub-register SR_IRQ_MASK_MODE
| #define P_ON (0) |
Constant P_ON for sub-register SR_TRX_STATUS
| #define PA_BUF_LT_0_US (0) |
Constant PA_BUF_LT_0_US for sub-register SR_PA_BUF_LT
| #define PA_BUF_LT_2_US (1) |
Constant PA_BUF_LT_2_US for sub-register SR_PA_BUF_LT
| #define PA_BUF_LT_4_US (2) |
Constant PA_BUF_LT_4_US for sub-register SR_PA_BUF_LT
| #define PA_BUF_LT_6_US (3) |
Constant PA_BUF_LT_6_US for sub-register SR_PA_BUF_LT
| #define PA_LT_2_US (0) |
Constant PA_LT_2_US for sub-register SR_PA_LT
| #define PA_LT_4_US (1) |
Constant PA_LT_4_US for sub-register SR_PA_LT
| #define PA_LT_6_US (2) |
Constant PA_LT_6_US for sub-register SR_PA_LT
| #define PA_LT_8_US (3) |
Constant PA_LT_8_US for sub-register SR_PA_LT
| #define PAD_CLKM_2MA (0) |
Constant PAD_CLKM_2MA for sub-register SR_PAD_IO_CLKM
| #define PAD_CLKM_4MA (1) |
Constant PAD_CLKM_4MA for sub-register SR_PAD_IO_CLKM
| #define PAD_CLKM_6MA (2) |
Constant PAD_CLKM_6MA for sub-register SR_PAD_IO_CLKM
| #define PAD_CLKM_8MA (3) |
Constant PAD_CLKM_8MA for sub-register SR_PAD_IO_CLKM
| #define PAD_IO_2MA (0) |
Constant PAD_IO_2MA for sub-register SR_PAD_IO
| #define PAD_IO_4MA (1) |
Constant PAD_IO_4MA for sub-register SR_PAD_IO
| #define PAD_IO_6MA (2) |
Constant PAD_IO_6MA for sub-register SR_PAD_IO
| #define PAD_IO_8MA (3) |
Constant PAD_IO_8MA for sub-register SR_PAD_IO
| #define PART_NUM_AT86RF231 (3) |
Constant PART_NUM_AT86RF231 for sub-register SR_PART_NUM
| #define PLL_ON (9) |
Constant PLL_ON for sub-register SR_TRX_STATUS
| #define PROM_MODE_DISABLE (0) |
Constant PROM_MODE_DISABLE for sub-register SR_AACK_PROM_MODE
| #define PROM_MODE_ENABLE (1) |
Constant PROM_MODE_ENABLE for sub-register SR_AACK_PROM_MODE
| #define RF231_RAM_SIZE (0x80) |
RF231 FIFO size.
| #define RSSI_BASE_VAL (-90) |
Minimum RSSI sensitivity value in dBm, which is equivalent to the value 0 in sub register SR_RSSI.
| #define RX_AACK_ON (22) |
Constant RX_AACK_ON for sub-register SR_TRX_STATUS
| #define RX_AACK_ON_NOCLK (29) |
Constant RX_AACK_ON_NOCLK for sub-register SR_TRX_STATUS
| #define RX_DISABLE (1) |
Constant RX_DISABLE for sub-register SR_RX_PDT_DIS
| #define RX_ENABLE (0) |
Constant RX_ENABLE for sub-register SR_RX_PDT_DIS
| #define RX_ON (6) |
Constant RX_ON for sub-register SR_TRX_STATUS
| #define RX_ON_NOCLK (28) |
Constant RX_ON_NOCLK for sub-register SR_TRX_STATUS
| #define RX_SAFE_MODE_DISABLE (0) |
Constant RX_SAFE_MODE_DISABLE for sub-register SR_RX_SAFE_MODE
| #define RX_SAFE_MODE_ENABLE (1) |
Constant RX_SAFE_MODE_ENABLE for sub-register SR_RX_SAFE_MODE
| #define SET_PD (1) |
Constant SET_PD for sub-register SR_AACK_SET_PD
| #define SLEEP (15) |
Constant SLEEP for sub-register SR_TRX_STATUS
| #define SPI_CMD_MODE_DEFAULT (0) |
Constant SPI_CMD_MODE_DEFAULT for sub-register SR_SPI_CMD_MODE
| #define SPI_CMD_MODE_IRQ_STATUS (3) |
Constant SPI_CMD_MODE_IRQ_STATUS for sub-register SR_SPI_CMD_MODE
| #define SPI_CMD_MODE_PHY_RSSI (2) |
Constant SPI_CMD_MODE_PHY_RSSI for sub-register SR_SPI_CMD_MODE
| #define SPI_CMD_MODE_TRX_STATUS (1) |
Constant SPI_CMD_MODE_TRX_STATUS for sub-register SR_SPI_CMD_MODE
| #define STATE_TRANSITION_IN_PROGRESS (31) |
Constant STATE_TRANSITION_IN_PROGRESS for sub-register SR_TRX_STATUS
| #define T_OCT 32 |
Duration of an octet for 250kb/s O-QPSK mode in us
| #define T_SYM 16 |
Duration of an symbol for 250kb/s O-QPSK mode in us
| #define THRES_ANT_DIV_DISABLED (7) |
Constant THRES_ANT_DIV_DISABLED for sub-register SR_PDT_THRES
| #define THRES_ANT_DIV_ENABLED (3) |
Constant THRES_ANT_DIV_ENABLED for sub-register SR_PDT_THRES
| #define TIMESTAMPING_DISABLE (0) |
Constant TIMESTAMPING_DISABLE for sub-register SR_IRQ_2_EXT_EN
| #define TIMESTAMPING_ENABLE (1) |
Constant TIMESTAMPING_ENABLE for sub-register SR_IRQ_2_EXT_EN
| #define TRAC_CHANNEL_ACCESS_FAILURE (3) |
Constant TRAC_CHANNEL_ACCESS_FAILURE for sub-register SR_TRAC_STATUS
| #define TRAC_INVALID (7) |
Constant TRAC_INVALID for sub-register SR_TRAC_STATUS
| #define TRAC_NO_ACK (5) |
Constant TRAC_NO_ACK for sub-register SR_TRAC_STATUS
| #define TRAC_SUCCESS (0) |
Constant TRAC_SUCCESS for sub-register SR_TRAC_STATUS
| #define TRAC_SUCCESS_DATA_PENDING (1) |
Constant TRAC_SUCCESS_DATA_PENDING for sub-register SR_TRAC_STATUS
| #define TRAC_SUCCESS_WAIT_FOR_ACK (2) |
Constant TRAC_SUCCESS_WAIT_FOR_ACK for sub-register SR_TRAC_STATUS
| #define TRX_AES_BLOCK_SIZE (16) |
Data block size in bytes.
| #define TRX_IRQ_AMI (0x20) |
Signals an address match.
| #define TRX_IRQ_AWAKE_END (TRX_IRQ_CCA_ED_DONE) |
Multi-functional interrupt (AWAKE_END and CCA_ED_DONE):
| #define TRX_IRQ_BAT_LOW (0x80) |
signals low battery
| #define TRX_IRQ_CCA_ED_DONE (0x10) |
Multi-functional interrupt (AWAKE_END and CCA_ED_DONE):
| #define TRX_IRQ_PLL_LOCK (0x01) |
PLL goes to lock-state.
| #define TRX_IRQ_PLL_UNLOCK (0x02) |
signals an unlocked PLL
| #define TRX_IRQ_RX_START (0x04) |
signals begin of a receiving frame
| #define TRX_IRQ_TRX_END (0x08) |
signals end of frames (transmit and receive)
| #define TRX_IRQ_TRX_UR (0x40) |
signals a FIFO underrun
| #define TRX_OFF (8) |
Constant TRX_OFF for sub-register SR_TRX_STATUS
| #define TX_ARET_ON (25) |
Constant TX_ARET_ON for sub-register SR_TRX_STATUS
| #define TX_AUTO_CRC_DISABLE (0) |
Constant TX_AUTO_CRC_DISABLE for sub-register SR_TX_AUTO_CRC_ON
| #define TX_AUTO_CRC_ENABLE (1) |
Constant TX_AUTO_CRC_ENABLE for sub-register SR_TX_AUTO_CRC_ON
| #define UPLD_RES_FT_DISABLE (0) |
Constant UPLD_RES_FT_DISABLE for sub-register SR_AACK_UPLD_RES_FT
| #define UPLD_RES_FT_ENABLE (1) |
Constant UPLD_RES_FT_ENABLE for sub-register SR_AACK_UPLD_RES_FT
| #define VERSION_NUM_AT86RF231 (2) |
Constant VERSION_NUM_AT86RF231 for sub-register SR_VERSION_NUM
| enum aes_access_t |
1.5.2