EBI Register Definitions
[Internal Register Definitions]
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Register offsets | |
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| #define | EBI_CTRL 0x00 |
| Control register. | |
| #define | EBI_SDRAMCTRLA 0x01 |
| SDRAM control register A. | |
| #define | EBI_SDRAMCTRLB 0x08 |
| SDRAM control register B. | |
| #define | EBI_SDRAMCTRLC 0x09 |
| SDRAM control register C. | |
| #define | EBI_REFRESHL 0x04 |
| SDRAM refresh period low byte. | |
| #define | EBI_REFRESHH 0x05 |
| SDRAM refresh period high byte. | |
| #define | EBI_INITDLYL 0x06 |
| SDRAM init. delay low byte. | |
| #define | EBI_INITDLYH 0x07 |
| SDRAM init. delay high byte. | |
Bitfields in CTRL | |
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| #define | EBI_IFMODE_START 0 |
| EBI mode. | |
| #define | EBI_IFMODE_SIZE 2 |
| EBI mode. | |
| #define | EBI_SRMODE_START 2 |
| SRAM mode. | |
| #define | EBI_SRMODE_SIZE 2 |
| SRAM mode. | |
| #define | EBI_LPCMODE_START 4 |
| SRAM Low Pin-Count mode. | |
| #define | EBI_LPCMODE_SIZE 2 |
| SRAM Low Pin-Count mode. | |
| #define | EBI_SDDATAW_START 6 |
| SDRAM data width setting. | |
| #define | EBI_SDDATAW_SIZE 2 |
| SDRAM data width setting. | |
IFMODE bitfield values | |
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| #define | EBI_IFMODE_DISABLED 0 |
| EBI disabled. | |
| #define | EBI_IFMODE_3PORT 1 |
| EBI enabled w/ 3-port interface. | |
| #define | EBI_IFMODE_4PORT 2 |
| EBI enabled w/ 4-port interface. | |
| #define | EBI_IFMODE_2PORT 3 |
| EBI enabled w/ 2-port interface. | |
SRMODE bitfield values | |
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| #define | EBI_SRMODE_ALE1 0 |
| Address bytes 0 and 1 multiplexed. | |
| #define | EBI_SRMODE_ALE2 1 |
| Address bytes 0 and 2 multiplexed. | |
| #define | EBI_SRMODE_ALE12 2 |
| Address bytes 0, 1 and 2 multiplexed. | |
| #define | EBI_SRMODE_NOALE 3 |
| No address multiplexing. | |
LPCMODE bitfield values | |
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| #define | EBI_LPCMODE_ALE1 0 |
| Data multiplexed with address byte 0. | |
| #define | EBI_LPCMODE_ALE12 2 |
| Data multiplexed with address bytes 0 and 1. | |
SDDATAW bitfield values | |
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| #define | EBI_SDDATAW_4BIT 0 |
| 4-bit data bus | |
| #define | EBI_SDDATAW_8BIT 1 |
| 8-bit data bus | |
Bitfields in SDRAMCTRLA | |
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| #define | EBI_SDCOL_START 0 |
| SDRAM column bits. | |
| #define | EBI_SDCOL_SIZE 2 |
| SDRAM column bits. | |
| #define | EBI_SDROW_BIT 2 |
| SDRAM row bits (11/12 bits). | |
| #define | EBI_SDCAS_BIT 3 |
| SDRAM CAS latency (2/3 cycles). | |
SDCOL bitfield values | |
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| #define | EBI_SDCOL_8BIT 0 |
| 8 column bits | |
| #define | EBI_SDCOL_9BIT 1 |
| 9 column bits | |
| #define | EBI_SDCOL_10BIT 2 |
| 10 column bits | |
| #define | EBI_SDCOL_11BIT 3 |
| 11 column bits | |
Bitfields in SDRAMCTRLB | |
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| #define | EBI_RPDLY_START 0 |
| SDRAM row to precharge delay in number of CLKper2 cycles (0-7). | |
| #define | EBI_RPDLY_SIZE 3 |
| SDRAM row to precharge delay in number of CLKper2 cycles (0-7). | |
| #define | EBI_ROWCYCDLY_START 3 |
| SDRAM row cycle delay in number of CLKper2 cycles (0-7). | |
| #define | EBI_ROWCYCDLY_SIZE 3 |
| SDRAM row cycle delay in number of CLKper2 cycles (0-7). | |
| #define | EBI_MRDLY_START 6 |
| SDRAM mode register delay in number of CLKper2 cycles (0-3). | |
| #define | EBI_MRDLY_SIZE 2 |
| SDRAM mode register delay in number of CLKper2 cycles (0-3). | |
Bitfields in SDRAMCTRLC | |
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| #define | EBI_ROWCOLDLY_START 0 |
| SDRAM row to column delay in number of CLKper2 cycles (0-7). | |
| #define | EBI_ROWCOLDLY_SIZE 3 |
| SDRAM row to column delay in number of CLKper2 cycles (0-7). | |
| #define | EBI_ESRDLY_START 3 |
| SDRAM exit self refresh to active delay in number of CLKper2 cycles (0-7). | |
| #define | EBI_ESRDLY_SIZE 3 |
| SDRAM exit self refresh to active delay in number of CLKper2 cycles (0-7). | |
| #define | EBI_WRDLY_START 6 |
| SDRAM write recovery delay in number of CLKper2 cycles (0-3). | |
| #define | EBI_WRDLY_SIZE 2 |
| SDRAM write recovery delay in number of CLKper2 cycles (0-3). | |
Bitfields in REFRESH | |
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| #define | EBI_REFRESH_START 0 |
| SDRAM refresh period in number of CLKper2 cycles. | |
| #define | EBI_REFRESH_SIZE 10 |
| SDRAM refresh period in number of CLKper2 cycles. | |
Bitfields in REFRESHL | |
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| #define | EBI_REFRESHL_START 0 |
| SDRAM refresh period in number of CLKper2 cycles (LSB). | |
| #define | EBI_REFRESHL_SIZE 8 |
| SDRAM refresh period in number of CLKper2 cycles (LSB). | |
Bitfields in REFRESHH | |
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| #define | EBI_REFRESHH_START 0 |
| SDRAM refresh period in number of CLKper2 cycles (MSB). | |
| #define | EBI_REFRESHH_SIZE 2 |
| SDRAM refresh period in number of CLKper2 cycles (MSB). | |
Bitfields in INITDLY | |
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| #define | EBI_INITDLY_START 0 |
| SDRAM initialization delay in number of CLKper2 cycles. | |
| #define | EBI_INITDLY_SIZE 14 |
| SDRAM initialization delay in number of CLKper2 cycles. | |
Bitfields in INITDLYL | |
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| #define | EBI_INITDLYL_START 0 |
| SDRAM initialization delay in number of CLKper2 cycles (LSB). | |
| #define | EBI_INITDLYL_SIZE 8 |
| SDRAM initialization delay in number of CLKper2 cycles (LSB). | |
Bitfields in INITDLYH | |
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| #define | EBI_INITDLYH_START 0 |
| SDRAM initialization delay in number of CLKper2 cycles (MSB). | |
| #define | EBI_INITDLYH_SIZE 6 |
| SDRAM initialization delay in number of CLKper2 cycles (MSB). | |
Bit manipulation macros | |
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| #define | EBI_BIT(name) (1U << EBI_##name##_BIT) |
| Create a mask with bit name set. | |
| #define | EBI_BF(name, value) ((value) << EBI_##name##_START) |
| Create a mask with bitfield name set to value. | |
| #define | EBI_BFMASK(name) (((1U << EBI_##name##_SIZE) - 1) << EBI_##name##_START) |
| Create a mask of the bitfield name. | |
| #define | EBI_BFEXT(name, regval) |
| Extract the value of bitfield name from regval. | |
| #define | EBI_BFINS(name, value, regval) |
| Return regval with bitfield name set to value. | |
Register access macros | |
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| #define | ebi_read_reg(reg) mmio_read8((void *)((uintptr_t)(EBI_BASE) + EBI_##reg)) |
| Read the value of EBI register reg. | |
| #define | ebi_write_reg(reg, value) mmio_write8((void *)((uintptr_t)(EBI_BASE) + EBI_##reg), (value)) |
| Write value to EBI register reg. | |
| #define | ebi_read_word_reg(reg) mmio_read16((void *)((uintptr_t)(EBI_BASE) + EBI_##reg##L)) |
| Read the value of EBI word-register reg. | |
| #define | ebi_write_word_reg(reg, value) mmio_write16((void *)((uintptr_t)(EBI_BASE) + EBI_##reg##L), (value)) |
| Write value to EBI word-register reg. | |
Define Documentation
| #define EBI_BF | ( | name, | |||
| value | ) | ((value) << EBI_##name##_START) |
Create a mask with bitfield name set to value.
Definition at line 209 of file xmega_ebi.h.
| #define EBI_BFEXT | ( | name, | |||
| regval | ) |
(((regval) >> EBI_##name##_START) \
& ((1U << EBI_##name##_SIZE) - 1))
Extract the value of bitfield name from regval.
Definition at line 215 of file xmega_ebi.h.
| #define EBI_BFINS | ( | name, | |||
| value, | |||||
| regval | ) |
(((regval) & ~(((1U << EBI_##name##_SIZE) - 1) \
<< EBI_##name##_START)) \
| EBI_BF(name, value))
Return regval with bitfield name set to value.
Definition at line 219 of file xmega_ebi.h.
| #define EBI_BFMASK | ( | name | ) | (((1U << EBI_##name##_SIZE) - 1) << EBI_##name##_START) |
Create a mask of the bitfield name.
Definition at line 212 of file xmega_ebi.h.
| #define EBI_BIT | ( | name | ) | (1U << EBI_##name##_BIT) |
Create a mask with bit name set.
Definition at line 206 of file xmega_ebi.h.
| #define EBI_CTRL 0x00 |
Control register.
Definition at line 53 of file xmega_ebi.h.
| #define EBI_ESRDLY_SIZE 3 |
SDRAM exit self refresh to active delay in number of CLKper2 cycles (0-7).
Definition at line 148 of file xmega_ebi.h.
| #define EBI_ESRDLY_START 3 |
SDRAM exit self refresh to active delay in number of CLKper2 cycles (0-7).
Definition at line 146 of file xmega_ebi.h.
| #define EBI_IFMODE_2PORT 3 |
EBI enabled w/ 2-port interface.
Definition at line 80 of file xmega_ebi.h.
| #define EBI_IFMODE_3PORT 1 |
EBI enabled w/ 3-port interface.
Definition at line 78 of file xmega_ebi.h.
| #define EBI_IFMODE_4PORT 2 |
EBI enabled w/ 4-port interface.
Definition at line 79 of file xmega_ebi.h.
| #define EBI_IFMODE_DISABLED 0 |
EBI disabled.
Definition at line 77 of file xmega_ebi.h.
| #define EBI_IFMODE_SIZE 2 |
EBI mode.
Definition at line 66 of file xmega_ebi.h.
| #define EBI_IFMODE_START 0 |
EBI mode.
Definition at line 65 of file xmega_ebi.h.
| #define EBI_INITDLY_SIZE 14 |
SDRAM initialization delay in number of CLKper2 cycles.
Definition at line 184 of file xmega_ebi.h.
| #define EBI_INITDLY_START 0 |
SDRAM initialization delay in number of CLKper2 cycles.
Definition at line 182 of file xmega_ebi.h.
| #define EBI_INITDLYH 0x07 |
SDRAM init. delay high byte.
Definition at line 60 of file xmega_ebi.h.
| #define EBI_INITDLYH_SIZE 6 |
SDRAM initialization delay in number of CLKper2 cycles (MSB).
Definition at line 200 of file xmega_ebi.h.
| #define EBI_INITDLYH_START 0 |
SDRAM initialization delay in number of CLKper2 cycles (MSB).
Definition at line 198 of file xmega_ebi.h.
| #define EBI_INITDLYL 0x06 |
SDRAM init. delay low byte.
Definition at line 59 of file xmega_ebi.h.
| #define EBI_INITDLYL_SIZE 8 |
SDRAM initialization delay in number of CLKper2 cycles (LSB).
Definition at line 192 of file xmega_ebi.h.
| #define EBI_INITDLYL_START 0 |
SDRAM initialization delay in number of CLKper2 cycles (LSB).
Definition at line 190 of file xmega_ebi.h.
| #define EBI_LPCMODE_ALE1 0 |
Data multiplexed with address byte 0.
Definition at line 94 of file xmega_ebi.h.
| #define EBI_LPCMODE_ALE12 2 |
Data multiplexed with address bytes 0 and 1.
Definition at line 96 of file xmega_ebi.h.
| #define EBI_LPCMODE_SIZE 2 |
SRAM Low Pin-Count mode.
Definition at line 70 of file xmega_ebi.h.
| #define EBI_LPCMODE_START 4 |
SRAM Low Pin-Count mode.
Definition at line 69 of file xmega_ebi.h.
| #define EBI_MRDLY_SIZE 2 |
SDRAM mode register delay in number of CLKper2 cycles (0-3).
Definition at line 136 of file xmega_ebi.h.
| #define EBI_MRDLY_START 6 |
SDRAM mode register delay in number of CLKper2 cycles (0-3).
Definition at line 134 of file xmega_ebi.h.
| #define ebi_read_reg | ( | reg | ) | mmio_read8((void *)((uintptr_t)(EBI_BASE) + EBI_##reg)) |
Read the value of EBI register reg.
Definition at line 228 of file xmega_ebi.h.
| #define ebi_read_word_reg | ( | reg | ) | mmio_read16((void *)((uintptr_t)(EBI_BASE) + EBI_##reg##L)) |
Read the value of EBI word-register reg.
For use with REFRESH and INITDLY.
Definition at line 238 of file xmega_ebi.h.
| #define EBI_REFRESH_SIZE 10 |
SDRAM refresh period in number of CLKper2 cycles.
Definition at line 160 of file xmega_ebi.h.
| #define EBI_REFRESH_START 0 |
SDRAM refresh period in number of CLKper2 cycles.
Definition at line 158 of file xmega_ebi.h.
| #define EBI_REFRESHH 0x05 |
SDRAM refresh period high byte.
Definition at line 58 of file xmega_ebi.h.
| #define EBI_REFRESHH_SIZE 2 |
SDRAM refresh period in number of CLKper2 cycles (MSB).
Definition at line 176 of file xmega_ebi.h.
| #define EBI_REFRESHH_START 0 |
SDRAM refresh period in number of CLKper2 cycles (MSB).
Definition at line 174 of file xmega_ebi.h.
| #define EBI_REFRESHL 0x04 |
SDRAM refresh period low byte.
Definition at line 57 of file xmega_ebi.h.
| #define EBI_REFRESHL_SIZE 8 |
SDRAM refresh period in number of CLKper2 cycles (LSB).
Definition at line 168 of file xmega_ebi.h.
| #define EBI_REFRESHL_START 0 |
SDRAM refresh period in number of CLKper2 cycles (LSB).
Definition at line 166 of file xmega_ebi.h.
| #define EBI_ROWCOLDLY_SIZE 3 |
SDRAM row to column delay in number of CLKper2 cycles (0-7).
Definition at line 144 of file xmega_ebi.h.
| #define EBI_ROWCOLDLY_START 0 |
SDRAM row to column delay in number of CLKper2 cycles (0-7).
Definition at line 142 of file xmega_ebi.h.
| #define EBI_ROWCYCDLY_SIZE 3 |
SDRAM row cycle delay in number of CLKper2 cycles (0-7).
Definition at line 132 of file xmega_ebi.h.
| #define EBI_ROWCYCDLY_START 3 |
SDRAM row cycle delay in number of CLKper2 cycles (0-7).
Definition at line 130 of file xmega_ebi.h.
| #define EBI_RPDLY_SIZE 3 |
SDRAM row to precharge delay in number of CLKper2 cycles (0-7).
Definition at line 128 of file xmega_ebi.h.
| #define EBI_RPDLY_START 0 |
SDRAM row to precharge delay in number of CLKper2 cycles (0-7).
Definition at line 126 of file xmega_ebi.h.
| #define EBI_SDCAS_BIT 3 |
SDRAM CAS latency (2/3 cycles).
Definition at line 111 of file xmega_ebi.h.
| #define EBI_SDCOL_10BIT 2 |
10 column bits
Definition at line 118 of file xmega_ebi.h.
| #define EBI_SDCOL_11BIT 3 |
11 column bits
Definition at line 119 of file xmega_ebi.h.
| #define EBI_SDCOL_8BIT 0 |
8 column bits
Definition at line 116 of file xmega_ebi.h.
| #define EBI_SDCOL_9BIT 1 |
9 column bits
Definition at line 117 of file xmega_ebi.h.
| #define EBI_SDCOL_SIZE 2 |
SDRAM column bits.
Definition at line 109 of file xmega_ebi.h.
| #define EBI_SDCOL_START 0 |
SDRAM column bits.
Definition at line 108 of file xmega_ebi.h.
| #define EBI_SDDATAW_4BIT 0 |
4-bit data bus
Definition at line 101 of file xmega_ebi.h.
| #define EBI_SDDATAW_8BIT 1 |
8-bit data bus
Definition at line 102 of file xmega_ebi.h.
| #define EBI_SDDATAW_SIZE 2 |
SDRAM data width setting.
Definition at line 72 of file xmega_ebi.h.
| #define EBI_SDDATAW_START 6 |
SDRAM data width setting.
Definition at line 71 of file xmega_ebi.h.
| #define EBI_SDRAMCTRLA 0x01 |
SDRAM control register A.
Definition at line 54 of file xmega_ebi.h.
| #define EBI_SDRAMCTRLB 0x08 |
SDRAM control register B.
Definition at line 55 of file xmega_ebi.h.
| #define EBI_SDRAMCTRLC 0x09 |
SDRAM control register C.
Definition at line 56 of file xmega_ebi.h.
| #define EBI_SDROW_BIT 2 |
SDRAM row bits (11/12 bits).
Definition at line 110 of file xmega_ebi.h.
| #define EBI_SRMODE_ALE1 0 |
Address bytes 0 and 1 multiplexed.
Definition at line 85 of file xmega_ebi.h.
| #define EBI_SRMODE_ALE12 2 |
Address bytes 0, 1 and 2 multiplexed.
Definition at line 87 of file xmega_ebi.h.
| #define EBI_SRMODE_ALE2 1 |
Address bytes 0 and 2 multiplexed.
Definition at line 86 of file xmega_ebi.h.
| #define EBI_SRMODE_NOALE 3 |
No address multiplexing.
Definition at line 88 of file xmega_ebi.h.
| #define EBI_SRMODE_SIZE 2 |
SRAM mode.
Definition at line 68 of file xmega_ebi.h.
| #define EBI_SRMODE_START 2 |
SRAM mode.
Definition at line 67 of file xmega_ebi.h.
| #define EBI_WRDLY_SIZE 2 |
SDRAM write recovery delay in number of CLKper2 cycles (0-3).
Definition at line 152 of file xmega_ebi.h.
| #define EBI_WRDLY_START 6 |
SDRAM write recovery delay in number of CLKper2 cycles (0-3).
Definition at line 150 of file xmega_ebi.h.
| #define ebi_write_reg | ( | reg, | |||
| value | ) | mmio_write8((void *)((uintptr_t)(EBI_BASE) + EBI_##reg), (value)) |
Write value to EBI register reg.
Definition at line 231 of file xmega_ebi.h.
| #define ebi_write_word_reg | ( | reg, | |||
| value | ) | mmio_write16((void *)((uintptr_t)(EBI_BASE) + EBI_##reg##L), (value)) |
Write value to EBI word-register reg.
For use with REFRESH and INITDLY.
Definition at line 245 of file xmega_ebi.h.
