00001
00039 #ifndef REGS_XMEGA_SPI_H_INCLUDED
00040 #define REGS_XMEGA_SPI_H_INCLUDED
00041
00042 #include <io.h>
00043
00050
00051
00052 #define SPI_CTRL 0 //!< Control Register
00053 #define SPI_INTCTRL 1 //!< Interrupt Control Register
00054 #define SPI_STATUS 2 //!< Status Register
00055 #define SPI_DATA 3 //!< Data Register
00056
00057
00058
00060 #define SPI_CTRL_PRESCALER_START 0 //!< Clock Prescaler
00061 #define SPI_CTRL_PRESCALER_SIZE 2 //!< Clock Prescaler
00062 #define SPI_CTRL_MODE_START 2 //!< Mode
00063 #define SPI_CTRL_MODE_SIZE 2 //!< Mode
00064 #define SPI_CTRL_MASTER_BIT 4 //!< Master/Slave Select
00065 #define SPI_CTRL_DORD_BIT 5 //!< Data Order
00066 #define SPI_CTRL_ENABLE_BIT 6 //!< Enable
00067 #define SPI_CTRL_CLK2X_BIT 7 //!< Clock Double
00068
00069
00070
00072 # define SPI_INTCTRL_INTLVL_START 0 //!< Interrupt Level
00073 # define SPI_INTCTRL_INTLVL_SIZE 2 //!< Interrupt Level
00074
00075
00076
00078 # define SPI_STATUS_WRCOL_BIT 6 //!< Write Collision Flag
00079 # define SPI_STATUS_IF_BIT 7 //!< Interrupt Flag
00080
00081
00083
00084
00085 #define SPI_BIT(name) \
00086 (1 << SPI_##name##_BIT)
00087
00088 #define SPI_BF(name,value) \
00089 (((value) & ((1 << SPI_##name##_SIZE) - 1)) \
00090 << SPI_##name##_START)
00091
00092 #define SPI_BFEXT(name,value) \
00093 (((value) >> USART_##name##_START) \
00094 & ((1 << USART_##name##_SIZE) - 1))
00095
00096 #define SPI_BFINS(name,value,old) \
00097 (((old) & ~(((1 << SPI_##name##_SIZE) - 1) \
00098 << SPI_##name##_START)) \
00099 | SPI_BF(name,value))
00100
00101
00103
00104
00105 #define spi_write_reg(spi, reg, value) \
00106 mmio_write8((void *)((uintptr_t)(spi) + SPI_##reg), value)
00107
00108 #define spi_read_reg(spi, reg) \
00109 mmio_read8((void *)((uintptr_t)(spi) + SPI_##reg))
00110
00111
00113 #endif