include/regs/xmega_osc.h

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#ifndef REGS_XMEGA_OSC_H_INCLUDED
#define REGS_XMEGA_OSC_H_INCLUDED

#include <chip/memory-map.h>
#include <io.h>



#define XMEGA_OSC_CTRL          0x00    //!< Oscillator Control
#define XMEGA_OSC_STATUS        0x01    //!< Oscillator Status
#define XMEGA_OSC_XOSCCTRL      0x02    //!< XOSC Control
#define XMEGA_OSC_XOSCFAIL      0x03    //!< XOSC Failure Detection
#define XMEGA_OSC_RC32KCAL      0x04    //!< 32 kHz Oscillator Calibration
#define XMEGA_OSC_PLLCTRL       0x05    //!< PLL Control
#define XMEGA_OSC_DFLLCTRL      0x06    //!< DFLL Control



#define XMEGA_OSC_RC2MEN_BIT      0     //!< 2 MHz RCOSC Enable
#define XMEGA_OSC_RC32MEN_BIT     1     //!< 32 MHz RCOSC Enable
#define XMEGA_OSC_RC32KEN_BIT     2     //!< 32 kHz RCOSC Enable
#define XMEGA_OSC_XOSCEN_BIT      3     //!< External Oscillator Enable
#define XMEGA_OSC_PLLEN_BIT       4     //!< PLL Enable



#define XMEGA_OSC_RC2MRDY_BI      0     //!< 2 MHz RCOSC Enable
#define XMEGA_OSC_RC32MRDY_BIT    1     //!< 32 MHz RCOSC Enable
#define XMEGA_OSC_RC32KRDY_BIT    2     //!< 32 kHz RCOSC Enable
#define XMEGA_OSC_XOSCRDY_BIT     3     //!< External Oscillator Enable
#define XMEGA_OSC_PLLRDY_BIT      4     //!< PLL Enable



#define XMEGA_OSC_XOSCSEL_START   0     //!< Crystal Oscillator Type
#define XMEGA_OSC_XOSCSEL_SIZE    4     //!< Crystal Oscillator Type
#define XMEGA_OSC_X32KLPM_BIT     5     //!< XTAL 32 kHz Low Power Mode
#define XMEGA_OSC_FRQRANGE_START  6     //!< XTAL Frequency Range
#define XMEGA_OSC_FRQRANGE_SIZE   2     //!< XTAL Frequency Range



#define XMEGA_OSC_XOSCFDEN_BIT    0     //!< Failure Detection Enable
#define XMEGA_OSC_XOSCFDIF_BIT    1     //!< Failure Detection Interrupt Flag



#define XMEGA_OSC_PLLFAC_START    0     //!< Multiplication Factor
#define XMEGA_OSC_PLLFAC_SIZE     5     //!< Multiplication Factor
#define XMEGA_OSC_PLLSRC_START    6     //!< Clock Source
#define XMEGA_OSC_PLLSRC_SIZE     2     //!< Clock Source




#define OSC_BIT(name)           (1U << XMEGA_OSC_##name##_BIT)

#define OSC_BF(name, value)                                             \
        ((value) << XMEGA_OSC_##name##_START)

#define OSC_BFMASK(name)                                                \
        (((1U << XMEGA_OSC_##name##_SIZE) - 1)                          \
                << XMEGA_OSC_##name##_START)

#define OSC_BFEXT(name, regval)                                         \
        (((regval) >> XMEGA_OSC_##name##_START)                         \
                & ((1U << XMEGA_OSC_##name##_SIZE) - 1))

#define OSC_BFINS(name, value, regval)                                  \
        (((regval) & ~(((1U << XMEGA_OSC_##name##_SIZE) - 1)            \
                        << XMEGA_OSC_##name##_START))                   \
                | XMEGA_OSC_BF(name, value))




#define osc_read_reg(reg)                                       \
        _osc_read_reg(reg)
#define _osc_read_reg(reg)                                      \
        mmio_read8((void *)(OSC_BASE + XMEGA_OSC_##reg))

#define osc_write_reg(reg, value)                               \
        _osc_write_reg(reg, value)
#define _osc_write_reg(reg, value)                              \
        mmio_write8((void *)(OSC_BASE + XMEGA_OSC_##reg), (value))

#define osc_write_ccp_reg(reg, value)                           \
        _osc_write_ccp_reg(reg, value)
#define _osc_write_ccp_reg(reg, value)                          \
        mmio_ccp_write8((void *)(OSC_BASE + XMEGA_OSC_##reg), (value))



#endif /* REGS_XMEGA_OSC_H_INCLUDED */

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