include/regs/xmega_ebi.h

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#ifndef REGS_XMEGA_EBI_H_INCLUDED
#define REGS_XMEGA_EBI_H_INCLUDED

#include <chip/memory-map.h>
#include <io.h>



#define EBI_CTRL                0x00  //!< Control register
#define EBI_SDRAMCTRLA          0x01  //!< SDRAM control register A
#define EBI_SDRAMCTRLB          0x08  //!< SDRAM control register B
#define EBI_SDRAMCTRLC          0x09  //!< SDRAM control register C
#define EBI_REFRESHL            0x04  //!< SDRAM refresh period low byte
#define EBI_REFRESHH            0x05  //!< SDRAM refresh period high byte
#define EBI_INITDLYL            0x06  //!< SDRAM init. delay low byte
#define EBI_INITDLYH            0x07  //!< SDRAM init. delay high byte



#define EBI_IFMODE_START        0  //!< EBI mode
#define EBI_IFMODE_SIZE         2  //!< EBI mode
#define EBI_SRMODE_START        2  //!< SRAM mode
#define EBI_SRMODE_SIZE         2  //!< SRAM mode
#define EBI_LPCMODE_START       4  //!< SRAM Low Pin-Count mode
#define EBI_LPCMODE_SIZE        2  //!< SRAM Low Pin-Count mode
#define EBI_SDDATAW_START       6  //!< SDRAM data width setting
#define EBI_SDDATAW_SIZE        2  //!< SDRAM data width setting



#define EBI_IFMODE_DISABLED     0  //!< EBI disabled
#define EBI_IFMODE_3PORT        1  //!< EBI enabled w/ 3-port interface
#define EBI_IFMODE_4PORT        2  //!< EBI enabled w/ 4-port interface
#define EBI_IFMODE_2PORT        3  //!< EBI enabled w/ 2-port interface



#define EBI_SRMODE_ALE1         0  //!< Address bytes 0 and 1 multiplexed
#define EBI_SRMODE_ALE2         1  //!< Address bytes 0 and 2 multiplexed
#define EBI_SRMODE_ALE12        2  //!< Address bytes 0, 1 and 2 multiplexed
#define EBI_SRMODE_NOALE        3  //!< No address multiplexing




#define EBI_LPCMODE_ALE1        0

#define EBI_LPCMODE_ALE12       2



#define EBI_SDDATAW_4BIT        0  //!< 4-bit data bus
#define EBI_SDDATAW_8BIT        1  //!< 8-bit data bus




#define EBI_SDCOL_START         0  //!< SDRAM column bits
#define EBI_SDCOL_SIZE          2  //!< SDRAM column bits
#define EBI_SDROW_BIT           2  //!< SDRAM row bits (11/12 bits)
#define EBI_SDCAS_BIT           3  //!< SDRAM CAS latency (2/3 cycles)



#define EBI_SDCOL_8BIT          0  //!< 8 column bits
#define EBI_SDCOL_9BIT          1  //!< 9 column bits
#define EBI_SDCOL_10BIT         2  //!< 10 column bits
#define EBI_SDCOL_11BIT         3  //!< 11 column bits





#define EBI_RPDLY_START         0

#define EBI_RPDLY_SIZE          3

#define EBI_ROWCYCDLY_START     3

#define EBI_ROWCYCDLY_SIZE      3

#define EBI_MRDLY_START         6

#define EBI_MRDLY_SIZE          2




#define EBI_ROWCOLDLY_START     0

#define EBI_ROWCOLDLY_SIZE      3

#define EBI_ESRDLY_START        3

#define EBI_ESRDLY_SIZE         3

#define EBI_WRDLY_START         6

#define EBI_WRDLY_SIZE          2




#define EBI_REFRESH_START      0

#define EBI_REFRESH_SIZE       10




#define EBI_REFRESHL_START      0

#define EBI_REFRESHL_SIZE       8




#define EBI_REFRESHH_START      0

#define EBI_REFRESHH_SIZE       2




#define EBI_INITDLY_START        0

#define EBI_INITDLY_SIZE         14




#define EBI_INITDLYL_START       0

#define EBI_INITDLYL_SIZE        8




#define EBI_INITDLYH_START       0

#define EBI_INITDLYH_SIZE        6




#define EBI_BIT(name) \
        (1U << EBI_##name##_BIT)

#define EBI_BF(name, value) \
        ((value) << EBI_##name##_START)

#define EBI_BFMASK(name) \
        (((1U << EBI_##name##_SIZE) - 1) << EBI_##name##_START)

#define EBI_BFEXT(name, regval) \
        (((regval) >> EBI_##name##_START) \
                & ((1U << EBI_##name##_SIZE) - 1))

#define EBI_BFINS(name, value, regval) \
        (((regval) & ~(((1U << EBI_##name##_SIZE) - 1) \
                        << EBI_##name##_START)) \
        | EBI_BF(name, value))




#define ebi_read_reg(reg) \
        mmio_read8((void *)((uintptr_t)(EBI_BASE) + EBI_##reg))

#define ebi_write_reg(reg, value) \
        mmio_write8((void *)((uintptr_t)(EBI_BASE) + EBI_##reg), (value))

#define ebi_read_word_reg(reg) \
        mmio_read16((void *)((uintptr_t)(EBI_BASE) + EBI_##reg##L))

#define ebi_write_word_reg(reg, value) \
        mmio_write16((void *)((uintptr_t)(EBI_BASE) + EBI_##reg##L), (value))





//{@
#define EBICS_CS0             0x10  //!< EBI Chip Select 0
#define EBICS_CS1             0x14  //!< EBI Chip Select 1
#define EBICS_CS2             0x18  //!< EBI Chip Select 2
#define EBICS_CS3             0x1c  //!< EBI Chip Select 3



#define EBICS_CTRLA           0x00  //!< Control register A
#define EBICS_CTRLB           0x01  //!< Control register B
#define EBICS_BASEADDRL       0x02  //!< Base address low byte
#define EBICS_BASEADDRH       0x03  //!< Base address high byte





#define EBICS_MODE_START      0

#define EBICS_MODE_SIZE       2

#define EBICS_ASIZE_START     2

#define EBICS_ASIZE_SIZE      5



#define EBICS_MODE_DISABLE    0  //!< CS disabled
#define EBICS_MODE_SRAM       1  //!< CS enabled for SRAM
#define EBICS_MODE_LPC        2  //!< CS enabled for low pin-count SRAM
#define EBICS_MODE_SDRAM      3  //!< CS enabled for SDRAM




#define EBICS_SRWS_START      0

#define EBICS_SRWS_SIZE       3



#define EBICS_SDMODE_START    0  //!< SDRAM mode
#define EBICS_SDMODE_SIZE     2  //!< SDRAM mode
#define EBICS_SDSREN_BIT      2  //!< SDRAM self-refresh enable
#define EBICS_SDINITDONE_BIT  7  //!< SDRAM initialization done



#define EBICS_SDMODE_NORMAL   0  //!< Normal mode
#define EBICS_SDMODE_LOAD     1  //!< Load mode




#define EBICS_BASEADDR_START  4

#define EBICS_BASEADDR_SIZE   12




#define EBICS_BASEADDRL_START  4

#define EBICS_BASEADDRL_SIZE   4




#define EBICS_BASEADDRH_START  0

#define EBICS_BASEADDRH_SIZE   8




#define EBICS_BIT(name) \
        (1U << EBICS_##name##_BIT)

#define EBICS_BF(name, value) \
        ((value) << EBICS_##name##_START)

#define EBICS_BFMASK(name) \
        (((1U << EBICS_##name##_SIZE) - 1) << EBICS_##name##_START)

#define EBICS_BFEXT(name, regval) \
        (((regval) >> EBICS_##name##_START) \
                & ((1U << EBICS_##name##_SIZE) - 1))

#define EBICS_BFINS(name, value, regval) \
        (((regval) & ~(((1U << EBICS_##name##_SIZE) - 1) \
                        << EBICS_##name##_START)) \
        | EBICS_BF(name, value))




#define ebics_read_reg(cs, reg) \
        mmio_read8((void *)((uintptr_t)(EBI_BASE) + EBICS_##cs + EBICS_##reg))

#define ebics_write_reg(cs, reg, value) \
        mmio_write8((void *)((uintptr_t)(EBI_BASE) + EBICS_##cs \
                        + EBICS_##reg), (value))

#define ebics_read_word_reg(cs, reg) \
        mmio_read16((void *)((uintptr_t)(EBI_BASE) + EBICS_##cs \
                        + EBICS_##reg##L))

#define ebics_write_word_reg(cs, reg, value) \
        mmio_write16((void *)((uintptr_t)(EBI_BASE) + EBICS_##cs \
                        + EBICS_##reg##L), (value))



#endif /* REGS_XMEGA_EBI_H_INCLUDED */

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