include/regs/xmega_clk.h

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#ifndef REGS_XMEGA_CLK_H_INCLUDED
#define REGS_XMEGA_CLK_H_INCLUDED

#include <chip/memory-map.h>
#include <io.h>



#define XMEGA_CLK_CTRL          0x00    //!< System Clock Control
#define XMEGA_CLK_PSCTRL        0x01    //!< System Clock Prescaler
#define XMEGA_CLK_LOCK          0x02    //!< Clock System Lock
#define XMEGA_CLK_RTCCTRL       0x03    //!< RTC Control



#define XMEGA_CLK_SCLKSEL_START 0       //< System Clock Selection
#define XMEGA_CLK_SCLKSEL_SIZE  3       //< System Clock Selection



#define XMEGA_CLK_PSBCDIV_START 0       //!< Prescaler B/C Division Factor
#define XMEGA_CLK_PSBCDIV_SIZE  2       //!< Prescaler B/C Division Factor
#define XMEGA_CLK_PSADIV_START  0       //!< Prescaler A Division Factor
#define XMEGA_CLK_PSADIV_SIZE   0       //!< Prescaler A Division Factor



#define XMEGA_CLK_LOCK_BIT      0       //!< Clock System Lock



#define XMEGA_CLK_RTCEN_BIT     0       //!< RTC Clock Source Enable
#define XMEGA_CLK_RTCSRC_START  1       //!< RTC Clock Source
#define XMEGA_CLK_RTCSRC_SIZE   3       //!< RTC Clock Source



#define XMEGA_CLK_PSADIV_1      0       //!< No division
#define XMEGA_CLK_PSADIV_2      1       //!< Divide by 2
#define XMEGA_CLK_PSADIV_4      3       //!< Divide by 2
#define XMEGA_CLK_PSADIV_8      5       //!< Divide by 2
#define XMEGA_CLK_PSADIV_16     7       //!< Divide by 2
#define XMEGA_CLK_PSADIV_32     9       //!< Divide by 2
#define XMEGA_CLK_PSADIV_64     11      //!< Divide by 2
#define XMEGA_CLK_PSADIV_128    13      //!< Divide by 2
#define XMEGA_CLK_PSADIV_256    15      //!< Divide by 2
#define XMEGA_CLK_PSADIV_512    17      //!< Divide by 2



#define XMEGA_CLK_PSBCDIV_1_1   0       //!< No division / No division
#define XMEGA_CLK_PSBCDIV_1_2   1       //!< No division / Divide by 2
#define XMEGA_CLK_PSBCDIV_4_1   2       //!< Divide by 4 / No division
#define XMEGA_CLK_PSBCDIV_2_2   3       //!< Divide by 2 / Divide by 2




#define CLK_BIT(name)           (1U << XMEGA_CLK_##name##_BIT)

#define CLK_BF(name, value)                                             \
        ((value) << XMEGA_CLK_##name##_START)

#define CLK_BFMASK(name)                                                \
        (((1U << XMEGA_CLK_##name##_SIZE) - 1)                          \
                << XMEGA_CLK_##name##_START)

#define CLK_BFEXT(name, regval)                                         \
        (((regval) >> XMEGA_CLK_##name##_START)                         \
                & ((1U << XMEGA_CLK_##name##_SIZE) - 1))

#define CLK_BFINS(name, value, regval)                                  \
        (((regval) & ~(((1U << XMEGA_CLK_##name##_SIZE) - 1)            \
                        << XMEGA_CLK_##name##_START))                   \
                | XMEGA_CLK_BF(name, value))




#define clk_read_reg(reg)                                       \
        _clk_read_reg(reg)
#define _clk_read_reg(reg)                                      \
        mmio_read8((void *)(CLK_BASE + XMEGA_CLK_##reg))

#define clk_write_reg(reg, value)                               \
        _clk_write_reg(reg, value)
#define _clk_write_reg(reg, value)                              \
        mmio_write8((void *)(CLK_BASE + XMEGA_CLK_##reg), (value))

#define clk_write_ccp_reg(reg, value)                           \
        _clk_write_ccp_reg(reg, value)
#define _clk_write_ccp_reg(reg, value)                          \
        mmio_ccp_write8((void *)(CLK_BASE + XMEGA_CLK_##reg), (value))



#endif /* REGS_XMEGA_CLK_H_INCLUDED */

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