00001 00039 #ifndef CHIP_TC_H_INCLUDED 00040 #define CHIP_TC_H_INCLUDED 00041 00042 #include <assert.h> 00043 #include <stdbool.h> 00044 #include <stdint.h> 00045 #include <clk/sys.h> 00046 #include <regs/xmega_tc.h> 00047 00057 static inline uint8_t tc_get_sysclk_port(uint8_t tc_id) 00058 { 00059 switch (tc_id) { 00060 case 0: /* Fall through. */ 00061 case 1: 00062 return SYSCLK_PORT_C; 00063 00064 case 2: /* Fall through. */ 00065 case 3: 00066 return SYSCLK_PORT_D; 00067 00068 case 4: /* Fall through. */ 00069 case 5: 00070 return SYSCLK_PORT_E; 00071 00072 case 6: /* Fall through. */ 00073 case 7: 00074 return SYSCLK_PORT_F; 00075 00076 default: 00077 unhandled_case(tc_id); 00078 return 0; 00079 } 00080 } 00081 00085 static inline uint8_t tc_get_sysclk_id(uint8_t tc_id) 00086 { 00087 switch (tc_id) { 00088 case 0: /* Fall through */ 00089 case 2: 00090 case 4: 00091 case 6: 00092 return SYSCLK_TC0; 00093 00094 case 1: /* Fall through */ 00095 case 3: 00096 case 5: 00097 case 7: 00098 return SYSCLK_TC1; 00099 00100 default: 00101 unhandled_case(tc_id); 00102 return 0; 00103 } 00104 } 00105 00109 static inline void tc_enable_pclk(uint8_t tc_id) 00110 { 00111 sysclk_enable_module(tc_get_sysclk_port(tc_id), 00112 tc_get_sysclk_id(tc_id)); 00113 } 00114 00118 static inline void tc_disable_pclk(uint8_t tc_id) 00119 { 00120 sysclk_disable_module(tc_get_sysclk_port(tc_id), 00121 tc_get_sysclk_id(tc_id)); 00122 } 00123 00127 static inline bool tc_pclk_is_enabled(uint8_t tc_id) 00128 { 00129 return sysclk_module_is_enabled(tc_get_sysclk_port(tc_id), 00130 tc_get_sysclk_id(tc_id)); 00131 } 00132 00142 static inline uint32_t tc_get_pclk_hz(uint8_t tc_id) 00143 { 00144 return (uint32_t)CONFIG_CPU_HZ; 00145 } 00146 00148 00149 #endif /* CHIP_TC_H_INCLUDED */
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